Abstract: A semiconductor chip is specified that has a contact layer that is not optimum for many common applications. For example, the contact layer is too thin to tolerate an operating current intended for the semiconductor chip without considerable degradation. Also specified is an optoelectronic component in which the semiconductor chip can be integrated so that the suboptimal quality of the contact layer is compensated for. In the component the semiconductor chip is applied to a carrier body so that the contact layer is arranged on a side of the semiconductor body that is remote from the carrier body. The semiconductor chip and the carrier body are at least partly covered with an electrically isolating layer, and an electrical conductor applied to the isolating layer extends laterally away from the semiconductor body and contacts at least a partial surface of the contact layer. In addition, an advantageous process for producing the component is specified.

Abstract: A conduction element includes a substrate which has a first wave surface and a second wave surface, and a laminate film which is formed on the first wave surface and where two or more layers are laminated, where the laminate film forms a conduction pattern, and the first wave surface and the second wave surface satisfy a relationship below. 0?(Am1/?m1)<(Am2/?m2)?1.8 (Here, Am1: average width of vibration in the first wave surface, Am2: average width of vibration in the second wave surface, ?m1: average wavelength of the first wave surface, ?m2: average wavelength of the second wave surface).

Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.

Abstract: A photoelectric conversion device including a substrate, a photoelectric conversion element including a first electrode, a second electrode and an organic compound layer and a sealing member that are disposed in this order. When a cross section of the photoelectric conversion device in a thickness direction is observed with the sealing member being placed at an upper side, a bonding member seals the organic compound layer at an outside thereof. An output electrode on the sealing member has a protrusion. A side conductive portion is electrically connected with the protrusion in an up-and-down direction. A substrate conductive member electrically connected with the first electrode and the second electrode extends to an outside of the bonding member. An electrical connecting member electrically connects the side conductive portion to the substrate conductive member at a further outside of the bonding member.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor apparatus with a metallic alloy. An exemplary structure for an apparatus comprises a first silicon substrate; a second silicon substrate; and a contact connecting each of the first and second substrates, wherein the contact comprises a Ge layer adjacent to the first silicon substrate, a Cu layer adjacent to the second silicon substrate, and a metallic alloy between the Ge layer and Cu layer.

Abstract: The image sensor includes a substrate, an insulating structure formed on a first surface of the substrate and including a first metal wiring layer exposed by a contact hole penetrating the substrate, a conductive spacer formed on sidewalls of the contact hole and electrically connected to the first metal wiring layer, and a pad formed on a second surface of the substrate and electrically connected to the first metal wiring layer.

Abstract: Photodiode arrays and methods of fabrication are provided. One photodiode array includes a silicon wafer having a first surface and an opposite second surface and a plurality of conductive vias through the silicon wafer. The photodiode array further includes a patterned doped epitaxial layer on the first surface, wherein the patterned doped epitaxial layer and the substrate form a plurality of diode junctions. A patterned etching defines an array of the diode junctions.

Abstract: An embodiment of the invention relates to a TFT-LCD array substrate comprising a substrate, a gate line and a data line formed on the substrate, a pixel electrode and a thin film transistor formed in a pixel region defined by the gate line and the data line, wherein the thin film transistor comprises a gate electrode, a source electrode, and a transparent drain electrode, and the transparent drain electrode is electrically connected with the pixel electrode.

Abstract: An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary diode comprises: a light emitting or absorbing region having a diameter between about 20 and 30 microns and a height between about 2.5 to 7 microns; a first terminal coupled to the light emitting region on a first side, the first terminal having a height between about 1 to 6 microns; and a second terminal coupled to the light emitting region on a second side opposite the first side, the second terminal having a height between about 1 to 6 microns.

Abstract: A germanium semiconductor radiation detector contact made of yttrium metal. A thin (˜1000 ?) deposited layer of yttrium metal forms a thin hole-barrier and/or electron-barrier contact on both p- and n-type germanium semiconductor radiation detectors. Yttrium contacts provide a sufficiently high hole barrier to prevent measurable contact leakage current below ˜120 K. The yttrium contacts can be conveniently segmented into multiple electrically independent electrodes having inter-electrode resistances greater than 10 G?. Germanium semiconductor radiation detector diodes fabricated with yttrium contacts provide good gamma-ray spectroscopy data.

Abstract: Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.

Abstract: An insulating layer is layered above a substrate, and a plurality of pixel electrodes are formed above the insulating layer in a matrix with intervals therebetween. A photoelectric conversion layer and an opposing electrode are formed in respective order above the pixel electrodes. A dummy layer is formed above the insulating layer in a region that in plan-view is more peripheral than a pixel region in which the pixel electrodes are formed. The dummy layer is formed from the same material as the pixel electrodes. The dummy layer is composed of a plurality of dummy layer portions that are each equal to each of the pixel electrodes in terms of size in plan-view. The dummy layer functions as a support layer for planarization during polishing by chemical mechanical polishing.

Abstract: A semiconductor device that includes a first metal layer component formed over a substrate. The semiconductor device includes a via formed over the first metal layer component. The via has a recessed shape. The semiconductor device includes a second metal layer component formed over the via. The semiconductor device includes a first dielectric layer component formed over the substrate. The first dielectric layer component is located adjacent to, and partially over, the first metal layer component. The first dielectric layer component contains fluorine. The semiconductor device includes a second dielectric layer component formed over the first dielectric layer component. The first dielectric layer component and the second dielectric layer component are each located adjacent to the via. The second dielectric layer component is free of fluorine.

Abstract: A radiation detector module (22) particularly well suited for use in computed tomography (CT) applications includes a scintillator (200), a photodetector array (202), and signal processing electronics (205). The photodetector array (202) includes a semiconductor substrate (208) having a plurality of photodetectors and metalization (210) fabricated on non-illuminated side of the substrate (208). The metalization routes electrical signals between the photodetectors and the signal processing electronics (205) and between the signal processing electronics (205) and an electrical connector (209).

Abstract: A semiconductor device includes a device substrate having a front side and a back side corresponding to a front side and a back side of the semiconductor device, a metal feature formed on the front side of the device substrate, a bonding pad disposed on the back side of the semiconductor device and in electrical communication with the metal feature, and a shield structure disposed on the back side of the device substrate in which the shield structure and the bonding pad have different thicknesses relative to each other.

Abstract: A three-dimensional integrated circuit device includes a first substrate having a first crystal orientation comprising at least one or more PMOS devices thereon and a first dielectric layer overlying the one or more PMOS devices. The three-dimensional integrated circuit device also includes a second substrate having a second crystal orientation comprising at least one or more NMOS devices thereon; and a second dielectric layer overlying the one or more NMOS devices. An interface region couples the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate.

Abstract: Flexible lateral p-i-n (“PIN”) diodes, arrays of flexible PIN diodes and imaging devices incorporating arrays of PIN diodes are provided. The flexible lateral PIN diodes are fabricated from thin, flexible layers of single-crystalline semiconductor. A plurality of the PIN diodes can be patterned into a single semiconductor layer to provide a flexible photodetector array that can be formed into a three-dimensional imaging device.

Abstract: A semiconductor light receiving device includes: a substrate having a rectangular shape with first through fourth corners, a multilayer structure formed on the substrate, a light receiving part having a mesa structure positioned at a first corner side from a center part of the rectangular shape of the substrate, a first electrode pad provided on the semiconductor substrate, and a second electrode pad provided on the semiconductor substrate so as to be close to a second corner diagonally opposite to the first corner, a first minimum distance between the second electrode pad and an edge of the substrate being longer than a second minimum distance between the first electrode pad and the edge of the substrate.

Abstract: An electrode includes a substantially planar metallic thin film layer with a patterned structure including a plurality of parallel lines or a plurality of crossed lines, the metallic thin film layer configured to transmit an incident light through the metallic thin film layer.

Abstract: A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads.

Abstract: The invention is directed to providing a semiconductor device receiving a blue-violet laser, of which the reliability and yield are enhanced. A device element converting a blue-violet laser into an electric signal is formed on a front surface of a semiconductor substrate. An optically transparent substrate is attached to the front surface of the semiconductor substrate with an adhesive layer being interposed therebetween. The adhesive layer contains transparent silicone. Since the front surface of the device element is covered by the optically transparent substrate, foreign substances are prevented from adhering to the front surface of the device element. Furthermore, the adhesive layer is covered by the optically transparent substrate. This prevents the adhesive layer from being exposed to outside air, thereby preventing the degradation of the adhesive layer 6 due to a blue-violet laser.

Abstract: A semiconductor package includes a semiconductor substrate which includes a first connection terminal electrically connected to a wiring for signal transfer. The semiconductor package may include a semiconductor support substrate which may be bonded to the semiconductor substrate such that a second connection terminal and the first connection terminal are connected to face each other, and has a through via exposing the second connection terminal.

Abstract: An optoelectronic semiconductor chip includes a carrier including a carrier element having a mounting side; one electrically conductive n-type wiring layer arranged at the mounting side; a structured, electrically conductive contact layer having a p-side and n-side contact region and arranged at a side of the n-type wiring layer facing away from the carrier element; at least one insulation region electrically insulating the p-side contact region from the n-side contact region; at least one electrically insulating spacer layer arranged at a side of the n-type wiring layer facing away from the carrier element in a vertical direction between the p-side contact region and the n-type wiring layer, wherein the n-side contact region and the n-type wiring layer electrically conductively connect to one another, and the p-side contact region and the spacer layer border the n-side contact region in a lateral direction; an optoelectronic structure connected to the carrier.

Abstract: A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step.

Abstract: At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise.

Abstract: A method of manufacturing a semiconductor device includes forming at least one sacrificial layer on a substrate during a complementary metal-oxide-semiconductor (CMOS) process. An absorber layer is deposited on top of the at least one sacrificial layer. A portion of the at least one sacrificial layer beneath the absorber layer is removed to form a gap over which a portion of the absorber layer is suspended. The sacrificial layer can be an oxide of the CMOS process with the oxide being removed to form the gap using a selective hydrofluoric acid vapor dry etch release process. The sacrificial layer can also be a polymer layer with the polymer layer being removed to form the gap using an O2 plasma etching process.

Abstract: There is provided a semiconductor device including a substrate made from a semiconductor material, and layers that are made from plural kinds of materials and formed over the substrate. An opening portion that is formed to penetrate at least a layer formed as an insulating film among the layers formed over the substrate and expose a surface of an electrode pad is filled with aluminum or an aluminum alloy.

Abstract: Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.

Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.

Abstract: A mounting substrate includes: a wiring substrate; and a plurality of optical elements mounted on a mounting surface of the wiring substrate, and each having a first electrode and a second electrode. The wiring substrate includes a support substrate, a plurality of first wires, and a plurality of second wires. The first wires and the second wires are provided within a layer between the support substrate and the mounting surface. The first wires are electrically connected with the first electrodes. The second wires are electrically connected with the second electrodes, and each have cross-sectional area larger than cross-sectional area of each of the first wires.

Abstract: Described are embodiments of apparatuses and systems including photonic devices having a conductive shunt layer, and methods for making such apparatuses and systems. A photonic device may include a device substrate, a photo-active region disposed on a first region of the device substrate, an isolation region in the device substrate, a contact disposed on a second region of the substrate such that the isolation region is located between the contact and the photo-active region, and a conductive material overlying the isolation region to shunt the first region with the second region. Other embodiments may be described and/or claimed.

Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.

Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate having a test pad with element pads; forming a conductive layer over the test pad, the conductive layer having element layers directly on the element pads; and mounting an integrated circuit over the substrate.

Abstract: Controlled-impedance out-of-substrate package structures employing electrical devices and related assemblies, components, and methods are disclosed. An out-of-substrate package structure may be used to electrically couple an electrical device to an electrical substrate, for example a printed circuit board. The out-of-substrate package structure may be electrically coupled to the electrical substrate. Ground paths of the out-of-substrate package structure may be arranged proximate to the electrical device and arranged symmetric with respect to at least one geometric plane intersecting the electrical device. In this regard, electric field lines generated by current flowing into the electrical device tend to terminate at the return or ground paths allowing for impedance to be more easily controlled. Accordingly, the out-of-substrate package structure may be impedance matched in a better way with respect to power provided from the electrical substrate enabling faster electrical device speeds.

Abstract: The invention relates to a substantially transparent electronic device comprising a first contact surface provided with a first pattern of electrically conductive lines and a second contact surface provided with a second pattern of electrically conductive lines, the first contact surface extending parallel to the second contact surface, wherein the first pattern is rotationally displaced with respect to the second pattern by an angle between 15 and 165 degrees. The electrically conductive lines of the said first pattern and the said second pattern are substantially not transparent for visible light and are preferably used as shunting lines. The invention further relates to a method of manufacturing such device.

Abstract: A photoelectric conversion device includes: a first substrate of which end portions are cut off so as to slope or with a groove shape; a photodiode and an amplifier circuit over the first substrate; a first electrode electrically connected to the photodiode and provided over one end portion of the first substrate; a second electrode electrically connected to the amplifier circuit and provided over an another end portion of the first substrate; and a second substrate having third and fourth electrodes thereon. The first and second electrodes are attached to the third and fourth electrodes, respectively, with a conductive material provided not only at the surfaces of the first, second, third, and fourth electrodes facing each other but also at the side surfaces of the first and second electrodes to increase the adhesiveness between a photoelectric conversion device and a member on which the photoelectric conversion device is mounted.

Abstract: A combined diode, lead assembly incorporating two expansion joints. The combined diode, lead assembly incorporating two expansion joints includes a diode having a first diode terminal and a second diode terminal, a first conductor and a second conductor. The first conductor includes a first terminal that is electrically coupled to the diode at the first diode terminal and a second terminal that is configured as a first expansion joint, which is configured to electrically couple to a first interconnecting-conductor and is configured to reduce a stress applied to the diode by the first conductor. The second conductor includes a first terminal that is electrically coupled to the diode at the second diode terminal and a second terminal that is configured as a second expansion joint, which is configured to electrically couple to a second interconnecting-conductor and is configured to reduce a stress applied to the diode by the second conductor.

Abstract: A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region and above the first pattern, and microlenses provided above the photoelectric conversion elements with the first and the second patterns provided therebetween. The photoelectric conversion device further has convex-shaped interlayer lenses in optical paths between the photoelectric conversion elements and the microlenses, the peak of each convex shape projecting in the direction from the electro-optical element to the microlens.

Abstract: A semiconductor device comprising a first semiconductor section including a first wiring layer at one side thereof, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other, a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication.

Abstract: Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.

Abstract: There is provided a solid-state imaging device including a sensor substrate having a sensor-side semiconductor layer including a pixel region in which a photoelectric conversion section is provided and a sensor-side wiring layer provided on an opposite surface side from a light receiving surface of the sensor-side semiconductor layer, a circuit substrate having a circuit-side semiconductor layer and a circuit-side wiring layer and provided on a side of the sensor-side wiring layer of the sensor substrate, a connection unit region in which a connection section is provided, the connection section having a first through electrode, a second through electrode, and a connection electrode connecting the first through electrode and the second through electrode, and an insulating layer having a step portion which has the connection electrode embedded therein and has a film thickness that gradually decreases from the connection unit region to the pixel region.

Abstract: An image sensor includes a substrate having a front side and a back side, an insulating structure containing circuits on the front side of the substrate, contact holes extending through the substrate to the circuits, respectively, and a plurality of pads disposed on the backside of the substrate, electrically connected to the circuits along conductive paths extending through the contact holes, and located directly over the circuits, respectively. The image sensor is fabricated by a process in which a conductive layer is formed on the back side of the substrate and patterned to form the pads directly over the circuits.

Abstract: A structure of stacking chips and a method for manufacturing the structure of stacking chips are provided. A wafer with optical chips and a glass substrate with signal processing chips are stacked with each other, and then subjected to ball mounting and die sawing to form the stacked packaging structure. The optical chips and the signal processing chips form the electrical connection on the surface of the glass substrate via the through holes thereof.

Abstract: The present invention relates generally to dendritic metal structures and devices including them. The present invention also relates particularly to methods for making dendritic metal structures without the use of solid electrolyte materials. In one aspect, a method for constructing a dendritic metal structure includes providing a substrate having a surface and a cathode disposed on the surface; providing an anode comprising a metal; and disposing a liquid on the surface of the substrate, such that the liquid is in electrical contact with the anode and the cathode; and then applying a bias voltage across the cathode and the anode sufficient to grow the dendritic metal structure extending from the cathode. The methods described herein can be used to grow dedritic metal electrodes, which can be useful in devices such as LEDs, touchscreens, solar cells and photodetectors.

Abstract: An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape.

Abstract: The present invention relates to an apparatus combining bypass diode and wire. According to the present invention, the bypass diode can connect with the wire directly. It is not necessary to reserve an extra region on the substrate of the solar cell as the wire soldering area. Thereby, the required area of the ceramic substrate is reduced, and hence lowering the manufacturing cost of the solar cell substantially.

Abstract: A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly beyond the perimeter of the solder bump, wherein an edge of the bump is aligned vertically to coincide with the gap separating the conductive bond pad from the topographical feature. The topographical feature provides thickness enhancement of a non-conductive layer disposed over the semiconductor die and the conductive bond pad and stress buffering.

Abstract: An integrated circuit structure includes an interconnect structure that includes a plurality of metal layers, wherein the interconnect structure is under a semiconductor substrate. A metal pad is formed in one of the plurality of metal layers. A dielectric pad extends from a bottom surface of the semiconductor substrate up into the semiconductor substrate. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate and the dielectric pad. An edge of the semiconductor substrate in the opening is vertically aligned to an edge of the dielectric pad in the opening. The opening stops on a top surface of the metal pad. A dielectric spacer is disposed in the opening, wherein the dielectric spacer is formed on the edge of the semiconductor substrate and the edge of the dielectric pad.

Abstract: An organic light-emitting device cutting off ambient light while keeping emission intensity includes a pair of first and second electrodes opposed to each other; and a plurality of organic semiconductor layers layered and disposed between the first and second electrodes, wherein the organic semiconductor layers include an organic light-emitting layer, the organic semiconductor device further comprising a light-scattering layer layered and disposed between the organic light-emitting layer and at least one of the first and second electrodes. The light-scattering layer includes: organic materials having carrier injection and transport characteristics of transporting electrons and/or holes; and plural particles dispersed among the organic materials so that light emitted from the organic light-emitting layer is passed therethrough.

Abstract: A semiconductor unit includes: a first device substrate including a first semiconductor substrate and a first wiring layer, in which the first wiring layer is provided on one surface side of the first semiconductor substrate; a second device substrate including a second semiconductor substrate and a second wiring layer, in which the second device substrate is bonded to the first device substrate, and the second wiring layer is provided on one surface side of the second semiconductor substrate; a through-electrode penetrating the first device substrate and a part or all of the second device substrate, and electrically connecting the first wiring layer and the second wiring layer to each other; and an insulating layer provided in opposition to the through-electrode, and penetrating one of the first semiconductor substrate and the second semiconductor substrate.