With Particular Contact Geometry (e.g., Ring Or Grid, Or Bonding Pad Arrangement) Patents (Class 257/459)
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Patent number: 8008786Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.Type: GrantFiled: July 1, 2010Date of Patent: August 30, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Tim V. Pham, Trent S. Uehling
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Publication number: 20110198719Abstract: An electronic device having a plurality of electronic components placed on a substrate, each component being constituted by a portion of a layer of active material joined mechanically to the substrate by an electrically conductive joining element pertinent to it, the layer of active material having at least one trench delimiting, at least in part, groups of electronic components each having at least two components and forming successive strips, two successive strips having a common boundary.Type: ApplicationFiled: July 6, 2009Publication date: August 18, 2011Applicant: ETAT FRANCAIS REPRESENTE PAR LE DELEGUE GENERAL POUR L'ARMEMENTInventor: Pierre Burgaud
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Patent number: 7999344Abstract: An optoelectronic device comprises a photodetector feature, an interfacial layer disposed above at least a portion of the photodetector feature, and a vertical contact disposed on at least a portion of the interfacial layer. The photodetector feature comprises germanium and is operative to convert a light signal into an electrical signal. The interfacial layer comprises nickel. Finally, the vertical contact is operative to transmit the electrical signal from the photodetector feature.Type: GrantFiled: May 6, 2010Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Solomon Assefa, Stephen Walter Bedell, Yurii A. Vlasov, Fengnian Xia
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Patent number: 7994464Abstract: A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the capacitor to change the conversion gain of the floating diffusion region from a first conversion gain to a second conversion gain. In order to increase the efficient use of space, the dual conversion gain element gate also functions as the bottom plate of the capacitor. In one particular embodiment of the invention, a high dynamic range transistor is used in conjunction with a pixel cell having a capacitor-DCG gate combination; in another embodiment, adjacent pixels share pixel components, including the capacitor-DCG combination.Type: GrantFiled: February 12, 2010Date of Patent: August 9, 2011Assignee: Micron Technology, Inc.Inventor: Jeffrey A. McKee
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Patent number: 7989907Abstract: Provided is a backside-illuminated solid-state image pickup device capable of allowing peripheral circuits to produce stable waveforms and thereby achieving image characteristics with less noise, the device including: a first-conductivity-type semiconductor layer having a first principal surface and a second principal surface opposed to the first principal surface and also having a pixel area and an analog circuit area; a first P type area formed to lie between the second principal surface and the first principal surface in the analog circuit area; a metal layer formed at least partially on the second principal surface of the first P type area; a VSS electrode electrically connected to the metal layer; a photo-conversion area formed in the pixel area and used to accumulate electric charges generated by photoelectric conversion; and a microlens provided on the second principal surface in the pixel area so as to correspond to the photo-conversion area.Type: GrantFiled: October 16, 2009Date of Patent: August 2, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Ikuko Inoue
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Patent number: 7989909Abstract: An image sensor module includes a semiconductor chip. Photodiode units are disposed in an active region of the semiconductor chip to convert light into electric signals. Pads are disposed in a peripheral region formed around the active region and the pads are electrically connected to the photodiode units. A connecting region is formed around the peripheral region. Re-distribution layers are electrically connected to respective pads and extend to the connecting region. A transparent substrate covers the photodiode units and the pads and exposes at least a portion of the re-distribution layers. Connecting layers are electrically connected to the respective re-distribution layers and extend to a top surface of the transparent substrate. Connecting members are connected to the respective connecting layers disposed on the top surface of the transparent substrate.Type: GrantFiled: December 8, 2008Date of Patent: August 2, 2011Assignee: Hynix Semiconductor Inc.Inventor: Sung Min Kim
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Publication number: 20110180895Abstract: Disclosed is a method of manufacturing a CMOS image sensor, capable of preventing hillock-type defects caused by the delamination of interconnections from occurring in the CMOS image sensor.Type: ApplicationFiled: June 10, 2009Publication date: July 28, 2011Applicant: CROSSTEK CAPITAL, LLCInventor: Sung-Gyu Pyo
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Publication number: 20110169122Abstract: Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment includes providing a substrate comprising a via formed therein. The substrate has a front side and a backside. The embodiment may further include forming a trench on the backside of the substrate, disposing an insulating material in the trench, and forming a trace over the insulating material in the trench.Type: ApplicationFiled: March 25, 2011Publication date: July 14, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Steve Oliver, Warren Farnworth
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Patent number: 7977233Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.Type: GrantFiled: August 16, 2010Date of Patent: July 12, 2011Assignee: Seiko Epson CorporationInventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
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Patent number: 7977141Abstract: A method of manufacturing a solid-state image pickup device according to an embodiment includes forming first and second holes in a semiconductor substrate, forming insulating films on surfaces of the first and second holes, forming a contact and an alignment mark by embedding a conducting material in the first and second holes, forming a photodiode in the semiconductor substrate, forming a wiring layer including a connecting part for connecting to the contact and a wiring for connecting to the connecting part, bonding a supporting substrate on the wiring layer, exposing the contact and the alignment mark on the surface of the semiconductor substrate by reducing the semiconductor substrate in thickness, and forming a filter and a lens on the photodiode based on the alignment mark.Type: GrantFiled: August 31, 2009Date of Patent: July 12, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tsubasa Harada, Atsushi Murakoshi
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Patent number: 7956435Abstract: In recent years, as electronic equipment becomes thinner, an area for mounting a semiconductor device used in the electronic equipment is required to be smaller, and a thickness of an encapsulating resin for encapsulating a semiconductor substrate having a circuit formed thereon and the like also becomes smaller. The encapsulating resin is marked with a product number, a manufacturer name, or the like. There arises a problem in that, in the marking, an infrared laser beam applied to the encapsulating resin passes through the encapsulating resin, generates heat in the semiconductor substrate, and destructs the formed circuit. By providing a thin film for refracting the infrared laser beam on a rear surface of the semiconductor substrate, the optical path of the infrared laser beam is made longer to reduce heat generated in the semiconductor substrate.Type: GrantFiled: February 12, 2009Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventor: Tomohiro Kamimura
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Patent number: 7948006Abstract: A photodetector with an improved electrostatic discharge damage threshold is disclosed, suitable for applications in telecommunication systems operating at elevated data rates. The photodetector may be a PIN or an APD fabricated in the InP compound semiconductor system. The increased ESD damage threshold is achieved by reducing the ESD induced current density in the photodetector by a suitable widening of the contact at a critical location, increasing the series resistance and promoting lateral current spreading by means of a current spreading layer.Type: GrantFiled: June 1, 2009Date of Patent: May 24, 2011Assignee: JDS Uniphase CorporationInventors: Zhong Pan, David Venables
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Publication number: 20110102657Abstract: A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.Type: ApplicationFiled: October 22, 2010Publication date: May 5, 2011Applicant: SONY CORPORATIONInventors: Hiroshi Takahashi, Taku Umebayashi
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Patent number: 7932512Abstract: Fabrication of a photonic integrated circuit (PIC) including active elements such as a semiconductor optical amplifier (SOA) and passive elements such as a floating rib waveguide. Selective area doping through ion implantation or thermal diffusion before semiconductor epitaxial growth is used in order to define the contact and lateral current transport layers for each active device, while leaving areas corresponding to the passive devices undoped. InP wafers are used as the substrate which may be selectively doped with silicon.Type: GrantFiled: September 27, 2006Date of Patent: April 26, 2011Assignee: HRL Laboratories, LLCInventors: Yakov I. Royter, Rajesh D. Rajavel, Stanislav I. Ionov, Irina Ionova, legal representative, Sophi Ionova, legal representative
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Patent number: 7928318Abstract: A solar cell includes a p-type semiconductor substance, and an n-type semiconductor substance. The p-type semiconductor substance and the n-type semiconductor substance form a pn junction or a pin junction, and the p-type semiconductor substance or the n-type semiconductor substance includes a structure film having a plurality of carbon nanotubes electrically connected to each other.Type: GrantFiled: July 28, 2005Date of Patent: April 19, 2011Assignee: Fuji Xerox Co., Ltd.Inventors: Kei Shimotani, Chikara Manabe, Takashi Morikawa
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Publication number: 20110073980Abstract: A light detecting apparatus is provided with a semiconductor substrate, a first electrode layer, and a second electrode layer. The semiconductor substrate has a first conductivity type first semiconductor region, and a second conductivity type second semiconductor region formed on the first semiconductor region and constituting a photodiode based on a pn junction formed between the first semiconductor region and the second semiconductor region. The first electrode layer is arranged above the second semiconductor region so as to be opposed to the second semiconductor region and is electrically connected to the second semiconductor region. The second electrode layer is arranged above the first electrode layer so as to be opposed to the first electrode layer and forms a capacitance component connected to the photodiode, between the first electrode layer and the second electrode layer.Type: ApplicationFiled: September 23, 2010Publication date: March 31, 2011Applicant: HAMAMATSU PHOTONICS K.K.Inventor: Takashi SUZUKI
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Publication number: 20110073981Abstract: The present invention provides a semiconductor device formed over an insulating substrate, typically a semiconductor device having a structure in which mounting strength to a wiring board can be increased in an optical sensor, a solar battery, or a circuit using a TFT, and which can make it mount on a wiring board with high density, and further a method for manufacturing the same. According to the present invention, in a semiconductor device, a semiconductor element is formed on an insulating substrate, a concave portion is formed on a side face of the semiconductor device, and a conductive film electrically connected to the semiconductor element is formed in the concave portion.Type: ApplicationFiled: December 10, 2010Publication date: March 31, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kazuo NISHI, Hiroki ADACHI, Junya MARUYAMA, Naoto KUSUMOTO, Yuusuke SUGAWARA, Tomoyuki AOKI, Eiji SUGIYAMA, Hironobu TAKAHASHI
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Patent number: 7911068Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.Type: GrantFiled: July 13, 2006Date of Patent: March 22, 2011Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Harry Hedler, Markus Brunnbauer
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Patent number: 7911019Abstract: A reflowable camera module has a set of solder joints formed on a bottom surface of the camera module that provide electrical signal and power connections between the camera module and a printed circuit substrate. The solder joints are susceptible to failure caused by shear forces, particularly in corner regions. Additional localized mechanical supports are provided to protect those solder joints carrying power and electrical signals for the camera module. The localized mechanical supports are formed outside of a region containing the solder joints carrying power and electrical signals. The localized mechanical supports may include dummy solder joints formed in corner regions and/or dummy leads used to support the camera module. Solder joint reliability is enhanced without requiring the use of an underfill encapsulant.Type: GrantFiled: March 16, 2010Date of Patent: March 22, 2011Assignee: OmniVision Technologies, Inc.Inventors: Jari Hiltunen, Ian Montandon
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Publication number: 20110062334Abstract: A novel pixel circuit and multi-dimensional array for receiving and detecting black body radiation in the SWIR, MWIR or LWIR frequency bands. An electromagnetic thermal sensor and imaging system is provided based on the treatment of thermal radiation as an electromagnetic wave. The thermal sensor and imager functions essentially as an electromagnetic power sensor/receiver, operating in the SWIR (200-375 THz), MWIR (60-100 THz), or LWIR (21-38 THz) frequency bands. The thermal pixel circuit of the invention is used to construct thermal imaging arrays, such as 1D, 2D and stereoscopic arrays. Various pixel circuit embodiments are provided including balanced and unbalanced, biased and unbiased and current and voltage sensing topologies. The pixel circuit and corresponding imaging arrays are constructed on a monolithic semiconductor substrate using in a stacked topology. A metal-insulator-metal (MIM) structure provides rectification of the received signal at high terahertz frequencies.Type: ApplicationFiled: September 13, 2010Publication date: March 17, 2011Inventor: David Ben-Bassat
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Publication number: 20110062541Abstract: The present invention relates to novel compounds that are useful as ligands in organometallic dyes. More particularly, the invention relates to dyes comprising the compounds, said dyes being sensitizing dyes useful in solar cell technology. According to an embodiment, the present invention discloses new ruthenium dyes and their application in dye-sensitized solar cells (DSC). The referred ruthenium dyes with new structural features can be easily synthesized, show more than 85% light-to-electricity conversion efficiency and a higher than 9% cell efficiency.Type: ApplicationFiled: February 27, 2009Publication date: March 17, 2011Inventors: Feifei Gao, Yuan Wang, Jing Zhang, Peng Wang, shaik Mohammad Zakeeruddin, Michael Graetzel
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Publication number: 20110057283Abstract: To provide a photoelectric conversion element that allows connection between adjacent photoelectric conversion elements by use of an inexpensive wiring member.Type: ApplicationFiled: July 25, 2008Publication date: March 10, 2011Inventors: Akiko Tsunemi, Satoshi Okamoto
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Publication number: 20110057284Abstract: A digital image sensor includes a planar substrate with one or more bonding pads on one side and a silicon chip with one or more bonding pads. The silicon chip is attached on the planar substrate through the one or more bonding pads. The attachment of the silicon chip to the planar substrate is performed in a manner such that the silicon chip, when attached, has a curved shape.Type: ApplicationFiled: September 3, 2010Publication date: March 10, 2011Applicant: STMicroelectronics (Research & Development) LimitedInventor: Douglas Stuart Brodie
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Publication number: 20110049665Abstract: An image pickup device includes a plurality of first electrodes, a second electrode, a third electrode, a photoelectric conversion layer, a plurality of signal reading portions, at least one of electric potential adjusting portions. The plurality of first electrodes is arranged on an upper side of a substrate in two dimensions with a predetermined gap interposed between one of the first electrodes and another first electrode adjacent to the one of the first electrode. The second electrode is arranged next to the first electrodes arranged on an outermost side of the first electrodes with the predetermined gap interposed between the first electrodes arranged on the outermost side and the second electrode. The third electrode faces both of the plurality of first electrodes and the second electrode. The photoelectric conversion layer is disposed between the plurality of first electrodes and the second electrode and the third electrode.Type: ApplicationFiled: August 31, 2010Publication date: March 3, 2011Applicant: FUJIFILM CORPORATIONInventor: Takashi GOTO
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Publication number: 20110049336Abstract: A solid-state imaging device includes: a plurality of substrates stacked via a wiring layer or an insulation layer; a light sensing section that is formed in a substrate, of the plurality of substrates, disposed on a light incident side and that generates a signal charge in accordance with an amount of received light; and a contact portion that is connected to a non-light incident-surface side of the substrate in which the light sensing section is formed and that supplies a desired voltage to the substrate from a wire in a wiring layer disposed on a non-light incident side of the substrate.Type: ApplicationFiled: August 20, 2010Publication date: March 3, 2011Applicant: SONY CORPORATIONInventor: Takeshi Matsunuma
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Patent number: 7888762Abstract: There is provided an infrared detector including: a silicon substrate provided with a concave portion; an infrared receiver having a polysilicon layer; and a beam that supports the infrared receiver above the concave portion, and extends along a side of the infrared receiver from the infrared receiver to connect with the silicon substrate, the beam having at least two bent portions, wherein at least one of the bent portions of the beam is disposed at a position on a side opposite to the concave portion with the polysilicon layer as a reference point.Type: GrantFiled: December 19, 2008Date of Patent: February 15, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Kazuhide Abe
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Patent number: 7883998Abstract: It is to provide a vapor phase growth method in which an epitaxial layer consisting of a compound semiconductor such as InAlAs, can be grown, with superior reproducibility, on a semiconductor substrate such as Fe-doped InP. In vapor phase growth method for growing an epitaxial layer on a semiconductor substrate, a resistivity of the semiconductor substrate at a room temperature is previously measured, a set temperature of the substrate is controlled depending on the resistivity at the room temperature such that a surface temperature of the substrate is a desired temperature regardless of the resistivity of the semiconductor substrate, and the epitaxial layer is grown.Type: GrantFiled: February 15, 2005Date of Patent: February 8, 2011Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Masashi Nakamura, Suguru Oota, Ryuichi Hirano
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Publication number: 20110024866Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.Type: ApplicationFiled: July 29, 2009Publication date: February 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Uway Tseng, Lin-June Wu, Yu-Ting Lin
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Publication number: 20110024867Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.Type: ApplicationFiled: November 11, 2009Publication date: February 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Uway Tseng, Lin-June Wu, Yu-Ting Lin
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Patent number: 7880258Abstract: The present invention is directed toward a detector structure, detector arrays, and a method of detecting incident radiation. The present invention comprises several embodiments that provide for reduced radiation damage susceptibility, decreased affects of crosstalk, reduced dark current (current leakage) and increased flexibility in application. In one embodiment, a photodiode array comprises a substrate having at least a front side and a back side, a plurality of diode elements integrally formed in the substrate forming the array, wherein each diode element has a p+ fishbone pattern on the front side, and wherein the p+ fishbone pattern substantially reduces capacitance and crosstalk between adjacent photodiodes, a plurality of front surface cathode and anode contacts, and wire interconnects between diode elements made through a plurality of back surface contacts.Type: GrantFiled: March 16, 2005Date of Patent: February 1, 2011Assignee: UDT Sensors, Inc.Inventors: Peter Steven Bui, Narayan Dass Taneja
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Publication number: 20110019709Abstract: The present invention provides a method of manufacturing a semiconductor device realizing improved yield. The semiconductor device includes: a substrate having a top face, an under face, and side faces; an optical function unit formed on the top face; a plurality of electrode pads formed on the under face; and a wiring formed on at least the side face and electrically connecting the optical function unit and at least one of the plurality of electrode pads.Type: ApplicationFiled: July 8, 2010Publication date: January 27, 2011Applicant: Sony CorporationInventors: Yuji Masui, Takahiro Arakida, Naoki Jogan, Rintaro Koda, Kouichi Kondo
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Patent number: 7863705Abstract: A bonding pad structure in a semiconductor device includes a contact pad connected to an interconnect, a bonding pad overlying the contact pad with an intervention of an insulating film and exposed from an opening of a passivation film, and an annular contact disposed between the contact pad and the bonding pad for electric connection therebetween. The annular contact encircles the opening as viewed normal to the substrate surface.Type: GrantFiled: November 23, 2005Date of Patent: January 4, 2011Assignee: Elpida Memory, Inc.Inventor: Yasushi Yamazaki
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Patent number: 7851836Abstract: A photosensor includes a semiconductor thin film for photoelectric conversion having a first side portion and a second side portion. A source electrode extends in the longitudinal direction of the semiconductor thin film and has a side edge portion that overlaps the first side portion of the semiconductor thin film, and a drain electrode extends in the longitudinal direction and has a side edge portion that overlaps the second side portion of the semiconductor thin film. At least one of the side edge portions of the source and drain electrodes has protruding portions which are arranged along the longitudinal direction and which overlap the semiconductor thin film, and notched portions formed between the protruding portions. An ohmic contact layer is formed between the semiconductor thin film and the protruding portions of the at least one of the side edge portions of the source and drain electrodes.Type: GrantFiled: December 20, 2007Date of Patent: December 14, 2010Assignee: Casio Computer Co., Ltd.Inventors: Hiroshi Matsumoto, Ikuhiro Yamaguchi, Hirokazu Kobayashi
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Publication number: 20100308431Abstract: In accordance with the disclosure, a MEMS substrate is provided that includes: a central planar portion configured to support a MEMS device; and a first electrical pad coplanar with the central planar portion, the first pad being connected to the central planar portion through a first flexure, wherein the first flexure is configured to substantially mechanically isolate the first electrical pad from the central planar portion.Type: ApplicationFiled: May 28, 2010Publication date: December 9, 2010Applicant: Siimpel CorporationInventors: Roman C. Gutierrez, Robert J. Calvet
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Publication number: 20100308430Abstract: A semiconductor device comprises a semiconductor substrate, and a multilayer wiring structure arranged on the semiconductor substrate, the multilayer wiring structure including a plurality of first electrically conductive lines, an insulating film covering the plurality of first electrically conductive lines, and a second electrically conductive line arranged on the insulating film so as to intersect the plurality of first electrically conductive lines, wherein the insulating film has gaps in at least some of a plurality of regions where the plurality of first electrically conductive lines and the second electrically conductive line intersect each other, and a width of the gap in a direction along the second electrically conductive line is not larger than a width of the first electrically conductive line.Type: ApplicationFiled: May 19, 2010Publication date: December 9, 2010Applicant: CANON KABUSHIKI KAISHAInventor: Takeshi Aoki
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Publication number: 20100301441Abstract: A photodetector with an improved electrostatic discharge damage threshold is disclosed, suitable for applications in telecommunication systems operating at elevated data rates. The photodetector may be a PIN or an APD fabricated in the InP compound semiconductor system. The increased ESD damage threshold is achieved by reducing the ESD induced current density in the photodetector by a suitable widening of the contact at a critical location, increasing the series resistance and promoting lateral current spreading by means of a current spreading layer.Type: ApplicationFiled: June 1, 2009Publication date: December 2, 2010Inventors: Zhong PAN, David Venables
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Patent number: 7843019Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.Type: GrantFiled: August 31, 2006Date of Patent: November 30, 2010Assignee: Micrel, IncorporatedInventors: Shekar Mallikarjunaswamy, Martin Alter
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Publication number: 20100289104Abstract: A photosensor package includes a substrate assembly, a photosensor chip mounted at the substrate assembly, a solder ball to electrically connect the photosensor chip, the substrate assembly and a printed circuit board, and a passive device mounted at the substrate assembly. Since the passive device is disposed on the substrate assembly of the photosensor package, it is possible to reduce the size of the printed circuit board compared to the convention technology where the passive device is disposed on the print circuit board. Furthermore, since it is possible to reduce a distance between the photosensor chip and the passive device, the electrical properties are also improved, and the number of processes may be reduced.Type: ApplicationFiled: May 13, 2010Publication date: November 18, 2010Applicant: OPTOPAC CO., LTD.Inventors: Jeong Seok RA, Jin Kwan KIM, Hui Tae KIM, Gi Tae LIM
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Patent number: 7834359Abstract: The invention enhances a production yield of a display device (an electro-optical device). The invention provides a method of manufacturing an electro-optical device including a display region in which a plurality of basic pixels are arranged, each basic pixel including a plurality of color pixels. The method includes: forming on a first substrate lines to drive a plurality of electro-optical elements respectively constituting the color pixels, correspondingly to the arrangement of the basic pixels; forming on a second substrate, as a chip to be transferred to each basic pixel, a drive circuit to drive the plurality of electro-optical elements which constitutes the plurality of color pixels of the basic pixels to obtain a plurality of basic-pixel driving chips; and transferring step of transferring the respective basic-pixel driving chips from the second substrate onto the first substrate, and connecting the drive circuits to regions of the lines corresponding to the basic pixels.Type: GrantFiled: December 18, 2006Date of Patent: November 16, 2010Assignee: Seiko Epson CorporationInventor: Mutsumi Kimura
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Patent number: 7834413Abstract: The present invention relates to a semiconductor photodetector and the like that can be made adequately compact while maintaining mechanical strength. The semiconductor photodetector includes a structural body of layers and a glass substrate. The structural body of layers is arranged from an antireflection film, a high-concentration carrier layer of an n-type (first conductive type), a light absorbing layer of the n-type, and a cap layer of the n-type that are laminated successively. The glass substrate is adhered via a silicon oxide film onto the antireflection film side of the structural body of layers. The glass substrate is optically transparent to incident light.Type: GrantFiled: November 30, 2004Date of Patent: November 16, 2010Assignee: Hamamatsu Photonics K.K.Inventor: Akimasa Tanaka
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Publication number: 20100271535Abstract: A solid-state imaging device includes: a semiconductor substrate; plural photoelectric conversion units formed side by side on the semiconductor substrate to form a light receiving unit; a peripheral circuit formed in a portion on an outside of the light receiving unit on the semiconductor substrate; a wiring section formed on the light receiving unit and formed for connecting the plural photoelectric conversion units and the peripheral circuit; and a dummy wiring section formed on an opposite side of the wiring section for at least one photoelectric conversion unit among the plural photoelectric conversion units on the light receiving unit and formed for functioning as a non-connected wiring section not connected to the photoelectric conversion units and the peripheral circuit, wherein the dummy wiring section has a predetermined potential.Type: ApplicationFiled: April 16, 2010Publication date: October 28, 2010Applicant: SONY CORPORATIONInventor: Kimihiko Sato
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Patent number: 7821094Abstract: A light emitting diode structure has a silicon substrate, a conductive layer, and a light emitting diode. The top surface of the silicon substrate has a cup-structure like paraboloid, and the bottom of the cup-structure has a plurality of through-holes penetrating the silicon substrate. The conductive layer fills up the through-holes and protrudes out from the through-holes. The light emitting diode is disposed on the top of the conductive layer protruding out from the through-holes and is located at the focus of the cup-structure.Type: GrantFiled: October 8, 2008Date of Patent: October 26, 2010Assignee: Touch Micro-System Technology Inc.Inventors: Hung-Yi Lin, Hong-Da Chang
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Patent number: 7821092Abstract: An open portion is provided to an interlayer insulation film so as to correspond to a photoreceptor part of an optical detection device. A partition wall for surrounding the open portion (120) is formed by a metal material inside a wiring structure layer (90) along the boundary between the photoreceptor part (4) and a circuit part (6). The partition wall is formed by a contact structure having a multi-level structure with respect to a separation region (74) disposed on the external periphery of the photoreceptor part (4). The partition wall prevents moisture absorption and light penetration from the wall surface of the open portion, and suppresses wiring degradation or fluctuation of the characteristics of the circuit elements on the periphery of the photoreceptor part.Type: GrantFiled: March 19, 2008Date of Patent: October 26, 2010Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventor: Akihiro Hasegawa
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Publication number: 20100264503Abstract: A solid-state imaging device includes an imaging element, an external terminal, an insulating film, a through-electrode and a first electrode. The imaging element is formed on a first major surface of a semiconductor substrate. The external terminal is formed on a second major surface opposing the first major surface of the semiconductor substrate. The insulating film is formed in a through-hole formed in the semiconductor substrate. The through-electrode is formed on the insulating film in the through-hole and electrically connected to the external terminal. The first electrode is formed on the through-electrode on the first major surface of the semiconductor substrate. When viewed from a direction perpendicular to the first major surface of the semiconductor substrate, an outer shape with which the insulating film and the semiconductor substrate are in contact is larger than an outer shape of the first electrode.Type: ApplicationFiled: March 19, 2010Publication date: October 21, 2010Inventors: Ikuko INOUE, Kenichiro HAGIWARA
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Patent number: 7816754Abstract: The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.Type: GrantFiled: June 13, 2007Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventor: Paul Marlan Harvey
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Publication number: 20100258896Abstract: In one example, an optoelectronic transducer includes a first contact, a second contact, a passivation layer, and a protection layer. The passivation layer is formed on top of the first contact and the second contact and is configured to substantially minimize dark current in the optoelectronic transducer. The protection layer is formed on top of the passivation layer and substantially covers the passivation layer. The protection layer is configured to protect the passivation layer from external factors and prevent degradation of the passivation layer.Type: ApplicationFiled: April 8, 2009Publication date: October 14, 2010Applicant: FINISAR CORPORATIONInventor: Roman Dimitrov
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Publication number: 20100252856Abstract: An opto-electronic element includes a header and an opto-electronic chip. The header have a metal stem and an insulating structure, and the opto-electronic chip located on the stem or insulating structure. The opto-electronic chip is grown with an epitaxy layer structure on a thicker and homogeneous electroconductive base, and the electrodes are located on the same side and have the same metal structure. Thus, the chip is located on the insulating structure and isolated from each electrode, and the chip and header are kept in an insulated state. Furthermore, an auxiliary pin for supporting the chip and for forming an open circuit or serving as an electrode of the chip is located in an axial direction of the insulating structure. The combination of the stem and insulating structure may be replaced with a non-metal stem with a corresponding shape, and a periphery of the non-metal stem may further have an extended wall portion combined with a cap to form the opto-electronic element.Type: ApplicationFiled: June 9, 2010Publication date: October 7, 2010Inventor: Rong-Heng Yuang
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Publication number: 20100252903Abstract: The surrounding length of a junction separation portion can be shortened to improve an insulating resistance in order to provide a solar cell with highly efficiency. In a photoelectric transducer of the type where a light-receiving surface electrode is wired to another electrode on a back surface via a through electrode passing through a semiconductor substrate of a first conductive type, the photoelectric transducer comprises: a junction separation portion made around the through electrode on a back surface of the semiconductor substrate; a dielectric layer formed for covering the junction separation portion, the through electrode penetrating the dielectric layer; and a back electrode provided on the dielectric layer and coupled to the through electrode which is connected to the light-receiving surface electrode.Type: ApplicationFiled: October 30, 2008Publication date: October 7, 2010Inventors: Tsutomu Yamazaki, Satoshi Okamoto, Jumpei Imoto
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Patent number: 7808110Abstract: A semiconductor package substrate proposed by the invention includes a base body and a plurality of finger pads disposed on surface of the base body, wherein the finger pads are arranged in such a way that an angle is formed between connecting line of centers of two adjacent finger pads and the direction in which the finger pads are arranged. The finger pads are waterdrop shaped finger pads with arc ends and angle ends alternately disposed on surface of the substrate, alternately disposed waterdrop shaped finger pads and arc shaped finger pads, or alternately disposed arc shaped finger pads at a predetermined spacing. According to the present invention, distance between adjacent finger pads is reduced and problem of short circuit as a result of erroneous contact between bonding wire and adjacent finger pad is prevented.Type: GrantFiled: January 30, 2008Date of Patent: October 5, 2010Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yu-Po Wang, Chien-Ping Huang, Wei-Chun Lin, Wen Cheng Lee
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Patent number: 7807559Abstract: A bonding pad includes multiple metal layers, insulation layers filled between the multiple metal layers, and a fixing pin coupled between the uppermost metal layer, where a bonding is performed, and the underlying metal layers. Peeling of the bonding pad can be prevented during the ball bonding by forming the fixing pin coupled to the edges of the bonding pad. The upper portion of the fixing pin is formed in a disk shape and a ball portion of the fixing pin is fixed by slits such that the peeling of the bonding pad can be further prevented.Type: GrantFiled: June 30, 2008Date of Patent: October 5, 2010Assignee: Hynix Semiconductor Inc.Inventor: Jeong-Soo Kim