Abstract: In a rear surface incidence type CMOS image sensor having a wiring layer 720 on a first surface (front surface) of an epitaxial substrate 710 in which a photodiode, a reading circuit (an n-type region 750 and an n+ type region 760) and the like are disposed, and a light receiving plane in a second surface (rear surface), the photodiode and a P-type well region 740 on the periphery of the photodiode are disposed in a layer structure that does not reach the rear surface (light receiving surface) of the substrate, and an electric field is formed within the substrate 710 to properly lead electrons entering from the rear surface (light receiving surface) of the substrate to the photodiode. The electric field is realized by providing a concentration gradient in a direction of depth of the epitaxial substrate 710. Alternatively, the electric field can be realized by providing a rear-surface electrode 810 or 840 for sending a current.

Abstract: A pixel with a photosensor and a transfer transistor having a split transfer gate. A first section of the transfer gate is connectable to a first voltage source while a second section of the transfer gate is connectable to a second voltage source. Thus, during a charge integration period of a photosensor, the two sections of the transfer gate may be oppositely biased to decrease dark current while controlling blooming of electrons within and out of the pixel cell. During charge transfer the two gate sections may be commonly connected to a positive voltage sufficient to transfer charge from the photosensor to a floating diffusion region.

Abstract: A solid state imaging apparatus includes a plurality of photoelectric conversion sections formed in an imaging area of a silicon substrate, and an embedded layer embedded in an isolation trench formed in at least one part of the silicon substrate located around the photoelectric conversion sections. The embedded layer is made of an isolation material having a thermal expansion coefficient larger than silicon oxide and equal to or smaller than silicon.

Abstract: A CMOS image sensor includes a photodiode, and a plurality of transistors for transferring charges accumulated at the photodiode to one column line, wherein at least one transistor among the plurality of transistors has a source region wider than a drain region, for increasing a driving current.

Abstract: An image sensor includes a semiconductor layer, and first and second photoelectric converting units including first and second impurity regions in the semiconductor layer that are spaced apart from each other and that are at about an equal depth in the semiconductor layer, each of the impurity regions including an upper region and a lower region. A width of the lower region of the first impurity region may be larger than a width of the lower region of the second impurity region, and widths of upper regions of the first and second impurity regions are equal.

Abstract: Disclosed herein is a solid-state imaging element which includes a plurality of drive signal inputs, a plurality of bus lines, and a plurality of vertical transfer register electrodes. In the solid-state imaging element, a charge accumulated in light-receiving elements in a pixel region is vertically transferred by the drive signals input to the electrodes. Each of the electrodes has a contact part connected to the second contact and having a width smaller than a width of the electrodes in the pixel region, and a blank region is formed between predetermined adjacent two of the contact parts so that a width of the blank region is larger than a distance between respective two of the contact parts other than the predetermined adjacent two of the contact parts. The first contact is disposed on the blank region.

Abstract: Provided is a CMOS image sensor and method of manufacturing same. The CMOS image sensor includes a photodiode, a transfer transistor, a reset transistor, a drive transistor, and a select transistor. A device isolation layer is formed on a first conductive type substrate. Gate electrodes of the transfer transistor, the reset transistor, the drive transistor, and the select transistor are formed on an active region of the substrate with gate insulating layers interposed therebetween. A first diffusion region is formed of a second conductive type in a first region of the active region, where the first region does not include a floating diffusion region between the transfer transistor and the reset transistor and the photodiode region. A second diffusion region is formed of the second conductive type in the floating diffusion region at a concentration lower than that of the second conductive type first diffusion region.

Abstract: Each of three light receiving sections has a P-type well having a P+-type layer and an N-type layer formed therein. The P+-type layer is diffused from substrate surface to depth d1. A PN junction forming portion of the N-type layer is diffused from depth d1 to depth d2 which is greater than depth d1 so as to form, with the P-type well, a PN junction of a photodiode at depth d2. Depths d1 as well as depths d2 of the three light receiving sections are different from each other. The N-type layer has a charge output portion which is diffused from the PN junction to the substrate surface, and which is coupled by circuit coupling to a MOS transistor for reading out charge. This allows each light receiving section to have spectral characteristics, thereby providing a solid state imaging element and a solid state imaging device without using color filters.

Abstract: In accordance with the invention, a photonic device comprises a semiconductor substrate including at least one circuit component comprising a metal silicide layer and an overlying layer including at least one photoresponsive component. The metal silicide layer is disposed between the circuit component and the photoresponsive component to prevent entry into the circuit component of light that penetrates the photoresponsive component. The silicide layer advantageously reflects the light back into the photoresponsive element. In addition, the overlying layer can include one or more reflective layers to reduce entry of oblique light into the photoresponsive component. In an advantageous embodiment, the substrate comprises single-crystal silicon including one or more insulated gate field effect transistors (IGFETs), and/or capacitors, and the photoresponsive element comprises germanium and/or germanium alloy epitaxially grown from seeds on the silicon.

Abstract: A photodiode in which a pn junction is formed between the doped region (DG) formed in the surface of a crystalline semiconductor substrate and a semiconductor layer (HS) deposited above said doped region. An additional doping (GD) is provided in the edge region of the doped zone, by means of which additional doping the pn junction is shifted deeper into the substrate (SU). With the greater distance of the pn junction from defects at phase boundaries that is achieved in this way, the dark current within the photodiode is reduced.

Abstract: A CMOS image sensor includes a photo-transistor capable of performing photo-sensing and active amplification. The photo-transistor is installed to improve low illustration characteristics while maintaining an existing pixel operation. The CMOS image sensor also includes a reset transistor connected to the photo-transistor and adapted to perform a reset function, a drive transistor for acting as a source follower buffer amplifier in response to an output signal from the photo-transistor, and a switching transistor connected to the drive transistor and adapted to perform an addressing function.

Abstract: A photodiode and a method of fabricating a photodiode for reducing modal dispersion and increasing travel distance. The central region of the photodiode is made less responsive to incident light than a peripheral region of the photodiode. The less responsive central region discriminates the lower order modes such that only the higher order modes are incident on the more responsive peripheral region. Because the lower order modes are subtracted, the range of propagation constants is reduced and modal dispersion is also reduced.

Abstract: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.

Abstract: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.

Abstract: A reset transistor includes a floating diffusion region for detecting a charge, a junction region for draining the charge, a gate for controlling a transfer of the charge from the floating diffusion region to the junction region upon receipt of a reset signal, and a potential well incorporated underneath the gate.

Abstract: A CMOS image sensor and a method for manufacturing the same. In one example embodiment, a CMOS image sensor includes a field region and an active region, a second conductive bottom region, a first conductive well region, a second conductive top region, and a first conductive high concentration region. The field region and the active region are formed in a first conductive semiconductor substrate. The second conductive bottom region has a first depth in part of the active region. The first conductive well region is formed in the active region. The second conductive top region has a depth that is less than the first depth. The first conductive high concentration region has a depth that is less than the depth of the second conductive top region.

Abstract: An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes depending on the level of accumulated charge in the accumulation region. During an integration period, incident light causes electrons to be accumulated inside the buried accumulation region. The resistance characteristic of the channel region changes in response to a field created by the charges accumulated in the accumulation region. Thus, when a voltage is applied to one side of the channel, the current read out from the other side is characteristic of the amount of stored charges.

Abstract: A pixel having a well-isolated charge storage region or floating diffusion region may be obtained by providing a separate P-well around the storage region or floating diffusion region. In one embodiment, a separate P-well entirely encases the storage region and is in contact with the storage region. This P-well provides an electrical barrier for preventing electrons that are generated elsewhere in the pixel from contaminating the storage region. In another embodiment, a first separate P-well encases and is in contact with the storage region and a second separate P-well encases and is in contact with the floating diffusion region.

Abstract: In a photoelectric conversion apparatus including a charge holding portion, a part of an element isolation region contacting with a semiconductor region constituting the charge holding portion extends from a reference surface including the light receiving surface of a photoelectric conversion element into a semiconductor substrate at a level equal to or deeper than the depth of the semiconductor region in comparison with the semiconductor region.

Abstract: A semiconductor image sensor includes: a semiconductor substrate having a number of pixels disposed in a matrix shape, the semiconductor substrate comprising a first region including a charge accumulation region of a photodiode and a floating diffusion and a second region including transistors, each having a gate electrode and source/drain regions; a first silicon oxide film formed above the semiconductor substrate, covering the surface of the charge accumulation region in the first region and formed as side wall spacers on side of the gate electrode walls of at lease some transistors in the second region; and a silicon nitride film formed above the first silicon oxide film, covering the source/drain regions in the second region and having an opening at least in an area above the charge accumulation region in the first region. The semiconductor image sensor is provided which has a high sensitivity and can supply an output with small noises.

Abstract: A method for fabricating a CMOS image sensor may include forming an isolation layer defining an active area on a semiconductor substrate, forming first and second gate electrodes in the transistor area of the semiconductor substrate, forming a photodiode area in the semiconductor substrate at a first side of the first gate electrode, forming an oxide layer over the photodiode area, the oxide layer having a thickness greater than that of the dielectric layer, forming a source/drain extension area in the semiconductor substrate at a second side of the second gate electrode and between the first and second gate electrodes, forming source/drain regions in the transistor area of the semiconductor substrate by ion implantation through the dielectric layer, and forming a complementary ion implantation region in the photodiode area through the oxide layer.

Abstract: A semiconductor device having a substrate that contains an insulating layer and a semiconductor layer provided on the insulating layer. The semiconductor also has an optical waveguide that is formed along a predetermined path. This optical waveguide is formed by making the semiconductor layer non-uniformed in thickness thereof. The semiconductor further has a photoreceptor having MISFET containing a floating channel body that is formed on a position of the semiconductor layer in which electric field of light guided inside the optical waveguide exists and a gate for forming channel formed on a front surface side of the channel body.

Abstract: The photodiode comprises an upper pn junction (D1) formed between an upper layer and an intermediate layer supported by one portion of a semiconductor substrate. A lower junction is formed between the intermediate layer and the substrate portion. The forward bias voltage of the upper junction (D1) is lower than the forward bias voltage of the lower junction (D2). The charges are permitted to be stored in the photodiode until the said upper junction is forward-biased so as to favor (A1) the recombination of the carriers coming from the intermediate layer with the carriers of the upper layer.

Abstract: A photo thin film transistor having a photoconductive layer including a chalcogenide element and a unit cell of an image sensor using the same are provided. The photo thin film transistor includes a glass substrate; a photoconductive layer that is formed of GST including a chalcogenide element, is disposed on the glass substrate, and absorbs light and generates an optical current; a source electrode and a drain electrode that are formed on respective sides of the photoconductive layer and form a path for the optical current generated by the photoconductive layer; a gate insulating layer formed on the photoconductive layer; and a gate electrode that is formed on the gate insulating layer and turns the optical current on or off. The photo thin film transistor includes amorphous GST including a chalcogenide element forming a photoconductive layer, thereby providing very high photoconductivity.

Abstract: Embodiments relate to an image sensor. According to embodiments, an image sensor may include a circuitry, a first substrate, a photodiode, a metal interconnection, and an electrical junction region. The circuitry and the metal interconnection may be formed on and/or over the first substrate. The photodiode may contact the metal interconnection and may be formed on and/or over the first substrate. The circuitry may include an electrical junction region on and/or over the first substrate and a first conduction type region on and/or over the electrical junction region and connected to the metal interconnection. According to embodiments, an image sensor and a manufacturing method thereof may provide a vertical integration of circuitry and a photodiode.

Abstract: Provided is an image sensor and a method for manufacturing the same. In the image sensor, a semiconductor substrate has a readout circuitry formed thereon. An interlayer insulating layer including a lower metal line is on the semiconductor substrate, the lower metal line being electrically connected with the readout circuitry. A buffer insulating layer is on the interlayer insulating layer. A lower electrode penetrates the buffer insulating layer to be connected with the lower metal line. A crystalline semiconductor layer is on the buffer insulating layer, the crystalline semiconductor layer being partially connected with the lower electrode. A photodiode is in the crystalline semiconductor layer.

Abstract: Embodiments relate to an image sensor. According to embodiments, an image sensor may include a metal interconnection, readout circuitry, a first substrate, an image sensing device, and a second conduction type interfacial layer. The metal interconnection and the readout circuitry may be formed on and/or over the first substrate. The image sensing device may include a first conduction type conduction layer and a second conduction type conduction layer and may be electrically connected to the metal interconnection. The second conduction type interfacial layer may be formed in a pixel interface of the image sensing device.

Abstract: Embodiments relate to an image sensor and a method of forming an image sensor. According to embodiments, an image sensor may include a first substrate and a photodiode. A circuitry including a metal interconnection may be formed on and/or over the first substrate. The photodiode may be formed over a first substrate, and may contact the metal interconnection. The circuitry of the first substrate may include a first transistor, a second transistor, an electrical junction region, and a first conduction type region. The first and second transistors may be formed over the first substrate. According to embodiments, an electrical junction region may be formed between the first transistor and the second transistor. The first conduction type region may be formed at one side of the second transistor, and may be connected to the metal interconnection.

Abstract: A photosensor includes a plurality of photosensitive regions including a first photosensitive region connected to a first voltage reference, and at least one additional photosensitive region. A signal collector is connected to the first photosensitive region. At least one switching device is for switching the at least one additional photosensitive region between the first voltage reference and a second voltage reference that is less than the first voltage reference, and for reversibly connecting the at least one additional photosensitive region to the signal collector so that the photosensor is variably responsive to different light levels.

Abstract: An optical semiconductor device is provided with a low concentration p-type silicon substrate (1); a low dopant concentration n-type epitaxial layer (second epitaxial layer) (26); a low dopant concentration p-type anode layer (27); a high concentration n-type cathode contact layer (9); a photodiode (2) made of the anode layer (27) and the cathode contact layer (9); and an NPN transistor (3) formed on the n-type epitaxial layer (26). The anode can be substantially completely depleted in the case where the anode layer (27) has its dopant concentration peak in the vicinity of the interface between the silicon substrate (1) and the n-type epitaxial layer (26). Therefore, high speed and high light receiving sensitivity characteristics can be obtained, and further, any influence of auto-doping from peripheral embedding layers can be controlled, so that a depletion layer can be stably formed in the anode.

Abstract: A method for fabricating a photo diode first involves providing a substrate. A doping area is then formed on the substrate. Afterwards, a dielectric layer, and a first poly-silicon layer are formed on the substrate. An opening is then formed to expose a surface of the doping area. A second poly-silicon layer is formed on the first poly-silicon layer and within the opening. The second poly-silicon layer is patterned to form a wire, while the first poly-silicon layer is patterned to form a gate. Finally, a source/drain is formed.

Abstract: An electrostatic discharge (ESD) protected semiconductor device. The semiconductor device is formed as a monolithic structure. The monolithic structure includes a vertical cavity surface emitting laser (VCSEL) and a protection diode. The protection diode cathode is electrically coupled to the VCSEL anode and the protection diode anode is electrically coupled to the VCSEL cathode so as to provide ESD protection to the VCSEL.

Abstract: A source region and drain region are formed in a surface region of a first semiconductor region. Moreover, a second semiconductor region connected to the drain region is formed in the surface region of the first semiconductor region. A third semiconductor region is formed in the first semiconductor region under the second semiconductor region, connected to the second semiconductor region, and accumulates signal charges in accordance with an incident light. A fourth semiconductor region is formed in the surface region of the first semiconductor region between the drain region and source region. Moreover, these source region, drain region, second semiconductor region, and third semiconductor region constitute a pixel, and different voltages are supplied to the drain region in an accumulation period of the signal charges in the pixel, signal readout period, and discharge period of the signal charges.

Abstract: An integrated circuit arrangement includes a pin photodiode and a highly doped connection region of a bipolar transistor. A production method produces an intermediate region of the pin diode with a large depth and without auto-doping in a central region.

Abstract: An optical semiconductor device includes a phototransistor for receiving incident light. The phototransistor includes a collector layer of a first conductivity type formed on a semiconductor substrate, a base layer of a second conductivity type formed on the collector layer, and an emitter layer of a first conductivity type formed on the base layer. A thickness of the emitter layer is equal to or less than an absorption length of the incident light in the semiconductor substrate.

Abstract: A solid state image pickup device that can properly widen a dynamic range is provided. Carriers that have overflowed from photodiodes (1003a to 1003c) to lateral overflow regions (1010a to 1010c) and carriers accumulated in the photodiodes (1003a and 1003b) are transferred to FD regions (1005a to 1005c). Signals based on those carriers are added and held in a signal level holding capacitor (Cs) and read out therefrom, thereby widening the dynamic range.

Abstract: A method and system for providing a bipolar transistor is described. The method and system include providing a compound base region, providing an emitter region coupled with the compound base region, and providing a collector region coupled with the compound base region. The bipolar transistor may also include at least one other predetermined portion. The method and system also include providing at least one predetermined amount of oxygen to at least one of the compound base region, the emitter region, the collector region, and the predetermined portion of the bipolar transistor.

Abstract: A MOS or CMOS sensor for high performance imaging in broad spectral ranges including portions of the infrared spectral band. These broad spectral ranges may also include portions or all of the visible spectrum, therefore the sensor has both daylight and night vision capabilities. The sensor includes a continuous multi-layer photodiode structure on a many pixel MOS or CMOS readout array where the photodiode structure is chosen to include responses in the near infrared spectral ranges. A preferred embodiment incorporates a microcrystalline copper indium diselenide/cadmium sulfide photodiode structure on a CMOS readout array. An alternate preferred embodiment incorporates a microcrystalline silicon germanium photodiode structure on a CMOS readout array. Each of these embodiments provides night vision with image performance that greatly surpasses the GEN III night vision technology in terms of enhanced sensitivity, pixel size and pixel count.

Abstract: A solid-state imaging device includes: a substrate; a photo-receiving portion formed in the substrate; a wiring layer formed on the substrate and having a trench being formed on a region directly above the photo-receiving portion; and a light guiding member provided in the trench and made of organic material. An empty space is formed between a side wall of the trench and a side surface of the light guiding member. The side surface of the light guiding member is curved so that a central part of the side surface along a vertical direction is closer to a center axis of the trench than both end parts of the side surface along the vertical direction.

Abstract: A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the capacitor to change the conversion gain of the floating diffusion region from a first conversion gain to a second conversion gain. In order to increase the efficient use of space, the dual conversion gain element gate also functions as the bottom plate of the capacitor. In one particular embodiment of the invention, a high dynamic range transistor is used in conjunction with a pixel cell having a capacitor-DCG gate combination; in another embodiment, adjacent pixels share pixel components, including the capacitor-DCG combination.

Abstract: A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor has a first-conductivity-type drain region formed in the second-conductivity-type semiconductor region to transfer signal charge to the drain region. The second transistor has a source region and a drain region which are formed in the second-conductivity-type semiconductor region and which have the first conductivity type. At least one second-conductivity-type potential barrier is provided under the drain region of the first transistor and the source region and/or the drain region of the second transistor.

Abstract: In the solid-state imaging device of the present invention having a photoelectric conversion section and a charge transfer section equipped with a charge transfer electrode for transferring an electric charge generated in the photoelectric conversion section, the charge transfer electrode has an alternate arrangement of a first layer electrode including a first layer electrically conducting film and a second layer electrode including a second layer electrically conducting film, which are formed on a gate oxide film including a laminate film consisting of a silicon oxide film and a metal oxide thin film, and the first layer electrode and the second layer electrode are separated by insulation with an interelectrode insulating film including a sidewall insulating film formed by a CVD process to cover the lateral wall of the first layer electrode.

Abstract: Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor structure comprises at least one semiconductor channel region, at least one gate for controlling the channel region, and first and second leads respectively coupled to a source region on one side of the at least one channel region and a drain region on an opposite side of the at least one channel region. The transistor structure has at least two threshold voltages associated with the at least one channel region, and an I-V characteristic of the transistor structure is determined at least in part by the threshold voltages.

Abstract: An object of the present invention is to simultaneously realize the enlargement of a dynamic range and the downsizing of a pixel. An additional capacitor CS is composed by using: a first capacitor formed of a first diffusion layer, a second diffusion layer and a P well by layering the P well, the first diffusion layer, a first dielectric film, a first polysilicon layer, a second dielectric film and a second polysilicon layer; a second capacitor formed of the second diffusion layer, the first polysilicon layer and the first dielectric film; and a third capacitor formed of the first polysilicon layers, a second polysilicon layer, and a second dielectric film. Thereby, the additional capacitor CS for accumulating carriers overflown from a photodiode PD can secure a required capacitance value while making its size as small as possible.

Abstract: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 ?m into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.

Abstract: A solid-state imaging device achieving a global shutter of images and its manufacturing method are disclosed. According to one aspect of the present invention, it is provided a solid-state imaging device comprising an optical signal storage region provided in a semiconductor substrate, a signal detecting region provided in the semiconductor substrate apart from the optical signal storage region, a transistor electrically connecting the optical signal storage region with the signal detecting region, a wiring connected with the signal detecting region, and a light shielding film provided in close proximity to the signal detecting region and over the signal detecting region.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or carbonated silicon is provided over the substrate of the pixel cell to reduce the dark current leakage.

Abstract: A solid-state image pickup device includes, in a substrate, a plurality of photoelectric conversion regions for subjecting incoming light to photoelectric conversion, a reading gate for reading a signal charge from the photoelectric conversion regions, and a transfer register (vertical register) for transferring the signal charge read by the reading gate. Therein, a groove is formed on the surface side of the substrate, and the transfer register and the reading gate are formed at the bottom part of the groove. With such a structure, in the solid-state image pickup device, reduction can be achieved for the smear characteristics, a reading voltage, noise, and others.

Abstract: A solid-state image sensing device having an effective pixel area and an optical black area disposed on one principal surface of a substrate, includes photoelectric converter elements, a wiring part containing a plurality of wiring layers disposed on the one principal surface of the substrate, in which in the optical black area more wiring layers are disposed than in the effective pixel area, an interlayer dielectric disposed between, among the plurality of wiring layers, a topmost first wiring layer and a second wiring layer disposed beneath the first wiring layer, a passivation film disposed on the interlayer dielectric in the effective pixel area and disposed on the first wiring layer in the optical black area, and inner lenses disposed at least at positions on the passivation film that corresponds to the effective pixel area, a thickness of the passivation film being equal to or less than a thickness of the first wiring layer.