With Particular Doping Concentration Patents (Class 257/463)
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Patent number: 5982012Abstract: The present invention relates to a pixel cell and pixel cell array modified to improve performance. One improvement taught by the present invention is implantation of dopant into the silicon to form the base region after formation of polysilicon, resulting in highest base dopant concentrations lying at the thin oxide and emitter interfaces. A second improvement taught by the present invention is a reduction in the size of the heavily doped portion of the emitter to extend no further than the footprint of the emitter contact, thereby inhibiting leakage between the emitter and adjacent polysilicon. A third improvement taught by the present invention is electronic isolation of pixel cells by inter-pixel regions doped with conductivity-altering impurity of a type opposite that of the base rather than by field oxides, thereby eliminating leakage at the field oxide edge.Type: GrantFiled: January 14, 1998Date of Patent: November 9, 1999Assignee: Foveon, Inc.Inventor: Richard B. Merrill
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Patent number: 5977576Abstract: In an image sensor 1 wherein an N.sup.+ -type impurity layer 13 to become a light-receiving part of a first conductive type is formed in a well layer 12 of a second conductive type (P-type) provided in a semiconductor substrate 11 of the first conductive type (N-type), an N.sup.- -type impurity layer 14 whose impurity concentration is lower than that of the N.sup.+ -type impurity layer 13 and connected to the lower side of the N.sup.+ -type impurity layer 13 is provided between the N.sup.+ -type impurity layer 13 and the P-type well layer 12. Alternatively, a P-type impurity layer (not shown) whose impurity concentration is lower than that of the P-type well layer 12 and joining with the lower side of the N.sup.+ -type impurity layer 13 may be provided.Type: GrantFiled: February 20, 1997Date of Patent: November 2, 1999Assignee: Sony CorporationInventor: Masaharu Hamasaki
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Patent number: 5973260Abstract: The present invention discloses a converging type solar cell element able to restrain recombination of carriers and inflow of carriers into an embankment section and improve photoelectric conversion efficiency. A p.sup.+ diffusion layer 16 is formed on the surface of a sunlight receiving section 10 which is formed on a silicon substrate 12 comprising a p-type silicon. An energy gradient arises between the p.sup.+ diffusion layer 16 and the silicon substrate 12. Therefore, free electrons, which are minority carriers among the carriers generated in the silicon substrate 12 resulting from irradiation of sunlight to the sunlight receiving section 10, can be prevented from migrating to the surface side of the silicon substrate 12. Further, recombination of free electrons which may arise due to lattice defects of the surface can also be prevented. Still further, the p.sup.+ diffusion layer 16 may also be formed on a back surface side of the embankment section 14 which surrounds the sunlight receiving section 10.Type: GrantFiled: October 8, 1997Date of Patent: October 26, 1999Assignee: Toyota Jidosha Kabushiki KaishaInventors: Kyoichi Tange, Tomonori Nagashima
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Patent number: 5942788Abstract: A solid state image sensing device having a semiconductor substrate, a first diffusion region of a positive or negative conductive type provided on the semiconductor substrate, a plurality of second diffusion regions each of which is an opposite conductive type relative to the first diffusion region and is provided in the first diffusion region, and a semiconductor thin layer provided on at least the second diffusion regions.Type: GrantFiled: April 30, 1996Date of Patent: August 24, 1999Assignee: Minolta Co., Ltd.Inventors: Kenji Takada, Kouichi Ishida, Keiichi Nomura, Yoshihiro Hamakawa, Hiroaki Okamoto
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Patent number: 5942789Abstract: A photodetector provides high photo-sensitivity, a low resistance of a cathode circuit and quick photoresponse, and includes a light absorption layer in a cavity, which is formed in a N-Si epitaxial layer and surrounded by a side wall oxide layer. A N-Si diffusion layer is formed on the bottom and the side wall around the cavity and has a lower resistance than the epitaxial layer. The diffusion layer contacts a cathode take-out region so that the resistance of the cathode circuit is decreased.Type: GrantFiled: July 29, 1997Date of Patent: August 24, 1999Assignee: NEC CorporationInventor: Takenori Morikawa
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Patent number: 5923071Abstract: A semiconductor substrate having a silicon-on-insulator structure may achieve superior performance by utilizing a low oxygen content monocrystalline silicon thin film layer for device formation. A supporting substrate, which may comprise a transparent material, such as quartz, or which may be silicon, has an insulating film disposed thereover. The insulating film preferably has a lower diffusion coefficient with respect to impurities than the monocrystalline silicon thin film, which is provided thereover. In accordance with this structure, oxygen particles are not introduced into the monocrystalline thin film and the thin film has a low oxygen concentration to maximize the minority carrier lifetime, enhance device performance characteristics, and prevent the occurrence of latch up.Type: GrantFiled: September 27, 1993Date of Patent: July 13, 1999Assignee: Seiko Instruments Inc.Inventor: Yutaka Saito
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Patent number: 5898209Abstract: A semiconductor photosensitive element comprises first and second photosensitive regions. The first photosensitive region is different from the second photosensitive region in its structure and thereby the first photosensitive region has photoelectric conversion characteristic and frequency characteristic which are different from those of the second photosensitive region.Type: GrantFiled: June 13, 1995Date of Patent: April 27, 1999Assignee: Sony CorporationInventor: Shinji Takakura
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Patent number: 5825071Abstract: A semiconductor photosensitive element comprises first and second photosensitive regions. The first photosensitive region is different from the second photosensitive region in its structure and thereby the first photosensitive region has photoelectric conversion characteristic and frequency characteristic which are different from those of the second photosensitive region.Type: GrantFiled: May 27, 1997Date of Patent: October 20, 1998Assignee: Sony CorporationInventor: Shinji Takakura
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Patent number: 5821567Abstract: A light-sensing/emitting diode array chip has impurity diffusion regions with a depth of at least 0.5 .mu.m but not more than 2 .mu.m in a semiconductor substrate. Each impurity diffusion region is preferably divided into a first region, used for emitting or sensing light, and a wider second region, used for electrode contact. The second regions are located on alternate sides of the array line, permitting a small array pitch to be combined with a large contact area. In a wafer process for fabrication of the chips, a diffusion mask has both windows defining the impurity diffusion regions, and dicing line marks. The dicing line marks are narrowed where they pass adjacent to the windows at the ends of the chip. In the electrode fabrication step, a photomask with an enlarged pattern is used, to allow for misalignment with the diffusion mask.Type: GrantFiled: December 11, 1996Date of Patent: October 13, 1998Assignee: Oki Electric Industry Co., Ltd.Inventors: Mitsuhiko Ogihara, Yukio Nakamura, Takatoku Shimizu, Masumi Taninaka
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Patent number: 5811867Abstract: A photo detective unit includes a photo detective semiconductor chip including a photo detective element formed under a first manufacturing condition and a buffer circuit for shaping output waveform of the photo detective element, and a signal processing semiconductor chip formed under a second manufacturing condition and responsive to voltage from the photo detective semiconductor chip for generating digital data, and the photo detective semiconductor chip and the signal processing semiconductor chip are together accommodated in a single package.Type: GrantFiled: September 9, 1996Date of Patent: September 22, 1998Assignee: Rohm Co., Ltd.Inventors: Yosuke Yamamoto, Tadayoshi Ogawa, Shinji Yano
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Patent number: 5770872Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N.sup.+ type diffusion layer, N.sup.- type epitaxial layer, P.sup.- type epitaxial layer, P.sup.+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P.sup.- epitaxial layer, the efficiency in density control at the time of P.sup.- type epitaxial growth can be improved.Type: GrantFiled: December 5, 1996Date of Patent: June 23, 1998Inventor: Chihiro Arai
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Patent number: 5747840Abstract: The quantum efficiency of a photodiode is substantially increased by forming the photodiode on a heavily-doped layer of semiconductor material which, in turn, is formed on a semiconductor substrate. The heavily-doped layer of semiconductor material tends to repel information carriers in the photodiode from being lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photodiode. In addition, the red and blue photoresponses are balanced by adjusting the depth of the photodiode.Type: GrantFiled: October 21, 1996Date of Patent: May 5, 1998Assignee: Foveonics, Inc.Inventor: Richard Billings Merrill
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Patent number: 5731622Abstract: It is the object of the invention to suppress the leakage current of a semiconductor photodiode. A trench, a side wall of which is covered with and insulating layer, is formed on the surface of a semiconductor substrate of the first conductivity type. Then, an epitaxial layer of the second conductivity type is grown in the trench, where a PN-junction is constructed between the bottom surface of the epitaxial layer and the semiconductor substrate. An impurity diffusion layer of the second conductivity type with higher impurity concentration than that of an internal portion of the epitaxial semiconductor layer is formed over the side surface of the epitaxial layer of the second conductivity type. In the aforementioned structure, when a reverse bias voltage is applied to the PN-junction, a depletion layer does not extend to a neighborhood of the insulating layer, and a leakage current, which flows via surface states near the insulating layer.Type: GrantFiled: February 24, 1997Date of Patent: March 24, 1998Assignee: NEC CorporationInventors: Mitsuhiro Sugiyama, Tsutomu Tashiro
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Patent number: 5719414Abstract: A photoelectric conversion semiconductor device is characterized in that a second conductivity type impurity region is formed in a first conductivity type semiconductor substrate, the second conductivity type impurity region having a depth of 0.1 .mu.m or less and a peak density of 1.times.10.sup.19 atoms/cm.sup.3 or more. A method of manufacturing a photoelectric conversion semiconductor device is characterized by a step of ion-injecting boron or boron fluoride with a dose amount of 1.times.10.sup.16 to 5.times.10.sup.16 atoms/cm.sup.2 into a semiconductor substrate as an impurity.Type: GrantFiled: March 16, 1994Date of Patent: February 17, 1998Inventors: Keiji Sato, Yutaka Saito, Tadao Akamine, Junko Yamanaka
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Patent number: 5652439Abstract: The invention relates generally to optoelectronic pnpn devices and more particularly to a layer structure suitable for fast electrical complete turn-off of such devices and to a method for efficient and fast operation of such devices and differential pairs of such devices. The devices have four layers and three junctions, and the invention provides for complete depletion of both center layers. The differential pair of pnpn devices also provides a very sensitive optical receiver which combines a very high cycle frequency with a very high optical sensitivity.Type: GrantFiled: September 8, 1995Date of Patent: July 29, 1997Assignee: IMECInventors: Maarten Kuijk, Paul Heremans, Roger Vounckx, Gustaaf Borghs
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Patent number: 5609694Abstract: A solar cell includes a first n.sup.+ type layer formed on the upper surface of a p type silicon substrate, a p type layer formed on the back surface of the substrate and having a dopant impurity concentration higher than that of the substrate, and a second n type layer formed at least on the edge face of the substrate so as to connect the first n type layer and the p type layer. The second n type layer has an impurity concentration lower than that of the first n.sup.+ layer proximate the region in contact with the p type layer.Type: GrantFiled: April 25, 1995Date of Patent: March 11, 1997Assignee: Sharp Kabushiki KaishaInventor: Masahito Asai
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Patent number: 5600157Abstract: According to a first aspect of the invention, a light-emitting and light-sensing diode has a doped region with a depth not exceeding 2 .mu.m, for adequate sensitivity, and an impurity concentration of at least 5.times.10.sup.20 atoms/cm.sup.-3, for adequate emission. According to a second aspect of the invention, a light-emitting and light-sensing diode has a doped region with a deep part and a shallow part, and the area of the shallow part is increased to enhance the sensitivity of the diode. This may be done by providing the doped region with a meandering edge, or with one or more interior islands, or by forming the deep and shallow parts separately.Type: GrantFiled: May 29, 1996Date of Patent: February 4, 1997Assignee: Oki Electric Industry Co., Ltd.Inventors: Ichimatsu Abiko, Yukio Nakamura, Katsuzo Kaminishi, Takatoku Shimizu, Kazuo Tokura, Yasuo Iguti, Hiroshi Furuya, Mituhiko Ogihara, Masumi Taninaka, Mio Chiba
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Patent number: 5600173Abstract: A semiconductor position sensitive detector has an epitaxial layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type. A first diffusion layer of the first conductivity type is formed in said epitaxial layer so as to isolate a rectangular portion of this epitaxial layer from the rest. A second diffusion layer of the first conductivity type is further formed in said rectangular portion of the epitaxial layer, in order to increase the resistance value of the epitaxial layer. In addition, due to the formation of the second diffusion layer, two p-n junctions having photoelectric transfer ability are formed in this device. So, a semiconductor position sensitive detector having excellent photoelectric characteristics can be obtained.Type: GrantFiled: February 8, 1995Date of Patent: February 4, 1997Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Suzunaga
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Patent number: 5598014Abstract: A photoconductor has an active layer of gallium nitride having approximately 10.sup.15 to 5.times.10.sup.15 net donor sites per cubic centimeter and is sensitive to UV radiation. This photoconductor has at least one of a sheet resistance in the approximate range of 10.sup.4 to 5.times.10.sup.6 ohms/unit area and a relatively low level of photoluminescence in the range from about 430-450 nm when excited with light of energy higher than the bandgap energy of 3.4 eV. These criteria tend to define similar semiconductor materials which can form the active layer of an ultraviolet (UV) photodetector having the improved characteristics of a relatively low dark resistance, high sensitivity over at least a range of UV radiation intensity, and decreasing gain with increasing UV radiation.Type: GrantFiled: February 28, 1995Date of Patent: January 28, 1997Assignee: Honeywell Inc.Inventors: Barbara G. Barany, Scott T. Reimer, Robert P. Ulmer, J. David Zook
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Patent number: 5519247Abstract: A detector circuit, for example for optical radiation, has a detector diode (20) and an amplifier circuit (30) integrated with the diode in the same silicon wafer for amplification of the diode signal. The diode is designed as a lateral diode. The diode and the amplifier circuit are both produced in a homogeneously weakly doped silicon wafer (1).Type: GrantFiled: October 25, 1994Date of Patent: May 21, 1996Assignee: Asea Brown Boveri ABInventors: Richard Arbus, Kjell Bohlin, Paul Stephanson, Jonas Tiren
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Patent number: 5510631Abstract: A non-monocrystalline silicon carbide semiconductor comprises carbon atoms, silicon atoms, and at least one of hydrogen atoms and halogen atoms, the non-monocrystalline silicon carbide semiconductor having therein microvoids with an average radius of not more than 3.5 .ANG. at a microvoid density of not more than 1.times.10.sup.19 cm.sup.-3.Type: GrantFiled: August 11, 1994Date of Patent: April 23, 1996Assignee: Canon Kabushiki KaishaInventors: Keishi Saito, Tatsuyuki Aoike, Toshimitsu Kariya, Yuzo Koda
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Patent number: 5500550Abstract: A photoelectric converting device comprises a first semiconductor area of a first conductivity type, a second semiconductor area of a second conductivity type, and a third semiconductor area of the first conductivity type. A charge is photoelectrically excited by light incident on the second semiconductor area, and is derived from the first semiconductor area after amplification.A fourth semiconductor area of the first conductivity type is formed in contact with the second semiconductor area and so positioned corresponding to the third semiconductor area. During operation of the device, a depletion layer extending from the interface between the third and fourth semiconductor areas reaches a depletion layer extending from the interface of the third and second semiconductor areas.Type: GrantFiled: November 10, 1994Date of Patent: March 19, 1996Assignee: Canon Kabushiki KaishaInventor: Masakazu Morishita
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Patent number: 5489794Abstract: The semiconductor device contains a CMOS transistor pair comprised of a P channel MOS transistor having a polysilicon gate 4 and an N channel MOS transistor having a polysilicon gate. The MOS transistor has a channel dope layer 5 localized in a vicinity of a surface of a channel region just below a gate electrode. This channel dope layer 5 has a quite shallow p-n junction depth xj effective to suppress a leak current. Thereby, an amount of impurity concentration in the surface of the channel region can be reduced to improve a subthreshold characteristics of the MOS transistor and to enable a low voltage and high speed operation under suppressing a leakage current.Type: GrantFiled: May 20, 1993Date of Patent: February 6, 1996Assignee: Seiko Instruments Inc.Inventors: Koju Nonaka, Shigeyuki Tsunoda, Kenji Kitamura
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Patent number: 5481123Abstract: A group III-V substrate is doped with tellurium or another group VI element, instead of silicon, in order to avoid the conductivity type conversion that could otherwise occur if the group V element is boiled off during high temperature processing. For example, a gallium arsenide substrate can be doped with tellurium and then a gallium arsenide epitaxial layer can be deposited on a surface. If the substrate is heated beyond a predetermined temperature during the processing of the device, the arsenic can boil away from the substrate and leave arsenic vacancies. If the silicon is used as the substrate dopant, the silicon can migrate to the arsenic vacancies and replace arsenic, particularly proximate the substrate surface. If, on the other hand, tellurium or another group VI element is used as the substrate dopant, this change in conductivity type can not occur. Therefore, the conductivity conversion proximate the substrate surface will not create a thyristor-like behavior that is significantly disadvantageous.Type: GrantFiled: December 20, 1994Date of Patent: January 2, 1996Assignee: Honeywell Inc.Inventors: Ralph H. Johnson, Edward W. Mehal
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Patent number: 5446308Abstract: A method of forming a planar semiconductor device, such as an array of APDs, includes the steps of doping a substantially planar block of n type semiconductor material with a p type dopant in accordance with a selected pattern to form a plurality of n type wells in the block surrounded by a foundation of p type semiconductor material. Each n type well is disposed so as to respectively adjoin a first surface of the block and such that a respective p-n junction is formed between the n type material in the well and the p type material foundation. The n type semiconductor material in each well has a substantially constant concentration of n type dopant throughout the n type material; the concentration of p type dopant in the foundation has a positive gradient extending from the p-n junction towards the second surface such that the peak surface electric field of the p-n junction in each well is less than the bulk electric field of the same p-n junction.Type: GrantFiled: April 4, 1994Date of Patent: August 29, 1995Assignee: General Electric CompanyInventors: Dante E. Piccone, Ahmad N. Ishaque, Donald E. Castleberry, Henri M. Rougeot, Peter Menditto
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Patent number: 5430321Abstract: A photodiode structure for the detection of radiation comprises a semiconductor base layer of p-type conductivity with a high doping density, an epitaxial layer of p-type conductivity with a relatively low doping density, areas of n-type conductivity and oxide layers covering the areas of n-type conductivity. The oxide layers comprise doping impurities of the same conductivity type as the areas below them. The doping density in the areas of n-type conductivity decrease towards the junction with the epitaxial layer. Due to this decrease in doping density, an electric field gradient is produced which guides the charge carriers to the junction. The generation of a field gradient and the creation of a surface charge result in an improved quantum efficiency. The invention is preferably used in photodiode arrays.Type: GrantFiled: May 5, 1994Date of Patent: July 4, 1995Assignee: Hewlett-Packard CompanyInventor: Uwe Effelsberg
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Patent number: 5424565Abstract: A position-sensitive semiconductor detector is provided having a completely depleted primary area of a first conductivity and insulation layers on the two main surfaces as well as conductive electrodes on the insulation layers (MIS structure).Type: GrantFiled: November 4, 1993Date of Patent: June 13, 1995Assignee: Josef KemmerInventor: Josef Kemmer
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Patent number: 5382824Abstract: An integrated circuit includes a photo diode having a first electrically isolated portion of an epitaxial layer of a first conductivity type, a first semiconductor layer of a second conductivity type disposed therein, a second semiconductor layer of the first conductivity type disposed in the first semiconductor layer, and a third semiconductor layer of the second conductivity type disposed in the second semiconductor layer.Type: GrantFiled: July 13, 1993Date of Patent: January 17, 1995Assignee: Landis & Gyr Business Support AGInventor: Radivoje Popovic
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Patent number: 5340408Abstract: A solar cell or photo diode has an n-type semiconductor layer and a p-type semiconductor layer which form a pn-junction at the metallurgical interface of the layers. A thin sheet of undoped semiconductor is located at the interface or the lower doped layer. The sheet has less recombination centers than its adjacent regions and prevents cross-doping of donors and acceptors from the n- and p-side by cross-diffusion to increase the open circuit voltage and fill-factor of the solar cells or photo diode.Type: GrantFiled: April 19, 1993Date of Patent: August 23, 1994Assignee: The University of DelawareInventor: Karl W. Boer
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Patent number: 5308996Abstract: A TFT device has an insulation substrate, a semiconductor layer formed on the insulation substrate, a pair of opposed electrodes formed on the semiconductor layer, and a gate electrode formed on the semiconductor layer with an insulation film interposed therebetween, wherein a region doped with at least one type of impurity selected from atoms belonging to the V group of the periodic table is formed in the semiconductor layer at the vicinity of the interface between the semiconductor layer and the insulation layer.Type: GrantFiled: June 29, 1993Date of Patent: May 3, 1994Assignee: Canon Kabushiki KaishaInventors: Satoshi Itabashi, Masaki Fukaya, Toshiyuki Komatsu, Yoshiyuki Osada, Ihachiro Gofuku
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Patent number: 5225706Abstract: In a matrix array of photosensitive elements, each photosensitive point is provided with a photosensitive element (pin photodiode) in series with a capacitor between a row lead and a column lead. It is proposed to make use of a simplified photosensitive element in which an end semiconductor layer is suppressed such as, for example, the n-layer of a pin photodiode or the n-layer of a five-layer phototransistor of the nipin type. The dielectric of the capacitor then comes directly into contact with an intrinsic semiconductor layer in which electrons accumulate. These electrons reconstitute the equivalent of an n-type doped layer.Type: GrantFiled: February 25, 1991Date of Patent: July 6, 1993Assignee: Thomson-CSFInventors: Jean L. Berger, Marc Arques
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Patent number: 5198881Abstract: A surface electron barrier region is formed on a semiconductor membrane device by a single step laser process which produces a sharp doping profile in a surface region above the light penetration depth. Enhanced quantum efficiency is observed, and by selectively forming barrier layers of differing depth, a CCD device architecture for two-color sensitivity is achieved. The barrier layer results in enhanced membrane-type and radiation hardened bipolar and CMOS devices.Type: GrantFiled: August 7, 1991Date of Patent: March 30, 1993Assignee: Massachusetts Institute of TechnologyInventors: Jammy C. Huang, Mordechai Rothschild, Barry E. Burke, Daniel J. Ehrlich, Bernard B. Kosicki
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Patent number: 5162887Abstract: A buried P-N junction photodiode is obtained in LinBiCMOS process with junctions formed between N+DUF diffused region and both first P-EPI layer and second P-EPI layer. Contact to N+DUF diffused region is made by a small area deep N+collector diffusion or N well diffusion. This novel buried-junction photodiode can be used for several types of unique photodetector structures including: single photodiode with low surface leakage current, multi-junction photodiodes for incident light spectral distribution information and higher efficiency visible response photodetectors. The disclosed structures are compatible with bipolar and CMOS processes for providing on-chip integration of optical photodetectors with Linear ASIC standard cells and other circuit functions.Type: GrantFiled: May 7, 1991Date of Patent: November 10, 1992Assignee: Texas Instruments IncorporatedInventor: Eugene G. Dierschke
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Patent number: 4616873Abstract: A safety boot for freely enclosing each rocker of a rocking chair, the inventive rocker safety boot comprises an elongated bottom wall of greater width and length than each rocker and adapted to support each rocker; elongated front and rear walls extending upwardly from the front and rear ends respectively for the bottom wall, and adapted to extend sufficiently above the highest rise of the front and rear ends respectively of the bottom wall, and adapted to extend sufficiently above the highest rise of the front and rear ends respectively of each rocker, in order to enclose the same when so elevated; elongated outer and inner side walls of greater height and length than each rocker connecting the walls, extending upwardly from bottom wall, and adapted to enclose each rocker and its connecting legs during rocking; and an elongated flexible cover connecting the end walls and side walls and adapted to enclose each rocker and its connecting legs.Type: GrantFiled: September 25, 1985Date of Patent: October 14, 1986Inventor: Joseph G. Debo