External Physical Configuration Of Semiconductor (e.g., Mesas, Grooves) Patents (Class 257/466)
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Patent number: 5773874Abstract: A semiconductor device comprises a monocrystalline silicon wafer having a major surface lying in the <100> crystal plane. Disposed on the surface is a mesa having a generally square cross-section with generally rounded corners. The mesa has four main side walls each having a slope of around 45 degrees with respect to the base plane of the mesa, and the horizontal edges of the main side walls are disposed at an angle of at least around 12 degrees to the <110> directions on the wafer surface. The corners of the mesa each comprises a number of surfaces also having slopes of around 45 degrees and one surface having a slope of around 54 degrees. A high-low (N.sup.+ N.sup.- or P.sup.+ P.sup.-) junction is disposed within the mesa and makes a continuous line intercept with the mesa side walls around the entire periphery of the mesa. Except for exceptionally small deviations of no great significance, the high low junction intercept is at a constant height location entirely around the mesa periphery.Type: GrantFiled: May 12, 1997Date of Patent: June 30, 1998Assignee: General Instrument CorporationInventor: Willem Gerard Einthoven
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Patent number: 5747860Abstract: On a surface of a silicon substrate, N.sup.+ type buried layer and N-type epitaxial layer are formed in order, and an isolation layer reaching the silicon substrate from the surface of the N-type epitaxial layer is formed to define a photodiode. In the surface of the photodiode, a rectangular recess is selectively formed toward inside of the N-type epitaxial layer. On the side face of the recess, a silicon oxide layer is formed. In the region surrounded by the silicon oxide layer, a photo absorbing layer and so forth is formed. On the other hand, in an optical waveguide, a LOCOS oxide layer is formed toward inside from the surface of the N-type epitaxial layer. The N-type epitaxial layer is sandwiched between the LOCOS oxide layer and the N.sup.+ type buried layer. The refraction indexes of the LOCOS oxide layer and the N.sup.+ type buried layer are smaller than that of the N-type epitaxial layer.Type: GrantFiled: March 8, 1996Date of Patent: May 5, 1998Assignee: Nec CorporationInventors: Mitsuhiro Sugiyama, Tsutomu Tashiro
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Patent number: 5747835Abstract: A serial arrangement of photosensitive components of the planar-type has a first main surface on which a first photosensitive junction appears at the surface and a second main surface. The components are piled so that the second main surface of a component contacts the first main surface of the adjacent component. The second main surface of each component has a notch at its periphery along a lateral length corresponding at least to the distance between the photosensistive junction and the periphery.Type: GrantFiled: September 11, 1995Date of Patent: May 5, 1998Assignee: SGS-Thomson Microelectronics S.A.Inventor: Robert Pezzani
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Patent number: 5731622Abstract: It is the object of the invention to suppress the leakage current of a semiconductor photodiode. A trench, a side wall of which is covered with and insulating layer, is formed on the surface of a semiconductor substrate of the first conductivity type. Then, an epitaxial layer of the second conductivity type is grown in the trench, where a PN-junction is constructed between the bottom surface of the epitaxial layer and the semiconductor substrate. An impurity diffusion layer of the second conductivity type with higher impurity concentration than that of an internal portion of the epitaxial semiconductor layer is formed over the side surface of the epitaxial layer of the second conductivity type. In the aforementioned structure, when a reverse bias voltage is applied to the PN-junction, a depletion layer does not extend to a neighborhood of the insulating layer, and a leakage current, which flows via surface states near the insulating layer.Type: GrantFiled: February 24, 1997Date of Patent: March 24, 1998Assignee: NEC CorporationInventors: Mitsuhiro Sugiyama, Tsutomu Tashiro
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Patent number: 5725006Abstract: A solar battery cell, solar battery module, and solar battery module group achieving high product value by enabling the display of surface patterns without reducing the power generating efficiency of the solar battery cells are provided. The direction and/or reflectance of reflected light incident to the surface of the solar battery cell are varied by controlling the distribution of the rough surface structure imparted to the solar battery cell surface. The direction or reflectance of reflected light incident to the surface of the solar battery cell is changed in part depending upon the part of the semiconductor solar battery cell surface to which the light is incident. Semiconductor solar battery cells with high product value can therefore be achieved because patterns with strong visual impact can be displayed and easily recognized without reducing the power generation efficiency of the solar battery cell.Type: GrantFiled: November 28, 1995Date of Patent: March 10, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshitatsu Kawama, Takashi Ishihara, Satoshi Arimoto, Hiroaki Morikawa, Akihiro Takami, Yoshinori Matsuno, Hideo Naomoto, Yoichiro Nishimoto
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Patent number: 5712504Abstract: A pin type light-receiving device according to the present invention comprises (a) a semiconductor substrate, (b) a first semiconductor layer formed on a semiconductor substrate and doped with an impurity of a first conduction type, (c) a second semiconductor layer formed in a mesa shape on the first semiconductor layer and made of a first semiconductor material without intentionally doping the first semiconductor material with an impurity, (d) a third semiconductor layer formed in a mesa shape on the second semiconductor layer and made of the first semiconductor material doped with an impurity of a second conduction type different from the first conduction type, (e) a first electrode layer formed in ohmic contact on the first semiconductor layer, (f) a second electrode layer formed in ohmic contact on the third semiconductor layer, and (g) a fourth semiconductor layer formed around the first to the third semiconductor layers and made of a second semiconductor material having a band gap energy greater than thType: GrantFiled: February 2, 1996Date of Patent: January 27, 1998Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiroshi Yano, Kentaro Doguchi, Sosaku Sawada, Takeshi Sekiguchi
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Patent number: 5710439Abstract: In an optoelectronic integrated device having an optical element section in the wavelength region of 1.33 to 1.55 .mu.m and an electronic element section such as an HEMT integrated in a monolithic form on a GaAs substrate, the optical element section includes light receiving elements or light emitting elements, and an optical absorption layer of the light receiving element or a semiconductor layer forming an active layer of the light emitting element is formed of GaAsN-series compound semiconductor which is lattice-matching with the GaAs substrate, particularly, one of GaAsN, InGaAsN, InGaAsPN, GaAlAsN, InGalAsN, AlGaAsPN and InGaAlAsPN.Type: GrantFiled: December 23, 1996Date of Patent: January 20, 1998Assignee: The Furukawa Electric Co., Ltd.Inventor: Michio Ohkubo
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Patent number: 5693967Abstract: A CCD and manufacturing method thereof is disclosed including: a first conductivity-type substrate having a convex portion; a first conductivity-type charge transmission domain formed on the substrate excluding the convex portion; a light detecting domain formed on the convex portion of the substrate and having a convex top surface; a second conductivity-type high-concentration impurity area formed on the top surface of the light detecting domain; a gate insulating layer formed on the substrate excluding the light detecting domain; a transmission gate formed on the gate insulating layer; a planarization layer formed on the substrate including the transmission gate; and a microlens formed on the planarization layer above a photodiode.Type: GrantFiled: August 10, 1995Date of Patent: December 2, 1997Assignee: LG Semicon Co., Ltd.Inventors: Chul Ho Park, Kwang Bok Song
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Patent number: 5677551Abstract: A photodetection device includes a collector layer, a collector electrode connected electrically to the collector layer, a base layer free from a junction region for contacting with an electrode, an emitter layer including at least two, mutually separated emitter regions; and at least two emitter electrodes provided respectively on the emitter regions, wherein the base layer is exposed optically to an external optical radiation.Type: GrantFiled: August 17, 1995Date of Patent: October 14, 1997Assignee: Fujitsu LimitedInventors: Kenichi Imamura, Naoki Yokoyama
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Patent number: 5665998Abstract: A substantial portion of the material at the pn junction (27) of the photodiode (37, 41) having an implanted region extending to a surface thereof is selectively removed (39), leaving a very small junction region (35, 43) with the remainder of the p-type (23) and n-type (25) material of each photodiode being spaced apart or electrically isolated at what was originally the junction. In the ion implanted n-type on p-type approach, the majority of the signal is created in the implanted n-type region while the majority of the noise is generated in the p-type region. By selectively removing p-type material, n-type material or both from the pn junction of the diode or otherwise electrically isolating most of the p-type and n-type regions from each other at the pn junction and thereby minimizing the pn junction area, noise is greatly reduced without affecting the signal response of the photodiode.Type: GrantFiled: February 14, 1996Date of Patent: September 9, 1997Assignee: Texas Instruments IncorporatedInventors: Peter D. Dreiske, Arthur M. Turner, David I. Forehand
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Patent number: 5665985Abstract: A semiconductor device includes a semiconductor substrate, and a plurality of semiconductor layers formed on the semiconductor substrate and forming a concave lateral surface, the semiconductor layers including an active layer for either emitting light or receiving light, wherein the concave lateral surface is used as either a light-emitting surface or a light-receiving surface.Type: GrantFiled: August 5, 1996Date of Patent: September 9, 1997Assignee: Ricoh Company, Ltd.Inventor: Hirokazu Iwata
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Patent number: 5623158Abstract: This is a system and method of forming an electrical contact to the optical coating of an infrared detector. The method may comprise: forming thermal isolation trenches 22 in a substrate 20; depositing a trench filler 24 in the thermal isolation trenches 22; depositing a common electrode layer 31 over the thermal isolation trenches 22; depositing an optical coating 26 above the common electrode layer 31; mechanically thinning the substrate to expose the trench filler 24; etching to remove the trench filler 24 in the bias contact area; depositing a contact metal 34 on the backside of the substrate 20, wherein the contact metal 34 connects to the common electrode layer 31 at bias contact areas 34 around a periphery of the thermal isolation trenches; and etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20. Bias contact vias 23 may be formed in the bias contact areas and then filled with bias contact metal 49.Type: GrantFiled: June 7, 1995Date of Patent: April 22, 1997Assignee: Texas Instruments IncorporatedInventors: Steven N. Frank, James F. Belcher, Charles E. Stanford, Robert A. Owen, Robert J. S. Kyle
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Patent number: 5610416Abstract: A SAM avalanche photodiode formed with an epitaxially regrown guard ring and a planar P-N junction defined between a cap layer and a multiplication layer. The multiplication layer is part of a multi-layer semiconductor platform having a conductivity opposite to the conductivity type of the cap layer, including a light absorption layer, a substrate and an intermediate layer. A second embodiment of the present invention is disclosed including a SAM avalanche photodiode having a guard ring with a variable distribution of impurity dopant concentrations. In addition, a third embodiment of the present invention is disclosed in which a narrow band gap layer completely covers the cap layer and a non-alloy metal contact is formed to completely cover the narrow band gap layer, forming a mirror junction. In this embodiment, incident light is shined through the substrate and reflected from the mirror junction, enhancing the absorption efficiency.Type: GrantFiled: February 16, 1995Date of Patent: March 11, 1997Assignee: Hewlett-Packard CompanyInventors: Chung-Yi Su, Ghulam Hasnain, James N. Hollenhorst
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Patent number: 5608255Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration using a lattice determining surrogate substrate and a mesa-forming deep etch processing sequence and then inverted onto a new permanent substrate member and the surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Fabrication of the device from two possible indium-inclusive semiconductor materials and a particular gate metal alloy is also disclosed.Type: GrantFiled: May 17, 1995Date of Patent: March 4, 1997Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Eric A. Martin, Kenneth Vaccaro, William Waters, Joseph P. Lorenzo, Stephen Spaziani
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Patent number: 5581108Abstract: Disclosed is an optical switch device for totally reflecting an incident light therein in accordance with a change in refractive index occurring owing to current application, which is manufactured by the steps of: sequentially forming an optical waveguide layer, an n-InP clad layer and an n-InGaAs cap layer on a main surface of an n-InP substrate using an epitaxial growing; selectively etching the n-InGaAs cap layer to form an opening tapered downward; diffusing an impurity into the n-InP clad layer through the opening and into the n-InGaAs cap layer to a predetermined depth from a surface thereof so as to form a first impurity diffused region in the n-InP clad layer under the opening and to form a second impurity diffused region along the surface of the n-InGaAs cap layer; etching the layers on the optical waveguide layer using a mask to form a ridge-shaped waveguide; and forming electrodes on the n-InGaAs cap layer and an exposed surface of the n-InP clad layer and on a surface which is opposite to the mainType: GrantFiled: September 7, 1994Date of Patent: December 3, 1996Assignee: Electronics & Telecommunications Research InstituteInventors: Hong-Man Kim, Kwang-Ryong Oh, Ki-Sung Park, Chong-Dae Park
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Patent number: 5578858Abstract: The invention relates to an infrared radiation absorption device, which can be unrestrictedly produced from CMOS technology methods and materials. The absorber structure according to the invention comprises a lower layer (1) with a low transmission coefficient, a central layer (2) with a high absorption coefficient and an upper, absorbing component (3) with a low reflection coefficient for the radiation to be absorbed and which is applied from above. The upper component can e.g. comprise depressions in the central layer, whose walls are coated with metal. The absorber structure is used in the inexpensive manufacture of integrated, thermal infrared detectors.Type: GrantFiled: April 13, 1995Date of Patent: November 26, 1996Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.Inventors: Michael Mueller, Ralf Gottfried-Gottfried, Heinz Kueck
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Patent number: 5574304Abstract: A superluminescent diode includes a semiconductor substrate of a first conductivity type. A lower cladding layer of the first conductivity type is provided on the semiconductor substrate. An active layer is provided on the lower cladding layer. An upper cladding layer of a second conductivity type opposite to the first conductivity type is provided on the active layer. A current blocking layer of the first conductivity type is buried in the upper cladding layer. The current blocking layer has a stripe-shaped groove serving as a current-injection region. The current-injection region is formed in a manner that it extends from an end face of a chip to the inside of the chip, and has a length shorter than that of the chip. The current blocking layer is made of a material having a band gap energy not greater than that of the active layer and a refractive index not smaller than that of the active layer so that light advancing in the active layer is absorbable.Type: GrantFiled: February 24, 1995Date of Patent: November 12, 1996Assignee: Rohm Co., Ltd.Inventors: Masato Mushiage, Tatsuo Yamauchi, Yukio Shakuda
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Patent number: 5567976Abstract: photosensor device (41) having tapered photodiodes (53, 55) that are interdigitated and which is compatible with typical ASIC, CMOS and BiCMOS processes. A left side photodiode array of tapered regions (53) of a first conductivity type is disposed into an epitaxial layer of a second conductivity type. This array of photodiodes is coupled together and further coupled to a first output terminal (43). A fight side photodiode array of tapered regions (55) of said first conductivity type is disposed into the epitaxial layer of the second conductivity type, spaced apart from the left side photodiode by a minimum distance. A second output terminal is coupled to the array of fight side photodiodes (51). An incident light spot (39) is focused onto the sensor. The amount of current generated at the first and second output terminals (43, 51) will be proportional to the area of the left photodiode array and the area of the fight photodiode array which is receiving light.Type: GrantFiled: May 3, 1995Date of Patent: October 22, 1996Assignee: Texas Instruments IncorporatedInventors: Eugene G. Dierschke, John H. Berlien, Jr.
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Patent number: 5557131Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with an elevated emitter structure. An elevation structure raises the BJT emitter above the plane of the base. The elevation structure increases travel distance between a heavily doped base contact region and the emitter and protects against encroachment without increasing the total surface area allocated to the BJT device. A spacer oxide separates the polysilicon base contact and the elevation structure.Type: GrantFiled: July 14, 1994Date of Patent: September 17, 1996Assignees: AT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.Inventor: Steven Lee
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Patent number: 5552616Abstract: A light detecting device of the present invention comprises a third semiconductor layer containing a second conductive impurity which is formed in the upper part of a semiconductor layer containing a first conductive impurity and a fourth semiconductor layer containing the second conductive impurity which is formed in the semiconductor layer around the third semiconductor layer with an interval between the layers.Type: GrantFiled: December 7, 1995Date of Patent: September 3, 1996Assignee: Fujitsu LimitedInventor: Masahiro Kobayashi
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Patent number: 5541438Abstract: An improved Metal Semiconductor Metal (MSM) photodiode device and a fabrication process for realizing this device. The improved photodiode device employs frontside electrodes and backside illumination to avoid active area shadowing in the device. This configuration is achieved through a device fabrication sequence which involves substrate removal--and replacement at the device's opposed frontside surface using such media as an epoxy adhesive. The disclosed device uses gallium arsenide semiconductor materials that are lattice determined by an indium phosphide sacrificial initial substrate, in order to select a desired input energy spectral range.Type: GrantFiled: May 17, 1995Date of Patent: July 30, 1996Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Eric A. Martin, Kenneth Vaccaro, Joseph P. Lorenzo
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Patent number: 5536964Abstract: A thin-film semiconductor pinhole component with monolithically integrated position-sensing photodetectors is herein referred to as a Position Sensitive Pinhole (PSP). Another embodiment is also discussed where a PSP is integrated onto a platform with controllable motion and is herein referred to as a Movable Position Sensitive Pinhole (MPSP). A third embodiment describes the MPSP with capacitive, electrostatic actuation incorporated into the device to achieve controlled motion, herein referred to as a Capacitively Actuated Movable Position Sensitive Pinhole (CAMPSP). Each of those embodiments of the present invention are discussed, as are their method of manufacture and use in a laser environment as a spatial filter.Type: GrantFiled: September 30, 1994Date of Patent: July 16, 1996Inventors: Evan D. H. Green, Tario M. Haniff, Albert K. Hu
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Patent number: 5536965Abstract: Thermal isolation mesas 36 comprising a porous material 64 are used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous material 64 is preferably a silicon-dioxide xerogel. The mesas 36 may also comprise a protective film 66.Type: GrantFiled: June 7, 1995Date of Patent: July 16, 1996Assignee: Texas Instruments IncorporatedInventors: Howard R. Beratan, Chih-Chen Cho, Scott R. Summerfelt
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Patent number: 5530266Abstract: A liquid crystal image display unit created on a substrate non-transparent to the light in the visible radiation area, characterized in that a portion beneath a liquid crystal pixel part on said substrate is removed, so that the light is made transmissive through said liquid crystal pixel part.Type: GrantFiled: May 13, 1994Date of Patent: June 25, 1996Assignee: Canon Kabushiki KaishaInventors: Takao Yonehara, Mamoru Miyawaki, Akira Ishizaki, Junichi Hoshi, Masaru Sakamoto, Shigetoshi Sugawa, Shunsuke Inoue, Toru Koizumi, Tetsunobu Kohchi, Kiyofumi Sakaguchi, Takanori Watanabe
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Patent number: 5510644Abstract: An improved x-ray detector in the form of a p-i-n CdTe homojunction device is disclosed. The intrinsic ("i") layer is of high resistivity CdTe, while the n- and p-doped CdTe layers are epitaxially grown in a photo-assisted process in a molecular beam epitaxial apparatus. The n-dopant is conveniently indium, with an indium metal contact. The "i" layer is optionally epitaxially grown in a photo-assisted process. The p-dopant is preferably arsenic. A PAMBE formed mercury telluride contact layer enhances the ohmic contact to the p-layer, and a gold contact is provided to the contact layer. The use of the PAMBE technique facilitates high quality crystal growth and activation of the dopants. The resulting CdTe p-i-n homojunction device has a wide band gap (1.45 eV) essential to room temperature operation.Type: GrantFiled: September 23, 1994Date of Patent: April 23, 1996Assignee: Martin Marietta CorporationInventors: Karl A. Harris, Thomas H. Myers, II, Robert W. Yanka
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Patent number: 5508206Abstract: Thin semiconductor devices, such as thin solar cells, and a method of fabricating same are disclosed. A microblasting procedure is employed to thin a semiconductor wafer or substrate, such as a solar cell wafer, wherein fine abrasive particles are used to etch away wafer material through a mask. Thick areas remain at the perimeter of the semiconductor device or solar cell, in regions of the semiconductor device or solar cell behind the front interconnect attachment pads, and at corresponding rear interconnect attachment areas. In addition, there are thick areas in a pattern that comprise interconnected beams that support the thin wafer areas. Consequently, predetermined areas of the wafer are thinned to form a predetermined structural pattern in the wafer that includes an external frame and a plurality of interconnected beams.Type: GrantFiled: March 28, 1995Date of Patent: April 16, 1996Assignee: Spectrolab, Inc.Inventors: Gregory S. Glenn, B. Terence Cavicchi
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Patent number: 5498904Abstract: A semiconductive film is formed on a substrate having a surface with indentations defining a plurality of plane regions and elevated step difference portions between adjacent plane regions. The semiconductive film is irradiated with energy beams to be polycrystallized, whereby the positions of the crystal grain boundaries in the polycrystalline semiconductive film are controlled.Type: GrantFiled: September 27, 1994Date of Patent: March 12, 1996Assignee: Sanyo Electric Co., Ltd.Inventors: Yasuki Harata, Masaaki Kameda, Keiichi Sano, Yoichiro Aya
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Patent number: 5448099Abstract: In a optoelectronic integrated circuit, a pin-type light receiving device and an electronic circuit device are electrically connected to each other and monolithically integrated on a semiconductor substrate. In the pin-type light receiving device, an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer are sequentially formed on the semiconductor substrate and sequentially formed into mesa shapes. The first mesa is constituted by the p-type semiconductor layer, and the second mesa is constituted by the i-type semiconductor layer. The boundary surface between the first and second mesas is formed to match the junction surface between the p-type semiconductor layer and the i-type semiconductor layer. The diameter of the first mesa is formed smaller than that of the second mesa.Type: GrantFiled: March 1, 1994Date of Patent: September 5, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventor: Hiroshi Yano
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Patent number: 5444274Abstract: A photodetector of the present invention is devised to reduce the dark current by employing a novel guard ring structure suitable for a mesa type photodiode (PD). Namely, the PD of the present invention has the structure in which a p-type or n-type semiconductor region which is to be a light receiving area is surrounded by a semiconductor region (guard ring) of the same conduction type. A guard ring electrode is formed on the guard ring region and is kept at the same potential as an electrode on a region desired to reduce the dark current. Also, an opto-electronic integrated circuit of the present invention has such a structure that a PD, which is the photodetector of the present invention, and a circuit element such as a transistor are formed on a common semiconductor substrate and that an anode electrode or a cathode electrode of the PD is conductively connected to a gate electrode of a field-effect transistor or to a base electrode of a bipolar transistor.Type: GrantFiled: July 6, 1994Date of Patent: August 22, 1995Assignee: Sumitomo Electric Industries Ltd.Inventor: Goro Sasaki
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Patent number: 5414294Abstract: A radiation detector includes a photovoltaic diode mesa structure (16) having of a plurality of sub-mesa structures (16a, 16b). Each of said sub-mesa structures includes a first layer (14a) of semiconductor material having a first type of electrical conductivity and a second layer (14b) having a second type of electrical conductivity such that a p-n junction is formed between the first and the second layers. Metalization (24) is disposed within a trench (30a) that runs between the sub-mesas and includes a tab portion (24a) that extends upwardly over a sidewall of each of said sub-mesa structures so as to electrically contact the second layer contained within each. As a result, each of said sub-mesa structures are electrically connected in parallel.Type: GrantFiled: March 31, 1993Date of Patent: May 9, 1995Assignee: Santa Barbara Research CenterInventors: Russell D. Granneman, William O. McKeag
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Patent number: 5412249Abstract: An n.sup.- -type InP buffer layer is formed on an n-type InP substrate. An n.sup.- -type InGaAs light absorbing layer is formed on the n.sup.- -type InP buffer layer. An n.sup.- -type InP cap layer is formed on the n.sup.- -type InGaAs light absorbing layer. A p-type InP region is formed in the InP cap layer. A layered electrode having a contact with the p-type InP region comprises a first layer made of an Au layer, a second layer made of a Ti layer or the like, a third layer made of a Pt layer or the like, and a fourth layer made of an Au layer. The first layer made of Au has a thickness of 1 to 500 nm. This structure improves an ohmic ability and a peel strength at a contact portion where an electrode is connected, and simplifies manufacturing steps.Type: GrantFiled: March 17, 1994Date of Patent: May 2, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Hyugaji, Reiji Ono
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Patent number: 5406109Abstract: A miniature electronic element is provided formed of and within a single crystal of semiconductor material on which are formed top and bottom surface layers of an oxide of the semiconductor material, and including at least one isolated island of semiconductor material formed in the remaining material between the top and bottom surface layers. Contact members may be attached in predetermined spatial relation to at least one of the top and bottom surface layers and extend through the one surface to the island of material connecting thereto in spaced relation, whereby the material of the island between the contact members provides an electrical path of predetermined value between the contact members. An isolating chamber (or chambers) is formed between the surface layers around the isolated island of material to provide thermal isolation to the island of material.Type: GrantFiled: October 28, 1992Date of Patent: April 11, 1995Inventor: Julie G. Whitney
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Patent number: 5401986Abstract: A photoresponsive device wherein the device includes semiconductor material, such as a cap region (14a), comprised of elements selected from Group IIB-VIA. A molybdenum contact pad (16) is formed upon a surface of the cap region, and a molybdenum ground contact pad is formed on a surface of a base region (12). A wide bandgap semiconductor passivation layer (20) overlies the surface of the cap region and also partially overlies the molybdenum contact pad. A dielectric layer (22) overlies the passivation layer, and an indium bump (24) is formed upon the molybdenum contact pad. The dielectric layer is in intimate contact with side surfaces of the indium bump such that no portion of the molybdenum contact pad can be physically contacted from a top surface of the dielectric layer. This method eliminates the possibility of unwanted chemical reactions occurring between the In and the underlying contact pad metal.Type: GrantFiled: July 5, 1994Date of Patent: March 28, 1995Assignee: Santa Barbara Research CenterInventors: Charles A. Cockrum, Francis I. Gesswein, Eric F. Schulte
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Patent number: 5397400Abstract: A thin-film solar cell includes a thin active layer of high purity material having opposed front and rear surfaces for light-to-electricity conversion, a structure for supporting the thin active layer, and a rear electrode in contact with the rear surface of the active layer. The supporting structure includes a supporting substrate of a low purity material having opposed front and rear surfaces, on the front surface of which the rear surface of the active layer is disposed, and an insulating barrier layer interposed between the front surface of the supporting substrate and the rear surface of the active layer. The barrier layer prevents impurities in the supporting substrate from diffusing into the active layer. Since the supporting substrate comprises a low purity material, the quantity of the expensive high purity material can be reduced by reducing the thickness of the active layer, resulting in low production costs.Type: GrantFiled: July 21, 1993Date of Patent: March 14, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshinori Matsuno, Hideo Naomoto, Satoshi Arimoto, Hiroaki Morikawa, Hajime Sasaki
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Patent number: 5394005Abstract: A silicon carbide photodiode exhibiting high short-wavelength sensitivity, particularly in the ultraviolet spectrum, and very low reverse leakage current includes a p type conductivity 6H crystalline substrate. A first p- silicon carbide crystalline layer is epitaxially grown on the body. A second n+ silicon carbide crystalline layer is epitaxially grown on the first layer and forms a p-/n+ junction with the first layer. A metallic upper contact layer is formed on a predetermined surface region of the second layer oppositely situated from the junction. The second layer is of a uniform minimum thickness, generally less than 1000 Angstroms, with a greater thickness, typically 3000-4000 Angstroms, beneath the predetermined surface region. The thicker portion of the second layer occupies less than 10% and generally less than 1% of the total second layer surface area.Type: GrantFiled: February 18, 1994Date of Patent: February 28, 1995Assignee: General Electric CompanyInventors: Dale M. Brown, John A. Edmond
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Patent number: 5386139Abstract: A semiconductor light emitting element in which light leakage from the vicinity of an active layer end thereof is significantly reduced, and an interval at which the element is disposed is sufficiently narrow, so that there can be realized an optimal distance-measuring accuracy when used for a light source of a camera's automatic focusing mechanism.Type: GrantFiled: April 15, 1993Date of Patent: January 31, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Yasuo Idei, Toshio Shimizu
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Patent number: 5370747Abstract: A photovoltaic device including a substrate, a first electrode layer provided on the substrate, a photoelectric conversion layer provided on the first electrode, and a second electrode layer provided on the photoelectric conversion layer. A discontinuous interfacial layer is provided at at least one of the interfaces between a first conductivity type layer and a photoactive layer provided in the photoelectric conversion layer, between the photoactive layer and a second, opposite conductivity type layer of the photoelectric conversion layer, and between the photoelectric conversion layer and the second electrode layer. The at least one interface provided with the discontinuous interfacial layer may be so textured that portions of the interface not provided with interfacial layers project toward the substrate.Type: GrantFiled: November 23, 1992Date of Patent: December 6, 1994Assignee: Sanyo Electric Co., Ltd.Inventors: Shigeru Noguchi, Hiroshi Iwata, Keiichi Sano
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Patent number: 5365087Abstract: A photodetector of the present invention is devised to reduce the dark current by employing a novel guard ring structure suitable for a mesa type photodiode (PD). Namely, the PD of the present invention has the structure in which a p-type or n-type semiconductor region which is to be a light receiving area is surrounded by a semiconductor region (guard ring) of the same conduction type. A guard ring electrode is formed on the guard ring region and is kept at the same potential as an electrode on a region desired to reduce the dark current. Also, an opto-electronic integrated circuit of the present invention has such a structure that a PD, which is the photodetector of the present invention, and a circuit element such as a transistor are formed on a common semiconductor substrate and that an anode electrode or a cathode electrode of the PD is conductively connected to a gate electrode of a field-effect transistor or to a base electrode of a bipolar transistor.Type: GrantFiled: July 12, 1993Date of Patent: November 15, 1994Assignee: Sumitomo Electric Industries, Ltd.Inventor: Goro Sasaki
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Patent number: 5359207Abstract: The present invention is a novel book scanner that employs 2-dimensional array detectors attached, either rigidly or rotatably, at a common edge and disposed in a wedge shaped manner. The opposite edges of the arrays are housed in a base portion. The base portion additionally supports backlight to provide the necessary illumination of the book pages and the read-out electronics which output the image data stored in the detectors to other processing units that may use such data.Type: GrantFiled: November 29, 1993Date of Patent: October 25, 1994Assignee: Xerox CorporationInventor: William D. Turner
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Patent number: 5357122Abstract: An optical-electronic integrated circuit device capable of three-dimensionally transmitting optical signals between plural semiconductor substrates on each of which an integrated circuit is previously formed. At least one of the light emitting elements and the light receiving elements are formed on the semiconductor substrate which transmits the light propagated between these elements. In this manner, signals may be transmitted in a direction perpendicular to the semiconductor substrate even without specifically processing the semiconductor substrate. Additionally, signal distortion, transmission losses, mutual intervention or delay are not incurred.Type: GrantFiled: September 2, 1992Date of Patent: October 18, 1994Assignee: Sony CorporationInventors: Akihiko Okubora, Chiaki Takano, Kiyoshi Tanaka, Hideto Ishikawa
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Patent number: 5332910Abstract: A semiconductor light-emitting device includes a plurality of semiconductor rods, each of which has a pn junction. The semiconductor rods are formed on a semiconductor substrate such that the plurality of semiconductor rods are arranged at a distance substantially equal to an integer multiple of the wavelength of light emitted from the semiconductor rod. With such devices, various novel optical devices such as a micro-cavity laser of which the threshold current is extremely small and a coherent light-emitting device having no threshold value can be realized.Type: GrantFiled: November 30, 1993Date of Patent: July 26, 1994Assignee: Hitachi, Ltd.Inventors: Keiichi Haraguchi, Kenji Hiruma, Kensuke Ogawa, Toshio Katsuyama, Ken Yamaguchi, Toshiyuki Usagawa, Masamits Yazawa, Toshiaki Masuhara, Gerard P. Morgan, Hiroshi Kakibayashi
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Patent number: 5324976Abstract: A controlled conductivity device utilizes incident phonons (1) to control conductivity. A body of material (2) is capable of changing its conductivity in response to the incident phonons by undergoing a metal-insulator transition.Type: GrantFiled: October 22, 1992Date of Patent: June 28, 1994Assignee: Hitachi, Ltd.Inventor: David A. Williams
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Patent number: 5321294Abstract: A shift register according to the present invention includes: a plurality of first electrodes; at least one second electrode; a voltage application unit for applying a voltage to each of the plurality of first electrodes; a plurality of optically bistable elements connected to each of the plurality of first electrodes and at least one second electrode; and an optical waveguide layer for optically coupling the plurality of optically bistable elements to each other.Type: GrantFiled: June 24, 1993Date of Patent: June 14, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toyoji Chino, Kenichi Matsuda
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Patent number: 5306647Abstract: A self-supporting layer of n-doped monocrystalline silicon is stripped from a substrate wafer of n-doped, monocrystalline silicon by electrochemical etching for manufacturing a solar cell. Holes are formed in the substrate wafer by electrochemical etching, particularly in a fluoride-containing, acidic electrolyte wherein the substrate wafer is connected as an anode. When a depth of the holes that essentially corresponds to the thickness of the self-supporting layer is reached, the process parameters of the etching are modified such that the self-supporting layer is stripped as a consequence of the holes growing together. The solar cell is manufactured from the self-supporting layer, and the method can be applied repeatedly on the same substrate wafer for stripping a plurality of self-supporting layers.Type: GrantFiled: December 30, 1992Date of Patent: April 26, 1994Assignee: Siemens AktiengesellschaftInventors: Volker Lehmann, Reinhard Stengl, Hermann Wendt, Wolfgang Hoenlein, Josef Willer
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Patent number: 5291057Abstract: A compound semiconductor device and a process for manufacturing it is disclosed. The process comprises the steps of forming a first conduction type first clad layer, a first conduction type or second conduction type activated layer, a second conduction type second clad layer, and a second conduction type cap layer upon a first conduction type semiconductor substrate, forming a first conduction type electrode and a second conduction type electrode, and forming a rectangular pole shaped laser diode, a triangular pole shaped detecting photo-diode, and a triangular pole shaped receiving photo-diode by carrying out a single round of anisotropic etching. According to the present invention, the high density can be easily realized, so that the power consumption and the manufacturing cost can be saved.Type: GrantFiled: November 6, 1991Date of Patent: March 1, 1994Assignee: Samsung Electronics Co., Ltd.Inventor: Seung H. Moon
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Patent number: 5291041Abstract: The present invention comprises a semi-insulating layer of GaAs with p+ and layers of aluminum gallium arsenide AlGaAs grown on one side of the semi-insulating GaAs and with p and n+ layers of AlGaAs grown on the other side of the semi-insulating GaAs. Ohmic contacts are grown on both sides of the thyristor as well as low temperature GaAs to provide for surface passivity.Type: GrantFiled: March 1, 1993Date of Patent: March 1, 1994Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Terence Burke, Maurice Weiner, Jian H. Zhao
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Patent number: 5285098Abstract: A method and structure are provided for internal photoemission detection. At least one groove (30a) is formed in a side of a semiconductor layer (32). A silicide film (58) is formed in each groove (30a) over the semiconductor layer (32). A metal contact region (44) is electrically coupled to the silicide film (58) such that a voltage at the metal contact region (44) indicates an intensity of radiation incident on the structure (28).Type: GrantFiled: April 30, 1992Date of Patent: February 8, 1994Assignee: Texas Instruments IncorporatedInventor: Sebastian R. Borrello
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Patent number: 5285514Abstract: In a waveguide type photodetector for receiving and detecting a light guided thereinto, a groove is formed in a semiconductor substrate, a waveguide layer is formed on the semiconductor substrate, and a light absorbing layer for absorbing a light propagated through a waveguide in the waveguide layer is formed on the waveguide layer. The waveguide is formed as a three-dimensional waveguide formed in the waveguide layer due to the presense of the groove. The three-dimensional waveguide is maintained also under the light absorbing layer since the refractive index of a portion layered on the groove formed in the substrate is made large than that of portions other than this portion layered above the groove.Type: GrantFiled: May 26, 1992Date of Patent: February 8, 1994Assignee: Canon Kabushiki KaishaInventors: Hidetoshi Nojiri, Tamayo Hirokio
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Patent number: 5285086Abstract: Semiconductor devices having a low density of dislocation defects can be formed of epitaxial layers grown on defective or misfit substrates by making the thickness of the epitaxial layer sufficiently large in comparison to the maximum lateral dimension. With sufficient thickness, threading dislocations arising from the interface will exit the sides of the epitaxial structure and not reach the upper surface. Using this approach, one can fabricate integral gallium arsenide on silicon optoelectronic devices and parallel processing circuits. One can also improve the yield of lasers and photodetectors.Type: GrantFiled: June 18, 1992Date of Patent: February 8, 1994Assignee: AT&T Bell LaboratoriesInventor: Eugene A. Fitzgerald, Jr.
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Patent number: 5281829Abstract: An optical semiconductor device includes a semiconductor laser buried with a current blocking layer, and a photodetector, such as a phototransistor, which are provided on a semiconductor substrate. In such a device, the photodetector has the same thickness and composition as those of the current blocking layer, and a groove is provided in the semiconductor substrate to define an emitting end surface of the semiconductor laser and a light detection surface of the photodetector opposed to each other.Type: GrantFiled: September 11, 1992Date of Patent: January 25, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Koyu Chinen