External Physical Configuration Of Semiconductor (e.g., Mesas, Grooves) Patents (Class 257/466)
  • Patent number: 6252251
    Abstract: A raised photodetector constructed to define an open channel extending between opposite edges of the photodetector and dimensioned for permitting light from laser to pass therethrough. The photodetector has a light-collecting region disposed in an outward facing wall recessed within the channel for collecting light from the laser.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: June 26, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Richard Bendicks Bylsma, Dominic Paul Rinaudo, Rory Keene Schlenker, Walter Jeffrey Shakespeare
  • Patent number: 6248948
    Abstract: A solar cell module comprises a plurality of unit cells connected in series, each of the unit cells comprising in this order an electrode, a first semiconductor layer having a first conductivity type and a second semiconductor layer having a second conductivity type. The electrode has a region not covered with the first semiconductor layer. The second semiconductor layer has a main region and a subregion which are separated by a groove. The main region of the second semiconductor layer in one unit cell is electrically connected to the region of the electrode not covered with the first semiconductor layer in another unit cell adjacent to the one unit cell. The region of the electrode not covered with the first semiconductor layer in the one unit cell is electrically connected to the subregion of the second semiconductor layer in the another unit cell. With this structure, it is possible to simplify the formation of a bypass diode and therefore provide a solar cell module with high reliability at a low cost.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: June 19, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsumi Nakagawa, Shoji Nishida, Yukiko Iwasaki
  • Patent number: 6246097
    Abstract: At a semiconductor photodetector 100, a photodetection portion 120 is formed on a first substrate surface 110a of a substrate 110. In addition, a recess 110d is formed at a second substrate surface 110b of the substrate 110 which faces opposite the first substrate surface 110a. This recessed portion 110d is formed as a wedge-type V-shaped groove with a forward mesa surface formed at a front surface thereof, and is formed approximately parallel to a side photodetection surface 110c of the substrate 110 which is approximately perpendicular to the second substrate surface 110b. A total reflection film is coated on the front surface of the recess 110d. In the semiconductor photodetector 100 structured as described above, an incoming light P1 entering through the side photodetection surface 110c is reflected at the recess 110d to enter the photodetection portion 120 from the side where the substrate 110 is provided. As a result, the incoming light P1 is sensed at the photodetection portion 120.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: June 12, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masanobu Kato, Ryozo Furukawa
  • Patent number: 6239354
    Abstract: A monolithically interconnected photovoltaic module having cells which are electrically connected which comprises a substrate, a plurality of cells formed over the substrate, each cell including a primary absorber layer having a light receiving surface and a p-region, formed with a p-type dopant, and an n-region formed with an n-type dopant adjacent the p-region to form a single pn-junction, and a cell isolation diode layer having a p-region, formed with a p-type dopant, and an n-region formed with an n-type dopant adjacent the p-region to form a single pn-junction, the diode layer intervening the substrate and the absorber layer wherein the absorber and diode interfacial regions of a same conductivity type orientation, the diode layer having a reverse-breakdown voltage sufficient to prevent inter-cell shunting, and each cell electrically isolated from adjacent cells with a vertical trench trough the pn-junction of the diode layer, interconnects disposed in the trenches contacting the absorber regions of adja
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: May 29, 2001
    Assignee: Midwest Research Institute
    Inventor: Mark W. Wanlass
  • Patent number: 6236097
    Abstract: A solid state microstructure comprises a substrate, a detector element extending outwardly from a surface of the substrate and having first and second electrodes on opposing sides thereof, the detector element incorporating an onboard electronically-triggered gating structure. The gating structure may for example be a third electrode.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: May 22, 2001
    Assignee: Imperial College of Science, Technology & Medicine
    Inventors: John Francis Hassard, Roland Smith
  • Patent number: 6232626
    Abstract: A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the trench photosensor.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: May 15, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 6229192
    Abstract: A method of manufacturing a PIN (positive-intrinsic-negative) diode structure includes depositing an insulation or dielectric layer over the bottom PIN diode electrodes, prior to depositing the PIN semiconductor layers. The insulation layer results in a PIN diode structure with reduced leakage current, reduced RIE (reactive ion etching) chamber contamination, the reduction or elimination of post RIE processing, improved yields, and/or expands the potential materials that may be used for the bottom electrode. A corresponding PIN diode structure is also disclosed. The resulting PIN diode structures may be used in, for example, LCD (liquid crystal display) and solid state imager applications.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: May 8, 2001
    Assignee: Ois Optical Imaging Systems, Inc.
    Inventor: Tieer Gu
  • Patent number: 6211532
    Abstract: A microprobe chip for detecting evanescent waves includes a photoconductive material and a substrate for supporting the photoconductive material. The photoconductive material is connected to electrodes formed on the substrate. A method for making a microprobe chip for detecting evanescent waves includes forming a film comprising a photoconductive material on a peeling layer of a first substrate, the film having a shape of the microprobe chip, and transferring the film on the peeling layer onto a junction layer provided on a second substrate. A method for making a probe provided with a microprobe chip for detecting evanescent waves includes forming a film comprising a photoconductive material and having the shape of the microprobe chip on a peeling layer of a first substrate, forming a thin film cantilever on a second substrate, and transferring the film on the peeling layer onto a junction layer formed on the thin film cantilever.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: April 3, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takayuki Yagi
  • Patent number: 6208007
    Abstract: Buried layers are formed within a semiconductor. Metallic or insulating buried layers are produced several microns within a semiconductor substrate. The buried layer can confine current to the buried layer itself by using a conductive material to create the buried layer. The buried layer can also confine current to a specified area of the semiconductor, by using an insulating material inside of the buried layer or by leaving a created void within the material. The buried layer is useful in the construction of a semiconductor Vertical Cavity Laser (VCL). A buried isolation layer confines the current to a narrow active region increasing efficiency of the VCL. The buried layer is also useful in fabricating discrete devices, such as diodes, transistors, and photodetectors, as well as fabricating integrated circuits.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: March 27, 2001
    Assignee: The Regents of the University of California
    Inventors: Dubravko Ivan Babic, John E. Bowers
  • Patent number: 6207975
    Abstract: An angle cavity resonant photodetector assembly (8), which uses multiple reflections of light within a photodetector (14) to convert input light into an electrical signal. The photodetector (14) has a combination of generally planar semiconductor layers including semiconductor active layers (20) where light is converted into an electrical output. The photodetector (14) is positioned relative to a waveguide (10), where the waveguide (10) has a waveguide active layer (22) located between a pair of waveguide cladding layers (24) and (26) and includes a first end (28) for receiving light and a second end (30) for transmitting the light to the photodetector (14). The photodetector (14) has a first reflector (12) and second reflector (16) that provides for multiple reflections across the semiconductor active layers (20).
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: March 27, 2001
    Assignee: TRW Inc.
    Inventors: Dean Tran, Eric R. Anderson, Edward A. Rezek
  • Patent number: 6204545
    Abstract: The present invention is a semiconductor device which has one or a plurality of spherical semiconductor elements as its main component. The spherical semiconductor element is a spherical semiconductor crystal with a photovoltaic part and a pair of electrodes. The present invention is also a semiconductor device of a semiconductor photocatalyst, photodiode or solar battery. The present invention is also a semiconductor device which has one or a plurality of spherical semiconductor elements as its main component. This spherical semiconductor element is a spherical semiconductor crystal with a pn junction and a pair of electrodes. Semiconductor devices of light-emitting diodes, various diodes, or display panels are disclosed. Referring to semiconductor photocatalyst 1 of the figure, a p-type diffusion layer 6 and a pn junction 7 is formed on an n-type silicon semiconductor spherical crystal.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: March 20, 2001
    Inventor: Josuke Nakata
  • Patent number: 6201257
    Abstract: An energy dispersive x-ray and gamma-ray photon counter is described. The counter uses a photon sensor which incorporates a unique photocathode called Advanced Semiconductor Emitter Technology for X-rays (ASET-X) as its critical element for converting the detected photons to electrons which are emitted into a vacuum. The electrons are multiplied by accelerations and collisions creating a signal larger than the sensor noise and thus allowing the photon to be energy resolved very accurately, to within ionization statistics. Because the signal is already above the sensor noise it does not have to be noise filtered therefore allowing high-speed counting. The photon sensor can also be used as a device to visualize and image gamma-ray and x-ray sources.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: March 13, 2001
    Assignee: Advanced Scientific Concepts, Inc.
    Inventors: Roger Stettner, Howard W. Bailey
  • Patent number: 6194771
    Abstract: A semiconductor light-receiving device includes a light-receiving section that receives an input light. The light-receiving section includes a light-receiving surface to which the input light is directed, a groove extending vertically into the light-receiving surface, and a thin film coated on the inside wall of the groove.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: February 27, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masanobu Kato, Ryozo Furukawa
  • Patent number: 6140570
    Abstract: A photovoltaic element having a specific transparent and electrically conductive layer on a back reflecting layer, said transparent and electrically conductive layer comprising a zinc oxide material and having a light incident side surface region with a cross section having a plurality of arcs arranged while in contacted with each other, said arcs having a radius of curvature in the range of 300 .ANG. to 6 .mu.m and an angle of elevation from the center of the curvature in the range of 30 to 155.degree., and said cross section containing regions comprising said plurality of arcs at a proportion of 80% or more, compared to the entire region of the cross section.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: October 31, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toshimitsu Kariya
  • Patent number: 6133615
    Abstract: Photodiode arrays are formed with close diode-to-diode spacing and minimized cross-talk between diodes in the array by isolating the diodes from one another with trenches that are formed between the photodiodes in the array. The photodiodes are formed of spaced regions in a base layer, each spaced region having an impurity type opposite to that of the base layer to define a p-n junction between the spaced regions and the base layer. The base layer meets a substrate at a boundary, with the substrate being much more heavily doped than the base layer with the same impurity type. The trenches extend through the base layer and preferably into the substrate. Minority carriers generated by absorption of light photons in the base layer can only migrate to an adjacent photodiode through the substrate. The lifetime and the corresponding diffusion length of the minority carriers in the substrate is very short so that all minority carriers recombine in the substrate before reaching an adjacent photodiode.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: October 17, 2000
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Henry Guckel, Shamus P. McNamara
  • Patent number: 6118916
    Abstract: A parallel light receiving OEIC comprising a light receiving OEIC layed out in an array form, the light receiving OEIC having an optical fiber fixing groove, provided on a silicon substrate, for efficiently introducing light from an optical fiber into a photodiode, wherein at least one optical fiber fixing groove is provided between light receiving ICs for respective channels. This constitution enables the substantial distance between channels to be increased without increasing the layout area, resulting in reduced interference of noises generated in respective channels with each other, which markedly reduces the influence of crosstalk without increasing the layout area of the parallel light receiving IC.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: September 12, 2000
    Assignee: NEC Corporation
    Inventors: Takenori Morikawa, Tsutomu Tashiro
  • Patent number: 6111299
    Abstract: A large area avalanche photodiode device that has a plurality of contacts formed on a bottom side that are isolated from each other by various kinds of isolation structures. In one embodiment, a cavity is formed in one layer of the avalanche photodiode that extends to a depletion region that exists in the layer as a result of a voltage applied to the device. The plurality of contacts are formed in the cavity so that each of the contacts are positioned substantially adjacent the depletion region. In another embodiment, a plurality of contacts are formed in a cavity and an isolation structure comprised of a grid of semiconductor material is formed so as to be interposed between adjacent contacts. The isolation structure preferably forms a p-n junction with the surrounding semiconductor material and the p-n junction provides isolation between adjacent contacts.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: August 29, 2000
    Assignee: Advanced Photonix, Inc.
    Inventors: Andrzej J. Dabrowski, Vladimir K. Eremin, Anatoly I. Sidorov
  • Patent number: 6093882
    Abstract: A solar cell and a method of producing the same which realizes electrical separation of the p n junction in a simple manner, and a method of producing a semiconductor device a method of producing a semiconductor device in which an electrode is formed by using a metallic paste material on a substrate covered with a silicon nitride film or a titanium oxide film, wherein a glass paste 104 composed mainly of glass which has a property of melting silicon is provided on an n type diffusion layer 101 in the p n junction; the substrate is baked so that penetration of the n type diffusion layer 101 is effected by the glass paste; aluminum is diffused in the n type diffusion layer 101 below a p electrode 103 formed of an aluminum silver paste to thereby form a p type inversion layer 105 inverted to a p type, whereby the electrical separation of the p n junction can be realized.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: July 25, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Satoshi Arimoto
  • Patent number: 6084175
    Abstract: Textured semi-conductor devices, such as macro textured buried-contact solar cells, are produced with special front contact trenches to increase efficiency and decrease costs. In order to produce the front contact trenches, front channels and narrower metallization grooves are cut in the semi-conductor body. The front contact trenches are plated to form attractive conductive buried contacts comprising flush metallization fingers and bus bars.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: July 4, 2000
    Assignee: Amoco/Enron Solar
    Inventors: James M. Perry, Srinvasamohan Narayanan, John H. Wohlgemuth, Steven P. Roncin
  • Patent number: 6075253
    Abstract: A semiconductor photodetector having a planar structure, including a first silicon layer having a first conductivity and formed with a recess, a silicon dioxide film covering a sidewall of the recess therewith, a germanium monocrystal layer formed in the recess, a first germanium layer having a first conductivity and sandwiched between the germanium monocrystal layer and the first silicon layer in the recess, a second germanium layer having a second conductivity and formed on the germanium monocrystal layer, and a second silicon layer having a second conductivity and formed on the second germanium layer. The first and second germanium layers prevent a depletion layer, which are generated in the germanium monocrystal layer when a voltage is applied to the semiconductor photodetector, from reaching the first and second silicon layers, respectively.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: June 13, 2000
    Assignee: NEC Corporation
    Inventors: Mitsuhiro Sugiyama, Toru Tatsumi
  • Patent number: 6072225
    Abstract: An interconnect in a microelectronic device is formed by forming a first mesa on a substrate. A first insulation layer is then formed on the substrate, the first insulation layer covering the first mesa to define a step at an edge thereof. A second mesa is formed on the first insulation layer adjacent the step, the second mesa being lower than the step. A second insulation layer is formed on the substrate, covering the second mesa and forming a step in the second insulation layer overlying the step in the first insulation layer. A spun-on-glass (SOG) layer on the second insulation layer, and then is planarized to expose a first portion of the second insulation layer at the step in the second insulation layer and to expose a second portion of the second insulation layer overlying the second mesa, thereby defining a planarized SOG region between the step and the second mesa.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: June 6, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-hyun Chang, Suck-tae Kim, Young-hun Park
  • Patent number: 6069394
    Abstract: A sapphire substrate, a buffer layer of undoped GaN and a compound semiconductor crystal layer successively formed on the sapphire substrate together form a substrate of a light emitting diode. A first cladding layer of n-type GaN, an active layer of undoped In.sub.0.2 Ga.sub.0.8 N and a second cladding layer successively formed on the compound semiconductor crystal layer together form a device structure of the light emitting diode. On the second cladding layer, a p-type electrode is formed, and on the first cladding layer, an n-type electrode is formed. In a part of the sapphire substrate opposing the p-type electrode, a recess having a trapezoidal section is formed, so that the thickness of an upper portion of the sapphire substrate above the recess can be substantially equal to or smaller than the thickness of the compound semiconductor crystal layer.
    Type: Grant
    Filed: April 8, 1998
    Date of Patent: May 30, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Tadao Hashimoto, Osamu Imafuji, Masaaki Yuri, Masahiro Ishida
  • Patent number: 6061606
    Abstract: A method of measuring overlay error comprises forming a first mask having a first alignment array comprising a periodic pattern of first features having a first periodicity, forming a second mask having a second alignment array comprising a pattern of second features having the first periodicity, the first alignment array being adjacent the second alignment array, the first alignment array and the second alignment array forming a combined alignment array, transforming the combined alignment array to produce a transformed array, selecting a first region within the transformed array, inverse transforming the region to produce geometric phase shift information, averaging the phase shift information, converting the averaged phase shift information into a value for misalignment in a first direction corresponding to the first region, repeating the selecting, inverse transforming, averaging and converting using a second region within the transformed array to calculate a value for misalignment in a second direction c
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: May 9, 2000
    Assignee: International Business Machines Corporation
    Inventor: Frances Mary Ross
  • Patent number: 6037642
    Abstract: A radiation-sensitive transducer with a doped semiconductor sensor is to be constructed on a mounting plate such that it does not deform during temperature fluctuations. On the back side of the mounting plate, i.e., the side opposite the side on which the semiconductor sensor is mounted, an additional element having the same dimensions as the semiconductor sensor is attached opposite the semiconductor sensor. The additional element is composed of the same semiconductor material as of the semiconductor sensor, but is undoped. Due to the corresponding size and material of the semiconductor sensor and the additional element, they respectively produce equal but opposite forces acting on the mounting plate during temperature fluctuations, so no deformation occurs.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: March 14, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventors: Klaus Ecker, Hartmut Sklebitz
  • Patent number: 6034405
    Abstract: The invention is a method and resulting device which provides a strong bond between a silicon substrate and an oxide component mounted within a cavity in the substrate. A layer of titanium, for example, is deposited on the walls of the cavity, followed by deposition of a layer of aluminum. The structure is preferably annealed to form titanium silicide and titanium-aluminum interface layers. The component is then bonded to the aluminum layer.
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: March 7, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Michael Francis Brady, Mindaugas Fernand Dautartas, James F. Dormer, Sailesh Mansinh Merchant, Casimir Roman Nijander, John William Osenbach
  • Patent number: 6023020
    Abstract: A solar cell utilizing a chalcopyrite semiconductor and reducing the density of defects on the junction interface of pn junctions is provided. This solar cell includes a substrate, a back electrode formed on the substrate, a p-type chalcopyrite semiconductor thin film formed on the back electrode, an n-type semiconductor thin film formed so as to constitute a pn junction with the p-type chalcopyrite semiconductor thin film, and a transparent electrode formed on the n-type semiconductor thin film. A material having a higher resistivity than the p-type chalcopyrite semiconductor is formed between the p-type chalcopyrite semiconductor thin film and the n-type semiconductor thin film. A thin film made of this material may be formed by deposition from a solution. For example, CuInS.sub.2 is formed on the surface of a p-type chalcopyrite based semiconductor such as CuInSe.sub.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: February 8, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mikihiko Nishitani, Takayuki Negami, Naoki Kohara, Takahiro Wada, Yasuhiro Hashimoto
  • Patent number: 6020620
    Abstract: A semiconductor light-receiving device including (a) a semiconductor substrate, (b) a multi-layered including a first buffer layer having a first electrical conductivity and lying on the semiconductor substrate, a first clad layer having a first electrical conductivity and lying on the first buffer layer, a light-absorbing layer having a first electrical conductivity and lying on the first clad layer, a second clad layer having a second electrical conductivity and lying on the light-absorbing layer, and a second buffer layer having a second electrical conductivity and lying on the second clad layer, (c) a first electrode formed on the second buffer layer, and (d) a second electrode formed on a lower surface of the semiconductor substrate. The multi-layered structure has at least one portion which is inclined to a direction in which a light introduced into the device is directed. For instance, the multi-layered structure has opposite end portions inclined to the direction.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: February 1, 2000
    Assignee: NEC Corporation
    Inventor: Atsuhiko Kusakabe
  • Patent number: 6013873
    Abstract: A photovoltaic apparatus includes a first conductive layer, a semiconductor layer and a second conductive layer on a substrate. The first conductive layer is divided into a first electrode layer and into a peripheral first electrode layer by the lower peripheral groove filled up with a first peripheral insulating material. The first upper peripheral groove is provided at the upper portion of the lower peripheral groove, to divide the semiconductor layer and the second conductive layer. The second peripheral insulating material is provided at the outer region of the lower peripheral groove to divide the semiconductor layer. The second upper part peripheral groove is provided at the upper part of the second peripheral insulating material to divide the semiconductor layer and the second conductive layer.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: January 11, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Naoki Daito, Toshihiro Nomura, Ryuji Okawa, Koji Katsube, Yoshinobu Takabatake
  • Patent number: 5994724
    Abstract: A photodetector design is disclosed for preventing an electrode from being broken. A recess portion is formed in a semiconductor substrate. A light absorbing layer is formed in the recess portion, and a buffer layer is formed on the light absorbing layer. A contact layer is formed on the buffer layer. The height of the light absorbing layer can be set to minimize the effect of a step caused by facet formation. An insulating layer is formed outside of a recess portion to project from a main surface of the substrate. The anode electrode is formed on the insulating layer and substantially outside of the recess and, as a result, the electrode is less likely to be broken.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: November 30, 1999
    Assignee: NEC Corporation
    Inventor: Takenori Morikawa
  • Patent number: 5994751
    Abstract: In an SOI substrate, an active zone is completely surrounded by a trench filled with insulating material. Disposed adjacent to the trench is a first doped zone which is formed, in particular, by out-diffusion from a doped layer disposed on the wall of the trench. The first doped zone and a second doped zone form a p-n junction of a photodiode.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: November 30, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventor: Klaus-Gunter Oppermann
  • Patent number: 5986206
    Abstract: Polymer based solar cells incorporate nanoscale carbon particles as electron acceptors. The nanoscale carbon particles can be appropriate carbon blacks, especially modified laser black. Conducting polymers are used in the solar cells as electron donors upon absorption of light. Preferred solar cell structures involve corrugation of the donor/acceptor composite material such that increased amounts of electricity can be produced for a given overall area of the solar cell.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: November 16, 1999
    Assignee: NanoGram Corporation
    Inventors: Nobuyuki Kambe, Peter S. Dardi
  • Patent number: 5977612
    Abstract: The present invention relates to electronic devices formed in crystallites of III-V nitride materials. Specifically, the present invention simplifies the processing technology required for the fabrication of high-performance electronic devices in III-V nitride materials.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: November 2, 1999
    Assignee: Xerox Corporation
    Inventors: David P. Bour, Fernando A. Ponce, G. A. Neville Connell, Ross D. Bringans, Noble M. Johnson, Werner K. Goetz, Linda T. Romano
  • Patent number: 5977604
    Abstract: Buried layers are formed within a semiconductor. Metallic or insulating buried layers are produced several microns within a semiconductor substrate. The buried layer can confine current to the buried layer itself by using a conductive material to create the buried layer. The buried layer can also confine current to a specified area of the semiconductor, by using an insulating material inside of the buried layer or by leaving a created void within the material. The buried layer is useful in the construction of a semiconductor Vertical Cavity Laser (VCL). A buried isolation layer confines the current to a narrow active region increasing efficiency of the VCL. The buried layer is also useful in fabricating discrete devices, such as diodes, transistors, and photodetectors, as well as fabricating integrated circuits.
    Type: Grant
    Filed: March 8, 1996
    Date of Patent: November 2, 1999
    Assignee: The Regents of the University of California
    Inventors: Dubravko Ivan Babic, John E. Bowers
  • Patent number: 5973260
    Abstract: The present invention discloses a converging type solar cell element able to restrain recombination of carriers and inflow of carriers into an embankment section and improve photoelectric conversion efficiency. A p.sup.+ diffusion layer 16 is formed on the surface of a sunlight receiving section 10 which is formed on a silicon substrate 12 comprising a p-type silicon. An energy gradient arises between the p.sup.+ diffusion layer 16 and the silicon substrate 12. Therefore, free electrons, which are minority carriers among the carriers generated in the silicon substrate 12 resulting from irradiation of sunlight to the sunlight receiving section 10, can be prevented from migrating to the surface side of the silicon substrate 12. Further, recombination of free electrons which may arise due to lattice defects of the surface can also be prevented. Still further, the p.sup.+ diffusion layer 16 may also be formed on a back surface side of the embankment section 14 which surrounds the sunlight receiving section 10.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: October 26, 1999
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kyoichi Tange, Tomonori Nagashima
  • Patent number: 5961742
    Abstract: For a converging solar cell element capable of preventing excessive concentration of converged sunlight to one point without lowering the degree of light convergence, a p+ layer 14 and an n+ layer 12 are formed on the rear surface of a silicon substrate; a positive pole 16 and a negative pole 18 are formed in response to the respective layers; and, on the front surface side, a light receiving surface 24 is formed with a bank portion 28 which enhances intensity in the surrounding area. In the central portion of the light receiving surface 24, a projected portion 26 is formed, which scatters converged sunlight and prevents the concentration of converged sunlight to one point.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: October 5, 1999
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kyoichi Tange, Tomonori Nagashima
  • Patent number: 5959339
    Abstract: An array (41) is comprised of a plurality of radiation detectors (10, 10') each of which includes a first photoresponsive diode (D1) having an anode and a cathode that is coupled to an anode of a second photoresponsive diode (D2). The first photoresponsive diode responds to electromagnetic radiation within a first band of wavelengths and the second photoresponsive diode responds to electromagnetic radiation within a second band of wavelengths. Each radiation detector further includes a first electrical contact (26) that is conductively coupled to the anode of the first photoresponsive diode; a second electrical contact (28) that is conductively coupled to the cathode of the first photoresponsive diode and to the anode of the second photoresponsive diode; and a third electrical contact (30) that is conductively coupled to a cathode of each second photoresponsive diode of the array. The electrical contacts are coupled during operation to respective bias potentials.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: September 28, 1999
    Assignee: Raytheon Company
    Inventors: George R. Chapman, Kenneth Kosai
  • Patent number: 5942788
    Abstract: A solid state image sensing device having a semiconductor substrate, a first diffusion region of a positive or negative conductive type provided on the semiconductor substrate, a plurality of second diffusion regions each of which is an opposite conductive type relative to the first diffusion region and is provided in the first diffusion region, and a semiconductor thin layer provided on at least the second diffusion regions.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: August 24, 1999
    Assignee: Minolta Co., Ltd.
    Inventors: Kenji Takada, Kouichi Ishida, Keiichi Nomura, Yoshihiro Hamakawa, Hiroaki Okamoto
  • Patent number: 5925897
    Abstract: An optoelectronic semiconductor diode is made from a layer of many small individual semiconductor particles containing doping junctions positioned between two contact surfaces mechanically supported by substrates. In the preferred embodiment, the particles are formed of a semiconductor, such as indium gallium nitride, as the active region. The particles are of a size on the order of 10 to 100 microns and are formed by reacting metallic gallium and indium with ammonia, or by a similar method. Electrical contacts are made to the particles by conductive films that have been deposited on the inner surfaces of the substrates. These contacts can be either reflective or transparent, depending upon the materials used. The particles each contain a p-n or similar junction, created either by diffusing in dopants or by selectively activating dopants that are already present. When a forward bias is applied to an LED, minority carriers spill over the junction and recombine with majority carriers to produce light.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: July 20, 1999
    Inventor: David B. Oberman
  • Patent number: 5923071
    Abstract: A semiconductor substrate having a silicon-on-insulator structure may achieve superior performance by utilizing a low oxygen content monocrystalline silicon thin film layer for device formation. A supporting substrate, which may comprise a transparent material, such as quartz, or which may be silicon, has an insulating film disposed thereover. The insulating film preferably has a lower diffusion coefficient with respect to impurities than the monocrystalline silicon thin film, which is provided thereover. In accordance with this structure, oxygen particles are not introduced into the monocrystalline thin film and the thin film has a low oxygen concentration to maximize the minority carrier lifetime, enhance device performance characteristics, and prevent the occurrence of latch up.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: July 13, 1999
    Assignee: Seiko Instruments Inc.
    Inventor: Yutaka Saito
  • Patent number: 5900631
    Abstract: A semiconductor crystal infrared detecting portion structure is provided in a photoconductive infrared detector and is provided at opposite ends with first and second electrodes so biased that the first and second electrodes have a positive potential and a ground potential respectively. The semiconductor crystal infrared detecting portion structure has an infrared receiving part so that the semiconductor crystal infrared detecting portion structure comprises a first half region defined between the infrared receiving part and the first electrode and a second half region defined between the infrared receiving part and the second electrode. At least the second half region reduces in section area toward the second electrode to increase a resistance of at least the second half region.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: May 4, 1999
    Assignee: NEC Corporation
    Inventor: Masahiko Sano
  • Patent number: 5889296
    Abstract: A photodetection device includes a collector layer, a collector electrode connected electrically to the collector layer, a base layer free from a junction region for contacting with an electrode, an emitter layer including at least two, mutually separated emitter regions; and at least two emitter electrodes provided respectively on the emitter regions, wherein the base layer is exposed optically to an external optical radiation.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Kenichi Imamura, Naoki Yokoyama
  • Patent number: 5880482
    Abstract: A low dark current metal-semiconductor-metal photodetector has an active region for receiving photons and generating charge carriers in the form of holes and electrons in response to the photons and an isolation region for allowing electrical coupling to occur without increasing the dark current. The photodetector is a III-V ternary semiconductor having its active region defined by a via through a dielectric layer. A pair of electrodes has contact portions extending into contact with the active region and terminating on the isolation region. One electrode of the pair provides a high Schottky barrier to holes.
    Type: Grant
    Filed: January 29, 1997
    Date of Patent: March 9, 1999
    Assignee: The Board of Trustees of the University of Illinios
    Inventors: Ilesanmi Adesida, Walter Wohlmuth, Mohamed Arafa, Patrick Fay
  • Patent number: 5866936
    Abstract: A mesa-structure avalanche photodiode in which a buffer region in the surface of the mesa structure effectively eliminates the sharply-angled, heavily doped part of the cap layer that existed adjacent the lightly-doped n-type multiplication layer and p-type guard ring before the buffer region was formed. This reduces electric field strength at the ends of the planar epitaxial P-N junction and prevents edge breakdown in this junction. The lateral extent of the guard ring is defined by a window formed in a masking layer prior to regrowth of the guard ring. This guard ring structure eliminates the need to perform additional processing steps to define the lateral extent of the guard ring and passivate the periphery of the guard ring.
    Type: Grant
    Filed: April 1, 1997
    Date of Patent: February 2, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Ghulam Hasnain, James N. Hollenhorst, Chung-Yi Su
  • Patent number: 5864158
    Abstract: Complementary metal-oxide-semiconductor (CMOS) transistors (18,22) are formed with vertical channel regions (30,52) on an insulator substrate (14). Highly doped polysilicon gates (44,68) are formed in trenches (36,58) to extend laterally around the channel regions (30,52) as insulatively displaced therefrom by gate insulators (41,62) that are grown on the sidewalls of the trenches (36,58). The transistors (18,22), which are formed in respective mesas (20,24) have deeply implanted source regions (28,50) that are ohmically connected to the semiconductor surface via respective source connector regions (34,70).
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: January 26, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yowjuang W. Liu, Donald L. Wollesen
  • Patent number: 5852322
    Abstract: A radiation-sensitive detector element has an active area which is formed between two adjoining layer areas of a layer arrangement and within which a conversion of incident electromagnetic radiation into electrical signals takes place. Taking into consideration the penetration depth of the radiation, the position of the active area in relation to the two limiting surfaces is selected in such a way that at least two layer areas for connecting the detector element to an evaluation circuit can be mounted on a surface located opposite the radiation-sensitive surface which is impinged by the incident radiation.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: December 22, 1998
    Assignee: Dr. Johannes Heidenhain GmbH
    Inventor: Peter Speckbacher
  • Patent number: 5831322
    Abstract: A large area avalanche photodiode device that has a plurality of contacts formed on a bottom side that are isolated from each other by various kinds of isolation structures. In one embodiment, a cavity is formed in one layer of the avalanche photodiode that extends to a depletion region that exists in the layer as a result of a voltage applied to the device. The plurality of contacts are formed in the cavity so that each of the contacts are positioned substantially adjacent the depletion region. In another embodiment, a plurality of contacts are formed in a cavity and an isolation structure comprised of a grid of semiconductor material is formed so as to be interposed between adjacent contacts. The isolation structure preferably forms a p-n junction with the surrounding semiconductor material and the p-n junction provides isolation between adjacent contacts.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: November 3, 1998
    Assignee: Advanced Photonix, Inc.
    Inventors: Andrzej J. Dabrowski, Vladimir K. Eremin, Anatoly I. Sidorov
  • Patent number: 5828118
    Abstract: An electromagnetic energy detector system down converts electromagnetic egy from a relatively high energy beyond the detectable range of an electromagnetic energy detector to a lower energy level within the detectable range of the electromagnetic energy detector. The detector includes a transparent substrate, a porous silicon structure formed on the substrate for down converting electromagnetic energy characterized by a first wavelength W1 to electromagnetic energy characterized by a second wavelength W2, where W2>W1; and an electromagnetic energy detector for detecting the down converted electromagnetic energy. The detector is useful in applications where the electromagnetic energy detector would ordinarily be incapable of detecting the higher level electromagnetic energy directly without going through the down conversion process effectuated by the porous silicon structure.
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: October 27, 1998
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Stephen D. Russell
  • Patent number: 5804833
    Abstract: A detector to be used for detecting photons from the visible to far infrared spectrum is described. The detector uses unique photocathodes called Advanced Semiconductor Emitter Technology (ASET) as its critical element for converting the detected photons to electrons which are emitted into a vacuum. The electron is multiplied by accelerations and collisions creating a signal larger than the sensor noise and thus allowing the photon to be detected. ASET is/composed of distinct detector and emitter technologies.
    Type: Grant
    Filed: October 10, 1996
    Date of Patent: September 8, 1998
    Assignee: Advanced Scientific Concepts, Inc.
    Inventors: Roger Stettner, Howard W. Bailey
  • Patent number: 5796118
    Abstract: A photodetection semiconductor device is constructed in such a manner that a photodiode light absorbing layer includes an Si/SiGe super-lattice layer (6), which forms a layer in parallel with the surface of a silicon substrate (1), and upper and lower P type low Ge concentration SiGe epitaxial layers (5) and (7), which sandwich the Si/SiGe super-lattice layer between them and contain Ge lower than a Ge content in the Si/SiGe super-lattice layer, a highly dense P+ type Si contact layer (8) is directly formed on the upper SiGe epitaxial layer (7) and a highly dense N+ type epitaxial layer (2) is formed immediately below the lower SiGe epitaxial layer (5). Preferably, Ge concentration in each of the upper and lower SiGe epitaxial layers (5) and (7) is set to be at least 1% or higher.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: August 18, 1998
    Assignee: NEC Corporation
    Inventors: Takenori Morikawa, Tsutomu Tashiro
  • Patent number: 5785768
    Abstract: A photo cell and a photo cell array which have high photoelectric conversion efficiency, little leakage current, long life, and high reliability, as well as a electrolytic device that employs the cell and array. The photo cell (1) comprises: a base material (2) consisting of p-type semiconductor; a light receiving section (3) being an integral spherical part of the base material (2) which protrudes outward from the surface of the base (2), and has an n-type semiconductor layer formed on the surface of said spherical part, so that a pn junction interface is formed between the base material (2) and the semiconductor layer; a front surface electrode (4) formed from conductive material in ohmic contact with a portion of the surface of the aforementioned sphere; and a lower or back electrode (5) formed from conductive material on the bottom of the aforementioned base material (2), to provide ohmic contact.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: July 28, 1998
    Inventor: Josuke Nakata