External Physical Configuration Of Semiconductor (e.g., Mesas, Grooves) Patents (Class 257/466)
  • Patent number: 7087832
    Abstract: Nanocomposite photovoltaic devices are provided that generally include semiconductor nanocrystals as at least a portion of a photoactive layer. Photovoltaic devices and other layered devices that comprise core-shell nanostructures and/or two populations of nanostructures, where the nanostructures are not necessarily part of a nanocomposite, are also features of the invention. Varied architectures for such devices are also provided including flexible and rigid architectures, planar and non-planar architectures and the like, as are systems incorporating such devices, and methods and systems for fabricating such devices. Compositions comprising two populations of nanostructures of different materials are also a feature of the invention.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: August 8, 2006
    Assignee: Nanosys, Inc.
    Inventors: Erik C. Scher, Mihai Buretea, Calvin Y. H. Chow, Stephen A. Empedocles, Andreas P. Meisel, J. Wallace Parce
  • Patent number: 7084044
    Abstract: The present invention provides an optoelectronic device and a method of manufacture thereof. In one embodiment, the method of manufacturing the optoelectronic device may include creating a multilayered optical substrate and then forming a self aligned dual mask over the multilayered optical substrate. The method may further include etching the multilayered optical substrate through the self aligned dual mask to form a mesa structure.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: August 1, 2006
    Assignee: TriQuint Technology Holding Co.
    Inventors: Charles W. Lentz, Bettina A. Nechay, Abdallah Ougazzaden, Padman Parayanthal, George J. Przybylek
  • Patent number: 7071524
    Abstract: A lower cladding layer is laminated on a substrate and constituted of at least one layer. A light absorption layer is laminated on the lower cladding layer. An upper cladding layer is laminated above the light absorption layer and constituted of at least one layer. A light incident end surface is provided on at least one of the substrate and the lower cladding layer, and, when a light is made incident at a predetermined angle, enables the light to be absorbed in the light absorption layer and to be output as a current. An equivalent refractive index of the at least one of the substrate and the lower cladding layer is larger than that of the upper cladding layer. The predetermined angle is an angle enabling a light incident into the light absorption layer to be reflected at a lower surface of the upper cladding layer.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: July 4, 2006
    Assignee: Anristsu Corporation
    Inventors: Kenji Kawano, Hiroaki Yoshidaya, Jun Hiraoka, Yuichi Sasaki
  • Patent number: 7067881
    Abstract: A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: June 27, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Takashi Ipposhi, Toshiaki Iwamatsu, Yuuichi Hirano
  • Patent number: 7045205
    Abstract: A nanostructured apparatus may include a mesoporous template having an array of regularly-spaced pores. One or more layers of material may conformally coat the walls to a substantially uniform thickness. Such an apparatus can be used in a variety of devices including optoelectronic devices, e.g., light emitting devices (such as LEDs, and lasers) and photovoltaic devices (such as solar cells) optical devices (luminescent, electro-optic, and magnetooptic waveguides, optical filters, optical switches, amplifies, laser diodes, multiplexers, optical couplers, and the like), sensors, chemical devices (such as catalysts) and mechanical devices (such as filters for filtering gases or liquids).
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: May 16, 2006
    Assignee: Nanosolar, Inc.
    Inventor: Brian M. Sager
  • Patent number: 7045832
    Abstract: Provided are a SiGe vertical optical path and a method for selectively forming a SiGe optical path normal structure for IR photodetection. The method comprises: forming a Si substrate surface; forming a Si feature, normal with respect to the Si substrate surface, such as a trench, via, or pillar; and, selectively forming a SiGe optical path overlying the Si normal feature. In some aspects, the Si substrate surface is formed a first plane and the Si normal feature has walls (sidewalls), normal with respect to the Si substrate surface, and a surface in a second plane, parallel to the first plane. Then, selectively forming a SiGe optical path overlying the Si normal feature includes forming a SiGe vertical optical path overlying the normal feature walls.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: May 16, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Douglas J. Tweet, Jong-Jan Lee, Jer-Shen Maa, Sheng Teng Hsu
  • Patent number: 6972469
    Abstract: A PIN diode includes a first p-area, an n-area, and in between an intermediate area on a first surface of a substrate, wherein a doping concentration of the intermediate area is lower than a doping concentration of the p-area and lower than a doping concentration of the n-area. Further, the PIN diode includes a first electrically conductive member, which is arranged on a side of the p-area, which faces away from the intermediate area, and a second electrically conductive member, which is arranged on a side of the n-area, which faces away from the intermediate area. The PIN diode is preferably separated from the substrate by an insulating layer, covered by a further insulating layer on the surface, which faces away from the substrate, and laterally surrounded by a trench filled with an insulating material, such that it is essentially fully insulated and encapsulated.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: December 6, 2005
    Assignee: Infineon Technologies AG
    Inventors: Raimund Peichl, Philipp Seng
  • Patent number: 6972477
    Abstract: To make thin a circuit device 10 in which are incorporated a plurality of types of circuit elements 12 that differ in thickness, first conductive patterns, onto which comparatively thin circuit elements 12A are mounted, are formed thickly, and second conductive patterns 11B, onto which comparatively thick second circuit elements 12B are mounted, are formed thinly. Also, fine wiring parts may be formed using the thinly formed second conductive patterns 12B. Thus even in the case where thick circuit elements are incorporated, by affixing such circuit elements onto the thinly formed second conductive patterns 11B, the total thickness can be made thin. Thinning of circuit device 10 as a whole can thus be accomplished.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: December 6, 2005
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Yusuke Igarashi, Nobuhisa Takakusaki, Jun Sakano, Noriaki Sakamoto
  • Patent number: 6963024
    Abstract: A solar cell module 60 has a plurality of solar cells 14 having a plurality of parallel grooves 8 on the individual light-receiving surfaces thereof, each of the grooves having an electrode 5 for extracting output on the inner side face (electrode-forming inner side face) on one side in the width-wise direction thereof; and a support 10, 50 for supporting the solar cells 14 in an integrated manner so as to direct the light-receiving surfaces upward. The annual power output can be increased by adjusting the direction of arrangement of the electrode-forming inner side faces of the grooves 8 while taking the angle of inclination ? of the light-receiving surface of the individual as-installed solar cells 14 relative to the horizontal plane and the latitude ? of the installation site of the solar cell module into consideration.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: November 8, 2005
    Assignees: Shin-Etsu Handotai Co., Ltd., Shin-Etsu Chemical Co., Ltd.
    Inventors: Satoyuki Ojima, Hiroyuki Ohtsuka, Masatoshi Takahashi, Takenori Watabe, Takao Abe
  • Patent number: 6946597
    Abstract: Photovoltaic devices, such as solar cells, and methods for their manufacture are disclosed. A device may be characterized by an architecture where two more materials having different electron affinities are regularly arrayed such that their presence alternates within distances of between about 1 nm and about 100 nm. The materials are present in a matrix based on a porous template with an array of template pores. The porous template is formed by anodizing a layer of metal. A photovoltaic device may include such a porous template disposed between a base electrode and a transparent conducting electrode. A first charge-transfer material fills the template pores, A second (complementary) charge-transfer material fills additional space not occupied by the first charge-transfer material.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: September 20, 2005
    Assignee: Nanosular, Inc.
    Inventors: Brian M. Sager, Martin R. Roscheisen, Klus Petritsch, Karl Pichler, Jacqueline Fidanza, Dong Yu
  • Patent number: 6946029
    Abstract: An inexpensive sheet with excellent evenness and a desired uniform thickness can be obtained by cooling a base having protrusions, dipping the surfaces of the protrusions of the cooled base into a melt material containing at least one of a metal material and a semiconductor material for crystal growth of the material on the surfaces of the protrusions. In addition, by rotating a roller having on its peripheral surface protrusions and a cooling portion for cooling said protrusions, the surfaces of the cooled protrusions can be dipped into a melt material containing at least one of a metal material and a semiconductor material for crystal growth of the material on the surfaces of the protrusions. Thus, a sheet with a desired uniform thickness can be obtained without slicing process.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: September 20, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Tsukuda, Hiroshi Taniguchi, Kozaburou Yano, Kazuto Igarashi, Hidemi Mitsuyasu, Tohru Nunoi
  • Patent number: 6943409
    Abstract: A semiconductor device is formed in on a semiconductor substrate starting with a first step, which is to form a wide trench and a narrow trench in the substrate. Then form a first electrode in the narrow trench by depositing a first fill material of a first conductivity type over the device to fill the wide trench partially and to fill the narrow trench completely. Etch back the first fill material until completion of removal thereof from the wide trench. Form a second electrode in the wide trench by filling the wide trench with a second fill material of an opposite conductivity type. Anneal to drive dopant both from the first fill material of the first electrode into a first outdiffusion region in the substrate about the periphery of the narrow trench and from the second fill material of the second electrode into a second outdiffusion region in the substrate about the periphery of the wide trench.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: September 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens
  • Patent number: 6940008
    Abstract: A solar cell module comprising a substrate, a filler, a photovoltaic element and a protective layer, wherein at least one of the substrate, the filler, the photovoltaic element and the protective layer is separable from other constituent members. Constituent members having been separated and still serviceable can be reused.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: September 6, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hidenori Shiotsuka, Ichiro Kataoka, Satoru Yamada, Shigeo Kiso, Hideaki Zenko
  • Patent number: 6919609
    Abstract: An opto-electronic device configured as a photodetector has a capacitor and/or resistor monolithically formed on a surface of the photodetector. The capacitor capacitively couples the AC ground of the photodetector to the bias terminal of the photodetector. The on chip capacitor design eliminates the inductance of external circuit traces between the power supply and an external capacitor. The resistor forces the AC return current of the photodetector through the AC ground in preference to the typical (DC bias terminal) path. Combinations of capacitors and resistors are particularly effective in reducing crosstalk among adjacent detectors in arrays.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: July 19, 2005
    Assignee: Optical Communication Products, Inc.
    Inventors: John Hart Lindemann, Michael Thomas Dudek, David Galt
  • Patent number: 6911713
    Abstract: An EA-DFB module including a DFB laser diode and an EA modulator formed on an InP first-conductivity-type substrate has a mesa stripe, a current blocking structure formed on both side surfaces of the mesa strip and a second InP cladding layer formed on top of the mesa stripe and the current blocking structure. The current blocking structure includes a Fe-doped semi-insulating film, a first conductivity-type buried layer and a carrier-depleted layer. The carrier-depleted layer reduces the parasitic capacitance at the boundary between the first-conductivity-type buried layer and the second InP cladding layer.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: June 28, 2005
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Nariaki Ikeda, Takeharu Yamaguchi, Satoshi Arakawa, Nobumitsu Yamanaka, Akihiko Kasukawa, Ryusuke Nakasaki
  • Patent number: 6909122
    Abstract: According to the present invention, a light-emitting semiconductor device has light-emitting elements separated by isolation trenches, preferably on two sides of each light-emitting element. The device may be fabricated by forming a single band-shaped diffusion region, then forming trenches that divide the diffusion region into multiple regions, or by forming individual diffusion regions and then forming trenches between them. The trenches prevent overlap between adjacent light-emitting elements, regardless of their junction depth, enabling a high-density array to be fabricated while maintaining adequate junction depth.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: June 21, 2005
    Assignee: Oki Data Corporation
    Inventors: Masumi Taninaka, Hiroyuki Fujiwara, Susumu Ozawa, Masaharu Nobori
  • Patent number: 6907150
    Abstract: The present invention provides an optical microbench having intersecting structures etched into a substrate. In particular, microbenches in accordance with the present invention include structures having a planar surfaces formed along selected crystallographic planes of a single crystal substrate. Two of the structures provided are an etch-stop pit and an anisotropically etched feature disposed adjacent the etch-stop pit. At the point of intersection between the etch-stop pit and the anisotropically etched feature the orientation of the crystallographic planes is maintained. The present invention also provides a method for micromachining a substrate to form an optical microbench. The method comprises the steps of forming an etch-stop pit and forming an anisotropically etched feature adjacent the etch-stop pit. The method may also comprise coating the surfaces of the etch-stop pit with an etch-stop layer.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: June 14, 2005
    Assignee: Shipley Company, L.L.C.
    Inventors: Dan A. Steinberg, Larry J. Rasnake
  • Patent number: 6906343
    Abstract: A method of manufacturing a semiconductor device with the use of a laser crystallization method is provided which can prevent grain boundaries from being formed in a channel forming region of a TFT and which can avoid substantial reduction in TFT mobility, reduction in on current, and increase in off current due to the grain boundaries, and a semiconductor device manufactured by using the manufacturing method is also provided. Stripe shape or rectangular shape unevenness is formed only in a driver circuit. Continuous wave laser light is irradiated to a semiconductor film formed on an insulating film along the stripe unevenness of the insulating film or along a major axis or minor axis of the rectangular unevenness. Although it is most preferable to use the continuous wave laser light at this point, pulse wave laser light may also be used.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: June 14, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6885786
    Abstract: A novel micromachining method in which dry etching and anisotropic wet etching are combined.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: April 26, 2005
    Assignee: Shipley Company, L.L.C.
    Inventors: Dan A. Steinberg, Jasean Rasnake
  • Patent number: 6878871
    Abstract: Nanocomposite photovoltaic devices are provided that generally include semiconductor nanocrystals as at least a portion of a photoactive layer. Photovoltaic devices and other layered devices that comprise core-shell nanostructures and/or two populations of nanostructures, where the nanostructures are not necessarily part of a nanocomposite, are also features of the invention. Varied architectures for such devices are also provided including flexible and rigid architectures, planar and non-planar architectures and the like, as are systems incorporating such devices, and methods and systems for fabricating such devices. Compositions comprising two populations of nanostructures of different materials are also a feature of the invention.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: April 12, 2005
    Assignee: Nanosys, Inc.
    Inventors: Erik Scher, Mihai A. Buretea, Calvin Chow, Stephen Empedocles, Andreas Meisel, J. Wallace Parce
  • Patent number: 6858462
    Abstract: Enhanced light absorption of solar cells and photodetectors by diffraction is described. Triangular, rectangular, and blazed subwavelength periodic structures are shown to improve performance of solar cells. Surface reflection can be tailored for either broadband, or narrow-band spectral absorption. Enhanced absorption is achieved by efficient optical coupling into obliquely propagating transmitted diffraction orders. Subwavelength one-dimensional structures are designed for polarization-dependent, wavelength-selective absorption in solar cells and photodetectors, while two-dimensional structures are designed for polarization-independent, wavelength-selective absorption therein. Suitable one and two-dimensional subwavelength periodic structures can also be designed for broadband spectral absorption in solar cells and photodetectors.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: February 22, 2005
    Assignees: Gratings, Inc., Sandia Corporation
    Inventors: Saleem H. Zaidi, James M. Gee
  • Patent number: 6853046
    Abstract: A photodiode array comprises a semiconductor substrate formed with an array of a plurality of pn junction type photodiodes on a light incident surface side, the surface opposite from the incident surface in the semiconductor substrate being made of a (100) plane; a through hole, formed in an area held between the photodiodes, penetrating through the semiconductor substrate from the incident surface side to the opposite surface side; and a conductive layer extending from the incident surface to the opposite surface by way of a wall surface of the through hole; the through hole being formed by connecting a vertical hole part formed substantially perpendicular to the incident surface on the incident surface side, and a pyramidal hole part formed like a quadrangular pyramid on the opposite surface side to each other within the semiconductor substrate; the pyramidal hole part having a wall surface formed as a (111) plane.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: February 8, 2005
    Assignee: Hamamatsu Photonics, K.K.
    Inventor: Katsumi Shibayama
  • Patent number: 6852920
    Abstract: Nano-architected/assembled solar cells and methods for their manufacture are disclosed. The solar cells comprise oriented arrays of nanostructures wherein two or more different materials are regularly arrayed and wherein the presence of two different materials alternates. The two or more materials have different electron affinities. The two materials may be in the form of matrixed arrays of nanostructures. The presence of the two different materials may alternate within distances of between about 1 nm and about 100 nm. An orientation can be imposed on the array, e.g. through solution deposition surfactant templation or other methods.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: February 8, 2005
    Assignee: Nanosolar, Inc.
    Inventors: Brian M. Sager, Martin R. Roscheisen
  • Patent number: 6849798
    Abstract: The present invention relates to the use of a nanocrystalline layer of Cu2O in the construction of photovoltaic cells to increase the ability of the photovoltaic cells to utilize UV radiations for photocurrent generation.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: February 1, 2005
    Assignee: General Electric Company
    Inventors: Chayan Mitra, Danielle Walker Merfeld, Gunasekaran Somasundaram
  • Patent number: 6844570
    Abstract: In the component of a radiation detector, an upper end face of a pad formation protrusion provided on an upper surface of an MID substrate is equal in height to an upper surface of a photodiode array, first pads are provided on upper surfaces of photodiodes arranged in the photodiode array, respectively, second pads are provided on the upper end face of the pad formation protrusion, a bonding wire is provided between one of the first pads and corresponding one of the second pads, a wiring pattern is provided on the upper surface of the MID substrate, first terminals as many as the second pads and one second terminal are provided on a lower surface of the MID substrate, the second pads and the first terminals are electrically connected to one another in a one-to-one correspondence, and the wiring pattern is electrically connected to the second terminal.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: January 18, 2005
    Assignee: Nihon Kessho Kogaku Co., Ltd.
    Inventors: Shigenori Sekine, Toshikazu Yanada
  • Patent number: 6838743
    Abstract: This invention relates an optoelectronic material comprising a uniform medium with a controllable electric characteristic; and semiconductor ultrafine particles dispersed in the medium and having a mean particle size of 100 nm or less, and an application device using the same.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: January 4, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuka Yamada, Takehito Yoshida, Shigeru Takeyama, Yuji Matsuda, Katsuhiko Mutoh
  • Patent number: 6825408
    Abstract: A stacked photoelectric conversion device comprising at least two photoelectric conversion element layers sandwiched between a first electrode layer and a light receiving second electrode layer, and at least one intermediate layer sandwiched between any two of said at least two photoelectric conversion element layers, wherein the intermediate layer has uneven surfaces on a light receiving side and a light outgoing side, the uneven surface on the latter having a greater average level difference than that on the former.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: November 30, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasue Nagano, Naoki Koide, Takanori Nakano, Mingju Yang, Yuji Komatsu
  • Patent number: 6825542
    Abstract: The present invention relates to a semiconductor photodetector. The photodetector is a waveguide photodetector, which comprises: a waveguide (1,2,3) having a III-V ridge structure including an active layer (1); a semiconductor layer (4) deposited on top of the ridge structure; and, metal detector electrodes (not shown) on the surface of the higher refractive index semiconductor layer (4). The semiconductor layer (4) has a higher refractive index than the waveguide structure (1,2,3). The ridge structure is configured to widen along the length of the waveguide (1,2,3) such that light passing through the active layer (1) of the waveguide couples more efficiently up into the higher refractive index semiconductor layer (4).
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: November 30, 2004
    Assignee: Denselight Semiconductors Pte Ltd
    Inventors: Yee Loy Lam, Yuen Chuen Chan, Chai Leng Terence Wee
  • Patent number: 6815790
    Abstract: The present invention improves the resolution and accuracy of the presently known two-dimensional position sensing detectors and delivers improved performance in the 1.3 to 1.55 micron wavelength region. The present invention is an array of semiconductor layers with four electrodes, the illustrative embodiment comprising a semi-insulating substrate semiconductor base covered by a semiconductor buffered layer, the buffered layer further covered by a semiconductor absorption layer and the absorption layer covered with a semiconductor layer. Four electrodes are placed on this semiconductor array: two on the top layer parallel to each other and near the ends of opposite edges, and two etched in the buffered layer, parallel to each other and perpendicular to the first set. The layers are doped as to make a p-n junction in the active area. Substantially all the layers, excepting the semi-insulating substrate layer, are uniformly resistive.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: November 9, 2004
    Assignee: Rapiscan, Inc.
    Inventors: Peter S. Bui, Narayan Dass Taneja
  • Patent number: 6815792
    Abstract: The present invention provides an epitaxially grown compound semiconductor film having a low density of crystal defects which are generated during the course of crystal growth of a compound semiconductor. The present invention also provides a compound semiconductor multi-layer structure including an n-type InP substrate, an n-type InP buffer layer, an undoped InGaAs light-absorbing layer, and an n-type InP cap layer, the layers being successively grown on the substrate through MOCVD. In the InGaAs layer, the compositional ratio of In/Ga is cyclically varied in a thickness direction (cyclic intervals: 80 nm) so as to fall within a range of ±2% with respect to a predetermined compositional ratio that establishes lattice matching between InGaAs and InP; specifically, within a range between 0.54/0.46 (i.e., In0.54Ga0.46As) and 0.52/0.48 (i.e., In0.52Ga0.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: November 9, 2004
    Assignee: Nippon Sheet Glass Company, Limited
    Inventors: Hisao Nagata, Yasunori Arima, Nobuyuki Komaba
  • Patent number: 6809391
    Abstract: A photodiode comprises an optical detection portion for detecting an optical signal and outputting a photoelectric conversion signal. The optical detection portion has a semiconductor substrate of a first conductive type and semiconductor layers of a second conductive type formed in spaced-apart relation in a surface of the semiconductor subtrate. A depletion layer is formed in the semiconductor subtrate by application of a reverse bias to the photodiode so as to surround the semiconductor layers. An etched surface portion of the depletion layer is disposed between the semiconductor layers so that an interface level region of the surface of the semiconductor substrate does not exist between the semiconductor layers.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: October 26, 2004
    Assignee: Seiko Instruments Inc.
    Inventor: Sumio Koiwa
  • Patent number: 6800914
    Abstract: Reducing a dark current in a semiconductor photodetector provided with a second mesa including an regrown layer around a first mesa. An n-type buffer layer, a n-type multiplication layer, a p-type field control layer, a p-type absorption layer, a cap layer made of p-type InAlAs crystal, and a p-type contact layer 107 are made to grow on a main surface of a n-type substrate. Thereafter the p-type contact layer, the p-type cap layer, the p-type absorption layer and the p-type field control layer are patterned to form a first mesa. Next, after making a p-type regrown layer selectively grow around the first mesa or by forming a groove in the regrow layer located in a vicinity of the p-type cap type during a step of the selective growth, the p-type cap layer containing Al and the regrow layer are separated owing to the groove such that no current path is formed between both layers.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: October 5, 2004
    Assignee: Opnext Japan, Inc.
    Inventors: Kazuhiro Ito, Shigehisa Tanaka, Sumiko Fujisaki, Yasunobu Matsuoka, Takashi Toyonaka
  • Patent number: 6791124
    Abstract: A sequential mesa type avalanche photodiode (APD) comprises a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: September 14, 2004
    Assignee: Anritsu Corporation
    Inventors: Jun Hiraoka, Kazuo Mizuno, Yuichi Sasaki
  • Patent number: 6787693
    Abstract: A photovoltaic generator constructed on an SOI N− layer subdivided into a series of connected isolated tubs whereby the isolated tubs are subdivided by a matrix of trenched wells. A P+ junction is formed into the top surface of each well to define a photovoltaic generator junction for its respective well.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: September 7, 2004
    Assignee: International Rectifier Corporation
    Inventor: Steven C. Lizotte
  • Patent number: 6780665
    Abstract: The disclosure describes an economical and environmentally benign method to recover crystalline silicon metal kerf from wiresaw slurries and to shape and sinter said recovered crystalline silicon kerf into thin-layer PV cell configurations with enhanced surface texture for metallization and reduced optical reflection losses.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: August 24, 2004
    Inventors: Romain Louis Billiet, Hanh Thi Nguyen
  • Patent number: 6777769
    Abstract: A light-receiving element, comprises an absorption layer formed on a semiconductor substrate, a window layer formed on the absorption layer, a first electrode formed on the window layer, a second electrode formed on the window layer and electrically connected to the first electrode, and a diffusion region which is formed in the absorption layer and the window layer and is formed between the first electrode and the substrate and between the second electrode and the substrate.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: August 17, 2004
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Takeshi Higuchi, Naoki Tsukiji
  • Patent number: 6777729
    Abstract: A radiometric quality semiconductor photodiode with one electrical contact extending from a p-n junction at the photodiode surface to the back of the photodiode substrate and a second contact formed on the back of the semiconductor substrate is provided and a method for manufacturing is presented. The electrical contact channel extending from the p-n junction to the photodiode substrate will be formed by dry etching and will require a cross sectional area of only 0.125 mm×0.125 mm.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: August 17, 2004
    Assignee: International Radiation Detectors, Inc.
    Inventors: Chad Prince, Raj Korde
  • Patent number: 6774448
    Abstract: An opto-electronic device configured as a photodetector has a capacitor and/or resistor monolithically formed on a surface of the photodetector. The capacitor capacitively couples the AC ground of the photodetector to the bias terminal of the photodetector. The on chip capacitor design eliminates the inductance of external circuit traces between the power supply and an external capacitor. The resistor forces the AC return current of the photodetector through the AC ground in preference to the typical (DC bias terminal) path. Combinations of capacitors and resistors are particularly effective in reducing crosstalk among adjacent detectors in arrays.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: August 10, 2004
    Assignee: Optical Communication Products, Inc.
    Inventors: John Hart Lindemann, Michael Thomas Dudek, David Galt
  • Patent number: 6770945
    Abstract: In a semiconductor photo-detector of the present invention, a first semiconductor layer, a second semiconductor layer having, and a photo-absorption part composed of a photo-absorption layer sandwiched between these layers are disposed on a substrate, at least the photo-absorption layer is formed at a position apart inwardly by a finite length from an end surface of the substrate, an end surface of the second semiconductor layer and the substrate or the end surface of the substrate is provided with a light incident facet angled inwardly as it separates from the surface of the second semiconductor or the surface of the substrate.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: August 3, 2004
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventor: Hideki Fukano
  • Patent number: 6762359
    Abstract: A method of producing a photovoltaic panel, including the steps of producing a light-transmitting, photovoltaic-element holding member which holds, along a reference surface, a plurality of photovoltaic elements each of which includes a P-type layer and an N-type layer, and forming, on one of opposite sides of the photovoltaic-element holding member, a first electrode which is electrically connected to the respective P-type layers of the photovoltaic elements, and a second electrode which is electrically connected to the respective N-type layers of the photovoltaic elements.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: July 13, 2004
    Assignee: Fuji Machine Mfg. Co., Ltd.
    Inventors: Koichi Asai, Yasuo Muto, Kazuya Suzuki, Kazutoshi Sakai
  • Patent number: 6753587
    Abstract: A high response speed semiconductor photo detecting device having a thin photo absorption layer which avoids an optical efficiency loss. The semiconductor photo detecting devices are formed on a semiconductor substrate having an inclined cleavage face to a principal plane of the substrate. An incoming photo signal is input to the cleavage face perpendicularly.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: June 22, 2004
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Akira Furuya, Tatsunori Shirai
  • Patent number: 6746880
    Abstract: A method for electrically contacting a rear side of a semiconductor substrate when processing the semiconductor substrate includes the step of placing the semiconductor substrate with a substrate rear side on a substrate holder such that an electrically conductive contact layer formed of a semiconductor material is disposed between the semiconductor substrate and the substrate holder.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: June 8, 2004
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Martin Franosch, Matthias Goldbach, Volker Lehmann, Jörn Lützen
  • Patent number: 6737718
    Abstract: A semiconductor device includes: a waveguide mesa structure including at least an optical absorption layer for photoelectric conversion; and a heat radiation semiconductor layer in contact directly with at least a part of the optical absorption layer for heat radiation from the optical absorption layer, and the heat radiation semiconductor layer being lower in refractive index and larger in energy band gap than the optical absorption layer.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: May 18, 2004
    Assignee: NEC Corporation
    Inventor: Takeshi Takeuchi
  • Patent number: 6730980
    Abstract: A multiple-trench photosensor for use in a CMOS imager having an improved charge capacity. The multi-trench photosensor may be either a photogate or photodiode structure. The multi-trench photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The multi-trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the multi-trench photosensor.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: May 4, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 6724798
    Abstract: The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top surface to the bottom surface, an optoelectronic structure and an ion implanted isolation moat, wherein the optoelectronic structure and the through wafer via are enclosed within the isolation moat. A method in accordance with the invention is a method of producing a device that includes the steps of forming an optoelectronic structure, forming a through wafer via, extending from a top surface to a bottom surface of the device and forming an ion implanted isolation moat, wherein the through wafer via and the optoelectronic structure are enclosed by the isolation moat.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: April 20, 2004
    Assignee: Honeywell International Inc.
    Inventors: Yue Liu, Klein L. Johnson, Steven M. Baier
  • Publication number: 20040070043
    Abstract: A CMOS image sensor is disclosed which has a photodiode formed by implanting ions into an area of a substrate. The photodiode surface area corresponds to about 15% to 40% of the surface area of a photoreceptor part region of the sensor. Thus, the capacitance associated with the photodiode is reduced relative to prior art photodiodes, and, thus, the output signals generated by the detected light are increased. Further, by reducing the size of the photodiode in manufacturing the CMOS image sensor, the junction region is reduced to thereby improve the absorption efficiency of light and high integration of the CMOS image sensor can be achieved to thereby prevent deterioration of device characteristics.
    Type: Application
    Filed: May 21, 2003
    Publication date: April 15, 2004
    Inventors: In Gyun Jeon, Jinsu Han
  • Patent number: 6690076
    Abstract: A circuit having a plurality of circuit blocks formed on a semiconductor substrate is disclosed. The circuit blocks are stitched together by appropriately connecting input and output lines of the plurality of circuit blocks. The circuit also includes connecting circuits coupled to the plurality of circuit blocks. The connecting circuits provide low voltage drop across boundaries where the plurality of circuit blocks are stitched together.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: February 10, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Eric R. Fossum, Anders Andersson, David Schick
  • Publication number: 20040012063
    Abstract: A semiconductor light-receiving module includes a semiconductor light-receiving element and an incident light direction device. The semiconductor light-receiving element includes a substrate, at least a light absorbing layer and an upper cladding layer formed sequentially on the substrate, a light incident facet formed at least at one facet of the substrate and the light absorbing layer, and electrodes which output an electric signal generated by absorption of the light entering from the light incident facet in the light absorbing layer. The incident light direction device directs to irradiate the light obliquely to the light incident facet of the semiconductor light-receiving element, and to cause at least part of the light to irradiate the light absorbing layer at the light incident facet.
    Type: Application
    Filed: July 11, 2003
    Publication date: January 22, 2004
    Applicant: Anritsu Corporation
    Inventors: Kenji Kawano, Hiroaki Yoshidaya, Jun Hiraoka, Yuichi Sasaki, Eiji Kawazura, Satoshi Magsumoto
  • Publication number: 20040007753
    Abstract: There is disclosed a photoelectric conversion device which is manufactured by depositing numerous crystalline semiconductor particles of one conductivity type on a substrate having an electrode of one side to join the crystalline semiconductor particles to the substrate, interposing an insulator among the crystalline semiconductor particles, forming a semiconductor layer of the opposite conductivity type over the crystalline semiconductor particles, and connecting an electrode to the semiconductor layer of the opposite conductivity type, in which the insulator comprises a mixture or reaction product of polysiloxane and polycarbosilane. The insulator interposed among the crystalline semiconductor particles is free from defects such as cracking and peeling, so that a low cost photoelectric conversion device with high reliability can be provided.
    Type: Application
    Filed: April 25, 2003
    Publication date: January 15, 2004
    Applicant: KYOCERA CORPORATION
    Inventors: Yoji Seki, Takeshi Kyoda, Yoshio Miura, Hisao Arimune
  • Patent number: 6664592
    Abstract: A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom and side surface the gate insulator film is formed, and an upper portion protruding a surface of said semiconductor substrate, and source region and a drain region formed on a surface of the semiconductor substrate in such a way as to sandwich the gate electrode. A thickness of the upper portion of the gate electrode protruding the surface of the semiconductor substrate is equal to or greater than twice a thickness of the lower portion of the gate electrode buried in the groove.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: December 16, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Tomohiro Saito, Atsushi Yagishita, Katsuhiko Hieda, Toshihiko Iinuma