With Complementary (npn And Pnp) Bipolar Transistor Structures Patents (Class 257/511)
  • Patent number: 9966318
    Abstract: A substrate includes first and second semiconductor layers doped with opposite conductivity type in contact with each other at a PN junction to form a junction diode. At least one through silicon via structure, formed by a conductive region surrounded laterally by an insulating layer, extends completely through the first semiconductor layer and partially through the second semiconductor layer with a back end embedded in, and in physical and electrical contact with, the second semiconductor layer. A first electrical connection is made to the first through silicon via structure and a second electrical connection is made to the first semiconductor layer. A testing current is applied to and sensed at the first and second electrical connections in order to detect a defect in the at least one through silicon via structure.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 8, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 9755072
    Abstract: A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 5, 2017
    Assignee: MICROSEMI SoC CORPORATION
    Inventors: Fengliang Xue, Fethi Dhaoui, John L. McCollum
  • Patent number: 9437718
    Abstract: A method of forming a semiconductor structure includes forming a first seed layer, a second seed layer and an intrinsic base spaced apart from each other and with the intrinsic base located between the first seed layer and the second seed layer on an insulator layer. The method further includes forming an emitter on the first seed layer and on a first vertical surface of the intrinsic base by epitaxially growing the emitter from the first seed layer and the first vertical surface of the intrinsic base, and forming a collector on the second seed layer and on a second vertical surface of the intrinsic base by epitaxially growing the collector from the second seed layer and the second vertical surface of the intrinsic base.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: September 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Kevin K. Chan, Tak H. Ning, Jeng-Bang Yau, Joonah Yoon
  • Patent number: 9412667
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • Patent number: 9379066
    Abstract: A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: June 28, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Fabrice Marinet, Julien Mercier, Jimmy Fort, Alexandre Sarafianos
  • Patent number: 9337323
    Abstract: Device structures and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: May 10, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: James S. Dunn, Qizhi Liu
  • Patent number: 9230808
    Abstract: A method of fabricating a semiconductor device includes providing a substrate that is divided into a first region on which a pattern layer is formed and a second region on which a photo key is formed. A silicon layer is formed on the first region and second region of the substrate. The silicon layer is patterned to form a hole exposing a photo key portion of the second region on which the photo key is formed. A buried oxide layer is formed to fill the hole exposing the photo key portion. The silicon layer is patterned by using the photo key formed under the buried oxide layer to form a silicon pattern layer.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: January 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-woo Han, Jun-ho Yoon, Dong-chan Kim, Gyung-jin Min, Jae-hong Park, Yong-moon Jang
  • Patent number: 9202934
    Abstract: A method of forming a junction field effect transistor, the transistor comprising: a back gate; a channel; a top gate; a drain and a source in current flow with the channel; wherein the method comprises selecting a first channel dimension between the top gate and the back gate such that a significant current flow path in the channel occurs in a region of relatively low electric field strength.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: December 1, 2015
    Assignee: ANALOG DEVICES GLOBAL
    Inventor: Edward John Coyne
  • Patent number: 9176173
    Abstract: A method for detecting an imperfect mounting of an essentially rod-shaped metallic object in a metallic hollow shaft is provided. The imperfect mounting may lead to the formation of metallic particles. The rod-shaped object is mounted electrically insulated from the hollow shaft. The electrical resistance between the rod-shaped object and the hollow shaft is measured. An alert is issued when the electrical resistance is lower than a predefined level. A device includes a spin unit with a hollow drive shaft and a nozzle mounted inside the hollow shaft. The device is configured to use the inventive method.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: November 3, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Wolfgang Pfeiffer, Thomas Klein
  • Patent number: 8907452
    Abstract: A device for detecting a laser attack in an integrated circuit chip formed in the upper P-type portion of a semiconductor substrate incorporating an NPN bipolar transistor having an N-type buried layer, including a detector of the variations of the current flowing between the base of said NPN bipolar transistor and the substrate.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Jimmy Fort, Alexandre Sarafianos, Julien Mercier
  • Patent number: 8872222
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8853043
    Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wade J. Hodge, Alvin J. Joseph, Rajendran Krishnasamy, Qizhi Liu, Bradley A. Orner
  • Patent number: 8786024
    Abstract: A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: July 22, 2014
    Assignees: Yoshitaka Sugawara, Fuji Electric Co., Ltd.
    Inventor: Yoshitaka Sugawara
  • Patent number: 8785306
    Abstract: A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: July 22, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
  • Patent number: 8685799
    Abstract: An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 1, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Shyue Seng Tan, Eng Huat Toh, Elgin Quek
  • Patent number: 8618584
    Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: December 31, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Seiji Otake, Yasuhiro Takeda, Yuta Miyamoto
  • Patent number: 8598678
    Abstract: A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: December 3, 2013
    Assignee: Shanghai Hua Hong Nec Electronics Company, Limited
    Inventors: Wensheng Qian, Jun Hu, Donghua Liu
  • Patent number: 8569867
    Abstract: According to one embodiment, a semiconductor device that has a rectification element includes a semiconductor substrate, a first well region of a first conductivity type formed on the semiconductor substrate, a second well region of a second conductivity type formed on the semiconductor substrate, and a plurality of fins arranged over the first well region and the second well region at a first pitch in the same direction. In the semiconductor device, the rectification element includes a cathode region, an anode region, a well contact region, and a trigger region that are configured using fins. These regions are connected to each wiring portion to form a PNP-type bipolar transistor and an NPN-type bipolar transistor.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Inaba
  • Patent number: 8564096
    Abstract: Methods and apparatus according to various aspects of the present invention may operate in conjunction with a resistor formed of a lightly-doped P-type region formed in a portion of a lightly-doped N-type semiconductor well extending on a lightly-doped P-type semiconductor substrate, the well being laterally delimited by a P-type wall extending down to the substrate, the portion of the well being delimited, vertically, by a heavily-doped N-type area at the limit between the well and the substrate and, horizontally, by a heavily-doped N-type wall. A diode may be placed between a terminal of the resistor and the heavily-doped N-type wall, the cathode of the diode being connected to said terminal.
    Type: Grant
    Filed: July 4, 2008
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics SA
    Inventors: Serge Pontarollo, Dominique Berger
  • Patent number: 8455975
    Abstract: A parasitic PNP bipolar transistor, wherein a base region includes a first and a second region; the first region is formed in an active area, has a depth larger than shallow trench field oxides, and has its bottom laterally extended into the bottom of the shallow trench field oxides on both sides of an active area; the second region is formed in an upper part of the first region and has a higher doping concentration; an N-type and a P-type pseudo buried layer is respectively formed at the bottom of the shallow trench field oxides; a deep hole contact is formed on top of the N-type pseudo buried layer to pick up the base; the P-type pseudo buried layer forms a collector region separated from the active area by a lateral distance; an emitter region is formed by a P-type SiGe epitaxial layer formed on top of the active area.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: June 4, 2013
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Donghua Liu, Wensheng Qian
  • Patent number: 8330223
    Abstract: A bipolar transistor has a collector having a base layer provided thereon and a shallow trench isolation structure formed therein. A base poly layer is provided on the shallow trench isolation structure. The shallow trench isolation structure defines a step such that a surface of the collector projects from the shallow trench isolation structure adjacent the collector.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Klaus Schimpf, Manfred Schiekofer, Carl David Willis, Michael Waitschull, Wolfgang Ploss
  • Patent number: 8283730
    Abstract: A negative differential resistance (NDR) device is designed and a possible compact device implementation is presented. The NDR device includes a voltage blocker and a current blocker and exhibits high peak-to-valley current ratio (PVCR) as well as high switching speed. The corresponding process and design are completely compatible with contemporary Si CMOS technology and area efficient. A single-NDR element SRAM cell prototype with a compact size and high speed is also proposed as its application suitable for embedded memory.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: October 9, 2012
    Inventor: Shu-Lu Chen
  • Patent number: 8227832
    Abstract: The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 24, 2012
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Tzuyin Chiu, Zhengliang Zhou, Xiongbin Chen
  • Patent number: 8148774
    Abstract: To provide a semiconductor device in which an interval between first wells can be shortened by improving a separation breakdown voltage between the first wells and a method for manufacturing the same.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: April 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hidemitsu Mori, Kazuhiro Takimoto, Toshiyuki Shou, Kenji Sasaki, Yutaka Akiyama
  • Patent number: 8138570
    Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. An isolated junction field-effect transistor is formed in the isolated pocket.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: March 20, 2012
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • Patent number: 8129249
    Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: March 6, 2012
    Assignee: Infineon Technologies AG
    Inventors: Karlheinz Mueller, Klaus Roeschlau
  • Patent number: 8125051
    Abstract: A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: February 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Chuang, Kong-Beng Thei, Chiung-Han Yeh, Mong-Song Liang, Hou-Ju Li, Ming-Yuan Wu, Tzung-Chi Lee
  • Patent number: 8120189
    Abstract: A wiring structure having a wiring-terminal-connection adhesive that includes a curing agent capable of generating a free radical upon heating, a radically polymerizable substance and silicone particles.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: February 21, 2012
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Motohiro Arifuku, Itsuo Watanabe, Kouji Motomura, Kouji Kobayashi, Yasushi Gotoh, Tohru Fujinawa
  • Patent number: 8115256
    Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: February 14, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Haruki Yoneda, Hideaki Fujiwara
  • Patent number: 8044488
    Abstract: The invention is based upon a semiconductor device where a high voltage bipolar transistor is manufactured on the same wafer with a high-speed bipolar transistor, and has a characteristic that the high-speed bipolar transistor and the high voltage bipolar transistor are formed on each epitaxial collector layer having the same thickness and are provided with a buried collector region formed in the same process and having the same impurity profile, the buried collector region exists immediately under a base of the high-speed bipolar transistor, no buried collector region and no SIC region exist immediately under a base of the high voltage bipolar transistor and distance between a base region and a collector plug region of the high voltage bipolar transistor is equal to or is longer than the similar distance of the high-speed bipolar transistor.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: October 25, 2011
    Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Mitsuru Arai, Shinichiro Wada, Hideyuki Hosoe
  • Patent number: 8035168
    Abstract: Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: October 11, 2011
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Dipankar Pramanik, Xi-Wei Lin
  • Patent number: 8030731
    Abstract: An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: October 4, 2011
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • Patent number: 8021952
    Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: September 20, 2011
    Assignee: Infineon Technologies AG
    Inventors: Karlheinz Mueller, Klaus Roeschlau
  • Patent number: 8015538
    Abstract: The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The design structure further includes a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: September 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Douglas D Coolbaugh, Xuefeng Liu, Robert M. Rassel, David C. Sheridan, Steven H. Voldman
  • Patent number: 7960758
    Abstract: A bipolar transistor and a radio frequency amplifier circuit capable of preventing thermal runaway in the bipolar transistor without affecting the radio frequency amplifier circuit, which includes: a direct-current (DC) bias terminal to which a DC bias is supplied; a DC base electrode connected to the DC terminal; a radio frequency (RF) power terminal to which a radio frequency signal is supplied; an RF base electrode connected to the RF terminal; and a base layer connected to the DC base electrode and the RF base electrode.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: June 14, 2011
    Assignee: Panasonic Corporation
    Inventor: Masahiro Maeda
  • Patent number: 7923810
    Abstract: A semiconductor device may include a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate. An insulating isolation structure in the semiconductor substrate may surround sidewalls of the semiconductor region. An interlayer insulating layer may be on the semiconductor substrate, on the semiconductor region, and on the insulating isolation structure, and the interlayer insulating layer may have first and second spaced apart element holes exposing respective first and second portions of the semiconductor region. A first semiconductor pattern may be in the first element hole on the first exposed portion of the semiconductor region, and a second semiconductor pattern may be in the second element hole on the second exposed portion of the semiconductor region.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: April 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Won Ha, Sang-Yoon Kim
  • Patent number: 7911023
    Abstract: A semiconductor apparatus is disclosed. The semiconductor apparatus includes a semiconductor substrate that has a first surface and a second surface opposite to each other. The semiconductor apparatus further includes multiple double-sided electrode elements each having a pair of electrodes located respectively on the first and second surfaces of the semiconductor substrate. A current flows between the first and second electrode. Each double-sided electrode element has a PN column region located in the semiconductor substrate. The semiconductor apparatus further includes an insulation trench that surrounds each of multiple double-sided electrode elements, and that insulates and separates the multiple double-sided electrode elements from each other.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: March 22, 2011
    Assignee: Denso Corporation
    Inventors: Nozomu Akagi, Hitoshi Yamaguchi, Tetsuo Fujii
  • Patent number: 7898008
    Abstract: A bipolar device is integrated in an active layer, wherein delimitation trenches surround respective active areas housing bipolar transistors of complementary types. Each active area accommodates a buried layer; a well region extending on top of the buried layer; a top sinker region extending between the surface of the device and the well region; a buried collector region extending on top of the well region and laterally with respect to the top sinker region; a base region, extending on top of the buried collector region laterally with respect to the top sinker region; and an emitter region extending inside the base region. The homologous regions of the complementary transistors have a similar doping level, being obtained by ion-implantation of epitaxial layers wherein the concentration of dopant added during the growth is very low, possibly zero.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: March 1, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Piero Giorgio Fallica, Roberto Modica
  • Patent number: 7868414
    Abstract: A bipolar transistor is formed in an isolation structure comprising a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: January 11, 2011
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • Patent number: 7868387
    Abstract: A high-voltage, low-leakage, bidirectional electrostatic discharge (ESD, or other electrical overstress) protection device includes a doped well disposed between the terminal regions and the substrate. The device includes an embedded diode for conducting current in one direction, and a transistor feedback circuit for conducting current in the other direction. Variations in the dimensions and doping of the doped well, as well as external passive reference via resistor connections, allow the circuit designer to flexibly adjust the operating characteristics of the device, such as trigger voltage and turn-on speed, to suit the required mixed-signal operating conditions.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: January 11, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Jean-Jacques Hajjar, Todd Thomas
  • Patent number: 7863610
    Abstract: An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: January 4, 2011
    Assignees: Qimonda North America Corp., International Business Machines Corporation
    Inventors: Bipin Rajendran, Shoaib Hasan.Zaidi
  • Patent number: 7859062
    Abstract: Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: December 28, 2010
    Inventors: Kleanthes G. Koniaris, Robert Paul Masleid, James B. Burr
  • Patent number: 7842971
    Abstract: A silicon-controlled rectifier (SCR) device having a high holding voltage includes a PNP transistor and an NPN transistor, each transistor having both p-type and n-type dopant regions in their respective emitter areas. The device is particularly suited to high voltage applications, as the high holding voltage provides a device which is more resistant to latchup subsequent to an electrostatic discharge event compared to devices having a low holding voltage.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: November 30, 2010
    Assignees: Intersil Americas Inc., University of Central Florida Research Foundation, Inc.
    Inventors: Zhiwei Liu, Juin J. Liou, James E. Vinson
  • Patent number: 7816264
    Abstract: A wafer processing method having a step of reducing the thickness of a wafer in only a device forming area where semiconductor chips are formed by grinding and etching the back side of the wafer to thereby form a recess on the back side of the wafer. At the same time, an annular projection is formed around the recess to thereby ensure the rigidity of the wafer. Accordingly, handling in shifting the wafer from the back side recess forming step to a subsequent step of forming a back side rewiring layer can be performed safely and easily.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: October 19, 2010
    Assignee: Disco Corporation
    Inventors: Keiichi Kajiyama, Kazuhisa Arai
  • Patent number: 7790564
    Abstract: Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, Robert R. Robison, William R. Tonti
  • Patent number: 7772060
    Abstract: A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar transistor. Growing of the epitaxial layer includes growing a first sublayer of silicon 28a, a first sublayer of silicon-germanium 28b onto the first sublayer of silicon, a second sublayer of silicon 28c onto the first sublayer of silicon-germanium, and a second sublayer of silicon-germanium 28d onto the second sublayer of silicon. Furthermore, an integrated BiCMOS circuit is provided, which includes an epitaxial layer 28 as described above.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: August 10, 2010
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Reiner Jumpertz, Klaus Schimpf
  • Patent number: 7755161
    Abstract: A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: July 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Xuefeng Liu, Robert M. Rassel, Steven H. Voldman
  • Patent number: 7719081
    Abstract: In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: May 18, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
  • Patent number: 7704824
    Abstract: The present invention provides a highly doped semiconductor layer. More specifically, the present invention provides a semiconductor layer that includes at least two impurities. Each impurity is introduced at a level below its respective degradation concentration. In this manner, the two or more impurities provide an additive conductivity to the semiconductor layer at a level above the conductivity possible with any one of the impurities alone, due to the detrimental effects that would be created by increasing the concentration of any one impurity beyond its degradation concentration.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: April 27, 2010
    Assignee: RF Micro Devices, Inc.
    Inventors: Matthew L. Seaford, Arthur E. Geiss, Wayne Lewis, Larry W. Kapitan, Thomas J. Rogers
  • Patent number: RE41477
    Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: August 10, 2010
    Inventor: James D. Beasom