Abstract: An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.

Abstract: A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a sub-collector which is located in an upper surface of the bottom Si-containing layer. The sub-collector is in contact with a bottom surface of the buried insulating layer.

Abstract: An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS evaluation stage from the bipolar evaluation stage. The evaluation configuration can reliably detect very small read signals and allows a high integration density.

Abstract: A bipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening, an intrinsic base doped region formed within the substrate and in a bottom of the opening by implanting through the self-aligned base region, a spacer formed on the heavily doped polysilicon layer to define a self-aligned emitter region in the opening, and an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the intrinsic base doped region.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer, an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 &mgr;m deep and 5 to 6 &mgr;wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

Abstract: High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.

Abstract: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

Abstract: An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.

Abstract: An electronic circuit comprises a bipolar transistor that includes a conductive back electrode, an insulator layer over the conductive back electrode and a semiconductor layer of either an n-type or p-type material over the insulator layer. The semiconductor layer includes a doped region, used as the collector and a heavily doped region, bordering the doped region, used as a reachthrough between the insulator layer and the collector contact electrode. A majority-carrier accumulation layer is induced adjacent to the insulator in the doped region of the collector by the application of a bias voltage to the back electrode.

Abstract: To provide a light emitting device having a highly definite pixel portion. An anode (102) and a bank (104) orthogonal to the anode (102) are formed on an insulator (101). A portion of the bank (104) (controlling bank 104b) is made of a metal film. By applying a voltage thereto, an electric field is formed, and a track of an EL material that is charged with an electric charge can be controlled. Thus, it becomes possible to control a film deposition position of an EL layer with precision by utilizing the above method.

Abstract: An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.

Abstract: A transistor using mechanical stress to alter carrier mobility. Voids are formed in one or more of the source, drain, channel or gate regions to introduce tensile or compressive stress to improve short channel effects.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: The semiconductor device comprises a p type Si substrate 10; a SiGe buffer layer 12 formed on the p type Si substrate 10 and having element isolation grooves 16 formed in the surface, which define an active region 18; a SiGe regrown buffer layer 20 formed on the SiGe buffer layer 12; a strained Si channel layer 22 formed on the side walls of the element isolation grooves 16 and on the SiGe regrown buffer layer 20 in the active region; a SiN film 24 formed on the strained Si channel layer 22 on the side walls of the element isolation grooves 16; and an element isolation insulation film 26 buried in the element isolation grooves.

Abstract: The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device includes a first conductivity type semiconductor substrate and a surface silicon layer formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer.

Abstract: Isolation of a heterojunction bipolar transistor device in an integrated circuit is accomplished by forming the device within a trench in dielectric material overlying single crystal silicon. Precise control over the thickness of the initially-formed dielectric material ultimately determines the depth of the trench and hence the degree of isolation provided by the surrounding dielectric material. The shape and facility of etching of the trench may be determined through the use of etch-stop layers and unmasked photoresist regions of differing widths. Once the trench in the dielectric material is formed, the trench is filled with selectively and/or nonselectively grown epitaxial silicon. The process avoids complex and defect-prone deep trench masking, deep trench silicon etching, deep trench liner formation, and dielectric reflow steps associated with conventional processes.

Abstract: A transistor includes a base, a collector, and an emitter comprising a group III/VI semiconductor. Microcircuits having at least one metal oxide semiconductor (MOS) transistor and the previously described transistor are provided. Processes for manufacturing a transistor and a BiMOS microcircuit are also provided.

Abstract: Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An “emitter window” is masked directly over the polysilicon trench fill. Heavily doped single emitter poly is deposited and masked over the entire active region. The standard emitter drive then diffuses dopant through the emitter window into the undoped trench poly fill to provide an ohmic contact between the emitter poly and the trench poly fill. Contact to the emitter poly is made from overlying metal.

Abstract: A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the trench. A filler material fills the trench and forms a filler plug. The gate layers adjacent to the trench are then patterned and etched and the filler plug is removed to obtain gate stacks spaced apart by a distance of less than about 400 Angstroms.

Abstract: In a semiconductor device having a dual isolation structure, and a method of fabricating the same, an epitaxial layer is formed on the entire surface of the semiconductor device. A device region including the semiconductor device and the epitaxial layer is defined by a device isolation layer. The device isolation layer has a dual structure that includes a diffused isolation layer and a trench isolation layer. The diffused isolation layer is formed in the semiconductor substrate, and surrounds the base and the bottom sidewall of the device region, and the trench isolation layer surrounds the upper sidewall of the device region by vertically penetrating the epitaxial layer.

Abstract: A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.

Abstract: Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer. The power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.

Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.

Abstract: Disclosed herein is a communication module, comprising a semiconductor chip in which channels for allowing signal converting means to convert current signals inputted from input terminals to voltage signals and outputting the same from output terminals respectively are arranged in parallel in plural form, and wherein the semiconductor chip is comprised principally of a semiconductor substrate in which a second semiconductor layer is provided on a first semiconductor layer with an insulating layer interposed therebetween, each of the signal converting means is formed in a channel forming region of the second semiconductor layer, which is defined for each channel, and the input and output terminals are formed on the channel forming regions of the second semiconductor layer with the insulating layer interposed therebetween.

Abstract: An arrangement in a semiconductor component includes a highly doped layer on a substrate layer and is delimited by at least one trench extending from the surface of the component through the highly doped layer. A sub-layer between the substrate layer and the highly doped layer is doped with the same type of dopant as the buried collector, but to a lower concentration. The sub-layer causes a more even distribution of the potential lines in the substrate and in a sub-collector layer, thereby eliminating areas of dense potential lines and increasing the breakdown voltage of the component, (i.e., because the breakdown voltage is lower in areas with dense potential lines).

Abstract: A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semiconductor projection. Source and drain regions are formed in the side surfaces of the semiconductor projection on opposite sides of the gate electrode. First and second device isolation insulating films are formed on the semiconductor substrate on opposite sides of the semiconductor projection. A first impurity region is formed in the semiconductor substrate below the first device isolation insulating film. A second impurity region is formed in the semiconductor substrate below the second device isolation insulating film. The first and second impurity regions are in contact with each other in the semiconductor substrate below the semiconductor projection.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: An active feedback network for gain linearization is disclosed. High quality epitaxial layers of monocrystalline materials grown over monocrystalline substrates enables the formation of an active device on a monocrystalline compound semiconductor material and an active feedback device on a monocrystalline substrate. Alternatively, the active device may be formed on the monocrystalline substrate and the active feedback device may be formed on the monocrystalline compound semiconductor material. In either case, the differing characteristics of each semiconductor material is used to advantageously provide wideband operation with additional benefits in stability.

Abstract: Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

Abstract: In a semiconductor substrate (100), semiconductor regions (1, 2, 3, 5) belonging to the IGBT are formed in an IGBT region (20) and semiconductor regions (1, 4) belonging to the diode are formed in a diode region (21). The IGBT and the diode are connected in anti-parallel to each other. A trench (15) in which an insulator (16) is buried is formed between the IGBT region (20) and the diode region (21). The insulator (16) restricts the reverse recovery current which flows from the diode region (21) into the IGBT region (20). Thus, semiconductor regions of an IGBT and a diode connected in anti-parallel with each other are fabricated in a single semiconductor substrate and the chip size is reduced.

Abstract: An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.

Abstract: The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated.

Abstract: A trench is formed on a primary surface of a semiconductor substrate, and is filled with trench material to separate the surface region of the semiconductor substrate into plural active regions. At least a portion of the surface of the trench material adjoining the semiconductor substrate is depressed by a predetermined depth with reference to the primary surface of the semiconductor device. Thus, prevented is a decrease in a drain current of a semiconductor device having a trench isolation structure.

Abstract: A circuit-incorporating photosensitive device comprising: an SOI wafer including a first silicon substrate, a second silicon substrate, and an oxide film; a photodiode formed in a first region of the SOI wafer; and a signal processing circuit formed in a second region of the SOI wafer, wherein the photodiode includes a photosensitive layer formed of an SiGe layer.

Abstract: A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either by ion implantation prior to epitaxial growth of well regions, or by high energy ion implantation into the substrate prior to formation of the well and the heavily doped buried collector layer. Utilization of trench lateral isolation extending into the semiconductor material beyond the isolation layer permits blanket implant of the isolation layer, obviating the need for an additional masking step.

Abstract: A lateral bipolar transistor includes a semiconductor layer overlying an electrically insulating material and an insulating layer overlying a central portion of the semiconductor layer. A contact hole resides in the insulating layer and a conductive material overlies the insulating layer and makes electrical contact with the semiconductor layer through the contact hole, thereby forming a base contact. The semiconductor layer has a first conductivity type in a central region which substantially underlies the conductive material, and has a second conductivity type in regions adjacent the central region. The first region forms a base region and the adjacent regions form a collector region and an emitter region, respectively. A method of forming a lateral bipolar transistor device is also disclosed. The method includes forming a semiconductor layer over an insulating material and forming an insulating layer over the semiconductor material.

Abstract: An object of the present invention is to provide a lateral bipolar transistor having a high current driving capacity and a high current amplification factor as well as a high cut-off frequency. A device area 13 surrounded by an isolating insulation layer is formed on the surface of a semiconductor substrate 11. A base area 15 is formed in the device area 13 to a specified depth from the surface of the semiconductor substrate 11. A core insulation layer 25 is formed in the base area 15 with a depth shallower than the base area 15 from the surface of the semiconductor substrate 11. Around the core insulation layer 25, there are formed emitter areas 26. A collector area 17 is formed at a specified distance from the emitter area 26. Since the bottom area of the emitter area 26 is reduced by being provided with the core insulation layer 25 without reducing the side area of the emitter area 26, the current driving capacity and the current amplification factor of the transistor are thus improved.

Abstract: An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.

Abstract: The invention relates to semiconductor devices having a bipolar transistor to form an isolation area within a base electrode contact area to ensure stable contact of the base electrode. The bipolar transistor formed in the transistor area is in the form of an island and is rectangular when view from above. The isolation area is formed of a dielectric material around the transistor area, and the base area is formed around the emitter area which forms the central area of the transistor area. A contact groove is formed at the inner interface of the isolation groove which faces the outer surface of the transistor area, and a part of the base electrode is buried in the contact groove and faces at least one of the upper surface of the transistor area and an inner surface of the contact groove.

Abstract: A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Abstract: A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either by ion implantation prior to epitaxial growth of well regions, or by high energy ion implantation into the substrate prior to formation of the well and the heavily doped buried collector layer. Utilization of trench lateral isolation extending into the semiconductor material beyond the isolation layer permits blanket implant of the isolation layer, obviating the need for an additional masking step.

Abstract: The semiconductor device and method of manufacturing the same according to the present invention has an object of reducing hem-pulling at a side wall of an isolation trench caused at an open space of a device isolation region having a well boundary at its bottom portion thereby to prevent structurally occurrence of punch-through. In an insulator filled device isolation method, an isolation trench for device isolation is formed by dry etching. If a second isolation trench intersects an intermediate portion of a first isolation like a T-shape, one side of the first isolation trench has an open space. In this case, the inclination angle of the side wall of the first isolation trench, opposed to the open space, is loosened and the side wall forms a shape whose hem is pulled out on the bottom portion. In this case if a well boundary exists along the lengthwise direction at the bottom of the first isolation trench, the structure tends to cause punch-through easily.

Abstract: In an NPN transistor of this invention having a trench isolation structure, for example, an N.sup.+ -type buried layer and an N.sup.- -type epitaxial layer are stacked on an element forming region of a P.sup.+ -type substrate, and a trench having polysilicon filled therein is formed in a portion adjacent to the element forming region. Further, a field oxide film is formed to extend from the trench having polysilicon filled therein over to the adjacent element isolation region without extending into the element forming region. Thus, a distance from the front end portion of the field oxide film on the element forming region side to the trench is reduced to reduce the element area. Therefore, the parasitic capacitance can be reduced and the power consumption of a circuit can be reduced.

Abstract: A bipolar transistor formed on a SOI substrate has a buried collector layer underlying an emitter region and a collector contact region for connection thereof, both of which are made of a doped polysilicon film deposited in a removed portion of an oxide film etched by wet etching and a collector contact groove, respectively. By reducing the area of the buried collector layer, the bipolar transistor has excellent frequency characteristics in a high-frequency range.

Abstract: A semiconductor device having the base region surrounded by at least two continuous slots. The collector region is surrounded by at least one continuous slot formed as a continuation of one of the at least two continuous slots surrounding the base region. The portions of the slots that are over the buried layer extends beyond the surface of the buried layer and the portions of the slots not over the buried layer extends beyond the interface between the epitaxial layer and the substrate. The slots are filled with either polysilicon or tungsten. The base region terminates on the surface of the innermost slot surrounding the base region. The boundary of the base region terminates substantially perpendicular to the surface of the surrounding slot.

Abstract: A sensor element provided with a silicon substrate having a semiconductor circuit, a sensing-element portion formed on the silicon substrate and connected to the semiconductor circuit, and a cavity portion formed by removing a silicon substrate portion below the sensing-element portion, in which a removal resistance region having resistance against substrate removal is provided in the silicon substrate between the semiconductor circuit and the cavity portion.

Abstract: A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed at predetermined locations of the semiconductor substrate and oxide films using organic silicon source as material are buried in the grooves as buried oxide films. The present invention is characterized in that the buried oxide films are annealed at a predetermined temperature within the range of 1100 to 1350.degree. C. before or after planarization of the semiconductor substrate such that ring structures of more than 5-fold ring and ring structures of less than 4-fold ring are formed at predetermined rates in the buried oxide films. The above annealing allows stress of the oxide film buried in the grooves to be relaxed. Hence, the generation of dislocation is suppressed.

Abstract: A semiconductor device and a method of making the semiconductor device, the semiconductor device having a base region wherein the base region is surrounded by a slot. The sideways depletion region of the collector-base junction terminates on the slot thus reducing the sideways spreading of the collector-base depletion region.