Abstract: The invention provides a trench isolation structure comprising a semiconductor region, a first insulation film formed on a top surface of the semiconductor region, a trench groove extending vertically from the first insulation film into the semiconductor region so that a bottom of the trench groove lies below an interface between the first insulation film and the semiconductor region, and an inter-layer insulator being formed which resides not only on the first insulation film but also within the trench groove so that the inter-layer insulator fills up the trench groove.The present invention still further provides a method for forming a trench isolation in a semiconductor region. The method comprises the following steps. A first insulation film is formed on a top surface of a semiconductor region.

Abstract: Narrow and wide, planar field isolation region (72, 74, 152, 172, 182) is formed by forming trenches (52, 54) within a substrate (10). For wide, planar field isolation regions (72, 152, 172, 182), the trenches (52) define at least one mesa (76, 150, 170, 180) within the field isolation region (72, 152, 172, 182). The trenches (52, 54) are filled with a material (62) that is polished or etched to form the planar field isolation region (72, 74, 152, 172, 182) where the wide, planar field isolation regions (72, 152, 172, 182) include the mesa(s) (76, 150, 170, 180). Etching can be used or by polishing with minimal, if any, dishing occurs because the widths of the trenches (52, 54) are kept relatively narrow (usually no more than five microns wide). Mesas (180) within a wide, planar field isolation region (182) can form linguistic characters to better identify the part number or mask set of the device.

Abstract: A semiconductor device with a base region that terminates on the surface of a slot that surrounds the base region. The base region terminates substantially perpendicular to the surface of the slot. The collector-base junction has substantially no cylindrical or spherical curvature.

Abstract: A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors.

Abstract: A depression having a depth not exceeding 0.1 .mu.m is formed on the surface of an epitaxial layer. An internal base region is formed just below the depression. An external base region is formed outside the depression. The depression having the above depth can suppress electric field at the end of the internal base in the neighborhood of the junction between the internal base region and the external base region.

Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

Abstract: A semiconductor device includes a groove formed in a surface of a first semiconductor substrate of one conductivity type in order to partition and isolate first and second device regions. A first insulating film on the first semiconductor substrate of the first device region also contacts the groove. A second insulating film covers an inner wall of the groove. The first insulating film is thicker than the second film in order to increase the breakdown voltage and facilitate carrying a higher current. This thickness relationship also aids manufacturing.

Abstract: A trench isolation structure includes a semiconductor region, a first insulation film on a top surface of the semiconductor region, a trench groove extending vertically from the first insulation film into the semiconductor region so that a bottom of the trench groove lies below an interface between the first insulation film and the semiconductor region, and an inter-layer insulator on the first insulation film and within the trench groove so that the inter-layer insulator fills up the trench groove.

Abstract: A bipolar variable resistance device suitable for integrated circuit applications includes a silicon substrate, and a resistive layer covering the silicon substrate, the resistive layer being doped with impurities of a first polarity and of a second polarity. A dielectric layer covers the resistive layer. A conductive layer covers the dielectric layer. The device is used to change the resistance of the resistive layer by varying a control voltage applied to the conductive layer.

Abstract: A buried collector layer is formed on a semiconductor substrate. An epitaxial layer is formed on the burled collector layer. A plurality of element separating trenches of roughly the same depth and filled with an insulating material are formed in the epitaxial layer. When these trenches are formed deep enough to penetrate the buried collector layer to the semiconductor substrate, an impurity region of conductivity the same as that of the buried collector layer is formed at a predetermined position of the semiconductor substrate and adjoining to at least one bottom portion of a plurality of the trenches. Further, when a separation layer is formed on the semiconductor substrate and adjoining to the buried collector layer to separate the semiconductor device from another adjacent semiconductor device, at least one of a plurality of trenches is formed on a boundary surface between the buried collector layer and the separation layer.

Abstract: In IGBTs or, respectively, MOSFETs a parasitic junction-FET effect can be nearly avoided on the basis of an insulation layer introduced between the two base zones and into which an electrode is additionally embedded. The on-resistance is lowered as a result thereof. In an advantageous development, a potential activation of the parasitic bipolar structure (latch-up) can also be prevented.

Abstract: A semiconductor BiCMOS device and method of manufacturing suitable for attaining high packing density and thereby speeding up a switching operation, wherein the device is formed to have one of a source region or a drain region of an MOS transistor be immediately adjacent a base region of a bipolar transistor so as to be electrically connected. In this manner, an electrical terminal is eliminated, thereby permitting a higher packing density.

Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

Abstract: A bipolar transistor has a first semiconductor region of an n-type epitaxial layer surrounded by a first insulating film, a second insulating film of silicon oxide having an opening, a second semiconductor region as a base link region of a p-type formed in the opening and having a high impurity concentration and a thickness substantially the same as that of the second insulating film, a third semiconductor region as an intrinsic base of a p-type having a thickness thinner than that of the second insulating film, a sidewall insulating film covering the third semiconductor region, and a fourth semiconductor of a p-type formed on the third semiconductor region and surrounded by the side-wall insulating film. The reduction in the thickness of the intrinsic base is achieved without reducing the thickness of the base link region and thus it is possible to realize a bipolar transistor in which a cut-off frequency is high and yet the base resistance is low.

Abstract: A semiconductor integrated circuit device includes an element separating first and second grooves formed to surround active regions to be formed with a semiconductor element. In addition a third groove is formed to surround at least a portion of the first groove, when viewed from a plane view. In the semiconductor integrated circuit device, the active regions and an element separating region of a silicon layer are insulated from each other by the separating grooves extending from the main surface of the silicon layer to an underlying insulating layer, and are fed with a common fixed potential.

Abstract: The plurality of functioning circuits are formed in a plurality of P-type well regions formed on a remaining part of said low concentration N-type layer, by isolating from each other. According to the present invention, the photoelectric current from the PIN photodiode can be processed in the functioning circuits formed in the P-type well regions by isolating from each other, so that the interference between the functioning circuits can be prevented and also the shift of the current flowing in each functioning circuit due to the impossibility of the high concentration N-type semiconductor layer to be grounded can be prevented. Therefore, the malfunction of the integrated PIN photodiode sensor can be prevented, and the PIN photodiode sensor can operate with high speed because the distributed resistance between the functioning circuits is decreased.

Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

Abstract: A semiconductor device in which a bipolar transistor is provided, such as a BiCMOS, and a production process thereof. The device has collector region of a first conductivity type; an intrinsic base region of a second conductivity type provided on the collector region; a graft base provided on the periphery of this intrinsic base region; and an emitter region of the first conductivity type provided by self-alignment with respect to the intrinsic base. A base electrode is provided in the upper portion where the graft base is scheduled to be formed. A trench is provided by self-alignment along the end portion on the outer circumference side of this base electrode. The graft base is provided in contact with the inner circumference of this trench.

Abstract: A semiconductor chip having an on-chip ground plane comprising a low resistivity semiconductor region in a plurality of non-device regions of the chip and reach-through regions electrically connected to the low resistivity semiconductor region. One or more front-side contacts are used to electrically connect the reach-through regions and the low resistivity semiconductor region to a ground potential to electrically ground the on-chip ground plane.

Abstract: There is provided a semiconductor integrated circuit device having bipolar transistors each composed of an emitter region, base region, and collector region arranged vertically on a semiconductor substrate, said collector region having a plane figure, with the square corners thereof cut off. To be concrete, the buried collector region having a high concentration of impurity has its square corners cut off and the base region formed on the major surface of the epitaxial layer formed on said buried collector region has also its square corners cut off. The bipolar transistor having such a plane figure has a reduced parasitic capacity and an increased operating speed. A manufacturing method is also provided capable of producing a highly reliable groove isolation structure with a low dielectric constant.

Abstract: Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices are obtained by forming an amorphous silicon carbide termination region in a monocrystalline silicon carbide substrate, at a face thereof, adjacent and surrounding a silicon carbide device. The amorphous termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize the substrate face. The device contact or contacts act as an implantation mask to provide a self-aligned termination region for the device. The terminated devices may exhibit voltage breakdown resistance which approaches the ideal value for silicon carbide.

Abstract: A power transistor has a plurality of small emitter-base complexes arranged in an array. These complexes are electrically insulated from the surrounding semiconductor material by separating regions such that for the current supply to the collectors, a joint subcollector layer and thereupon a collector metallization exist outside of the emitter-base complexes and reaching up to the separating regions. The individual emitter-base complexes are electrically connected with each other via strip-shaped base supply lines and strip-shaped emitter supply lines, and also with a base contact surface and an emitter contact surface.

Abstract: A device-isolating trench having a taper at its upper portion is formed in a silicon semiconductor substrate. Then, a silicon oxide film is formed on the inner wall of the trench and the surface of the semiconductor substrate near the trench by an oxidizing method, and polycrystalline silicon is buried in the trench.

Abstract: This invention relates to a monolithic IC having a PIN photodiode and an n-p-n bipolar transistor formed on a single semiconductor (silicon) substrate. In fabricating such IC, it is important to electrically isolate the photodiode and the bipolar transistor. In addition it is necessary to make the surface of the substrate flat. According to this invention, the inter-device isolation between the above-described two devices is attained by forming two epitaxial layers on the silicon substrate, forming trenches in the layers, and burying silicon dioxide in the trenches. In the monolithic IC according to this invention wiring capacity is small, and high-speed performance becomes possible. A p-type buried-layer is formed below the bipolar transistor to thereby prevent punch through between the bipolar transistor and other devices. Also this invention provides the process for fabricating a planar type bipolar transistor suitable to fabricate the monolithic IC and also provides a PIN photodiode of a new structure.

Abstract: A planar heterobipolar transistor and its methods for manufacture provide that the transistor has the base-emitter region separated from the collector terminal by a collector parting trench and the parting trench structure may be used to separate the transistor from adjoining function components.

Abstract: A heterojunction bipolar transistor comprises n.sup.+ -type GaAs collector contact region, an n-type GaAs collector region, a p.sup.+ -type GaAs base region, an n-type AlGaAs emitter region, and an n.sup.+ -type InGaAs emitter contact region, all of which are formed on a semiinsulative GaAs substrate. A heterojunction is formed by the base region and the emitter region. The emitter region is formed in mesa shape by dry etching. Around this mesa, B.sup.+ ion-implanted high-resistance region is formed. The base-emitter Junction is isolated from the ion-implanted region. The heterojunction bipolar transistor therefore has little on-voltage changes.

Abstract: P-channel MOSFETs in a fully CMOS-type memory cell are formed by a thin film (polysilicon), and portions that serve as source and drain regions of the thin-film p-channel MOSFETs are thickened by a conductor layer having a small resistance value. Further, the thin film and the conductor layer having a small resistance value are formed in common with a base lead-out layer of an npn bipolar transistor constituting a peripheral circuit.

Abstract: The thickness of a DI island structure is reduced and the performance of bipolar and JFET structures enhanced by shaping the bottom of the DI island during anisotropic etching to define isolated islands, so that the resulting structure contains one or more projections whose separation from the topside diffusion predefines operational characteristics of the device. If the projection is directly beneath the bottom of a gate diffusion, pinch-off voltage of a JFET device is reduced without substantially affecting channel resistance. When the projection is positioned so that its inclined surface extends alongside the curvilinear PN junction formed between the gate diffusion and the island, channel thickness and sensitivity of channel thickness to viriations in island thickness are reduced.

Abstract: A semiconductor integrated circuit device according to the present invention includes a semiconductor layer of a first conductivity type having a high concentration of impurity atoms which layer is formed in or on predetermined locations of a semiconductor substrate with the first conductivity type which locations requires a resistance to alpha rays. The device of the present invention can decrease the amount of the electron collection to a semiconductor layer of a second conductivity type having a high concentration of impurity atoms which layer is separated from the semiconductor layer of the first conductivity type having a high concentration of impurity atoms. Therefore, the semiconductor integrated circuit device of the present invention can have enhanced resistance to alpha rays without capacitances being increased and maintain a fast speed of circuit operation.

Abstract: An image reversal process for self-aligned implants in which a mask opening and plug in the opening are used to enable one implant in the mask opening, another self-aligned implant in the region surrounding the opening, and a self-aligned electrode to be formed in the opening.

Abstract: Semiconductor devices having a reduced parasitic capacitance while having a maximum acceptable current similar to those of prior devices, and a method of manufacturing thereof are disclosed. The inventive device has a hole at the bottom of which an insulating film separated from the hole walls is located, a semiconductor film being present in the hole, which is connected to the semiconductor substrate adjacent to the insulating film and a conductor film constituting a portion of the hole wall, and extends onto the insulating film so as to cover at least part of the film.

Abstract: A method for dielectrically isolating a semiconductor integrated circuit is provided. Each integrated circuit is substantially surrounded by silicon oxide sidewalls which have been appropriately doped to be of an opposite conductivity type as the surrounding substrate. The doped silicon oxide sidewalls are formed prior to the growth of epitaxial silicon within the sidewalls. Upon deposition of the epitaxial silicon the dopant within the oxide sidewalls diffuses into the adjacent epitaxial silicon, thereby resulting in a heavily doped, low resistivity region of epitaxial silicon adjacent to and along the entire length of the oxide sidewall. This heavily doped region results in the substantial elimination of charge-depleting parasitic currents along the sidewalls during use of the integrated circuit. In addition, the heavily doped, low resistivity epitaxial region provides an electrically conductive contact to a buried layer within an integrated circuit having such a buried layer.

Abstract: A method of forming self-aligned transistors wherein both bipolar and field effect transistors are formed in the same Integrated Circuit simultaneously is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be typically polycrystalline silicon. An insulator layer is formed upon the surface of the conductive layer. Openings with substantially vertical sidewalls are formed through the conductive layer to the semiconductor substrate in the locations of the first element, the emitter for the bipolar and gate for the MOSFET, of the transistors to be formed. The structure is heated to form the heavily doped portions of the second element of said transistors of the one conductivity type by outdiffusing from the conductive layer.

Abstract: There is disclosed herein a transistor having a sidewall base contact. The base region of the transistor is in a column of selectively grown epitaxial silicon isolated from adjacent structures in a field of oxide. The sidewall base contact is a layer of doped polysilicon which is embedded in the insulating material surrounding the column of epitaxial silicon. The collector contact is formed of another column of selectively grown epitaxial silicon grown over and in electrical contact with a buried layer underlying the first column of epitaxial silicon. The emitter region is implanted into the top of column doped as the base region. In one embodiment, the base contact is a buried polysilicon layer. In another embodiment, the base contact is epitaxial silicon which is grown over oxide by uncontrolled growth following controlled selective growth.