Abstract: The present invention is directed to a semiconductor interconnect structure comprised of a promoter layer defining openings and a metal layer having a portion elevated above the substrate assembly and a portion that fills the openings. The metal layer is in electrical contact with the substrate assembly through the portion of the metal layer that fills the openings. The portion of the metal layer that fills the openings supports the elevated portion of the metal layer. A method of fabricating a semiconductor interconnect structure is also provided. A resist layer is patterned on a substrate assembly to define openings. A metal layer is deposited on the resist layer and into the openings, and the resist layer is removed to form a gap between the metal layer and the underlying substrate assembly.

Abstract: An apparatus for fabricating encapsulated micro-channels in a substrate is described. The apparatus includes the formation of a thin film layer over an area of a substrate. Following the formation of the thin layer, a periodic array of access windows are formed within the thin film layer along dimensions of one or more desired micro-channels. Following formation of the access windows, the one or more micro-channels are formed within an underlying layer of the substrate. Finally, the one or more micro-channels are encapsulated, thereby closing the one or more access windows along the dimensions of the desired micro-channels. Accordingly, the apparatus is suitable in one context for rapid prototyping of micro-electromechanical systems in the areas of, for example, RF micro-systems, fluidic micro-systems and bio-fluidic applications. In addition, the apparatus enables the rapid prototyping of integrated circuits.

Abstract: The present invention relates to a fabrication process relating to a fabrication process for manufacture of micro-electromechanical (MEM) devices such as cantilever supported beams. This fabrication process requires only two lithographic masking steps and offers moveable electromechanical devices with high electrical isolation. A preferred embodiment of the process uses electrically insulating glass substrate as the carrier substrate and single crystal silicon as the MEM component material. The process further includes deposition of an optional layer of insulating material such as silicon dioxide on top of a layer of doped silicon grown on a silicon substrate. The silicon dioxide is epoxy bonded to the glass substrate to create a silicon-silicon dioxide-epoxy-glass structure. The silicon is patterned using anisotropic plasma dry etching techniques.

Abstract: A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an external cover attached to the substrate and at least partially enclosing the first and second device features and the conductive link. The external cover can have a composition substantially identical to the composition of the conductive links and the external cover can be formed simultaneously with formation of the conductive link to reduce the number of process steps required to form the microelectronic device package. A sacrificial material can temporarily support the conductive link during manufacture and can subsequently be removed to suspend at least a portion of the conductive link between two points.

Abstract: An improved temperature compensated quartz oscillator, which includes a package for mounting compensating circuitry over a cavity instead of on a planar layer, reduces the chip failure rate by preventing undesired contact of the compensation circuitry with the material forming the layer upon which the circuitry is mounted.

Abstract: A semiconductor device (2) includes a semiconductor substrate (12) having a surface (13) formed with a first recessed region (20). A first dielectric material (60) is deposited in the first recessed region and formed with a second recessed region (76), and a second dielectric material (100) is grown over the first dielectric material to seal the second recessed region.

Abstract: A semiconductor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain.

Abstract: An inter-level insulator structure is provided having an effective insulator dielectric constant approaching 1. An embodiment of the inter-level insulator comprises a first metal layer comprising a first plurality of metal lines; a second metal layer comprising a second plurality of metal lines, and at least one via connected to the first metal layer; and an air gap interposed between the first metal layer and the second metal layer. In one embodiment, the air gap is also present between metal lines on either metal layer, such that air gaps act as intra-level as well as inter-level insulators. A method is also provided to deposit and pattern a sacrificial polymer, and form metal layers. The sacrificial polymer is capable of being decomposed to become air gaps during annealing.

Abstract: A first insulating layer (12) overlying semiconductor substrate (10) has a plurality of conductive paths (14, 16) disposed thereon. Each of the plurality of conductive paths has at least a major portion thereof overlied with a second insulating layer (20). A third insulating layer (26), having air gap ports (28) formed therein, overlies adjacent conductive paths and extends from one to another such that an air gap (34) is formed. A passivation layer (30) overlies third insulating layer and seals the plurality of air gaps ports to form an insulation structure (40) for a semiconductor integrated circuit, and method thereof.

Abstract: A power transistor cell includes an air bridge and a plurality of individual transistors. Each of the plurality of individual transistors has at least one separate connection contact. Each of the at least one separate connection contact of the plurality of individual transistors is thermally conductively connected to one another through the air bridge forming air bridge connections, which define a contact plane. A surface of the contact plane that contains each connection path between two of the air bridge connections defines a convex region. The air bridge is formed to have, in the contact plane, dimensions that exceed a smallest convex region containing all of the air bridge connections in all directions of the air bridge. Each of the plurality of power transistor cells can be respectively thermally conductively connected to one another through the air bridge to form a block of power transistor cells.

Abstract: A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon spheres define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are rigid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperatures up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are “T-topped” (i.e., viewed cross-sectionally). Dielectric fill is deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off an internal void.

Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat

Abstract: A lower carbon film as a provisional film, a lower SiO2 film and an upper carbon film are formed, and then trenches having a wiring pattern are formed in the upper carbon film. Next, contact holes are formed through the lower carbon film and the lower SiO2 film. Then, wires and plugs are formed by filling in the trenches and contact holes with a barrier metal film and a Cu alloy film. After these process steps are repeatedly performed several times, a dummy opening is formed to extend downward through the uppermost SiO2 film. Thereafter, the carbon films are removed by performing ashing with oxygen introduced through the dummy opening. As a result, gas layers are formed to surround the wires and plugs. In this manner, a highly reliable gas-dielectric interconnect structure can be obtained by performing simple process steps.

Abstract: A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.

Abstract: An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed intentionally therein is provided.

Abstract: A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by the method. The method includes formation and patterning of a mask on a silicon substrate followed by anisotropic etching of the silicon to provide a dense array of deep holes. Isotropic etching may be used to form a cavity beneath the dense array of holes and coupling to bottoms of the holes. Sides of the holes are then thermally oxidized. A conventional dielectric is then formed, sealing tops of the holes. The conventional dielectric is optionally densified. Conventional chemical-mechanical polishing then planarizes the dielectric and further conventional processing may be carried out on the wafer to form active circuitry together with passive components such as high Q inductors.

Abstract: A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improves speed and efficiency of the integrated circuit. However, current air bridges must be kept short because typical aluminum conductors sag too much. Accordingly, one embodiment of the invention forms air-bridge conductors from an aluminum-beryllium alloy, which enhances stiffness and ultimately provides a 40-percent improvement in air-bridge lengths.

Abstract: An improved microelectronic structure is disclosed. The improved structure includes an air-gap region formed by removing an insulating material through an aperture residing in a mask.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. Trench digging is time consuming and costly. Accordingly, the invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer.

Abstract: Structures and methods are disclosed for insulating a polysilicon gate adjacent to an electrically active region with a silicon base layer. A layer of silicon nitride having a thickness in a range from about 100 Å to about 150 Å is conformally deposited over the polysilicon gate. A layer of silicon dioxide is formed over the layer of silicon nitride on the polysilicon gate. The layer of silicon dioxide is subjected to a spacer etch to form spacers upon the layer of silicon nitride and on lateral sidewalls of the polysilicon gate. A portion of the layer of silicon nitride situated between the polysilicon gate and the spacer is removed by an etching process that is selective to silicon dioxide and to polysilicon. The etch forms a recess defined between the polysilicon gate and each respective spacer. A cover layer is formed to close an opening to the recess so as to enclose a void therein.

Abstract: Disclosed is a structure and process for incorporating air or other gas as a permanent dielectric medium in a multilevel chip by providing CVD diamond as a semi-sacrificial interlevel and intralevel dielectric material. The semi-sacrificial dielectric is subsequently at least partially removed in an isotropic oxygen etch. A variation of the disclosure includes providing a final, permanent CVD diamond encapsulant to contain the gaseous dielectric medium within the chip.

Abstract: Airbridge structures and processes for making air bridge structures and integrated circuits are disclosed. One airbridge structure has metal conductors 24 encased in a sheath of dielectric material 249. The conductors extend across a cavity 244 and a semiconductor substrate 238. In one embodiment, the conductors traversing the cavity 244 are supported by posts 248 that extend from the substrate. In another embodiment, oxide posts 258 extend from the substrate to support the conductors. In another embodiment, trenches 101 are made in a device substrate 110 bonded to a handle substrate 100. The trenches are filled with a dielectric and a conductor pattern is formed over the filled trenches. The substrate material between the conductors is then removed to leave a pattern of posts 116, 114, 112 that included dielectrically encased conductors 106. In another bonded wafer embodiment, conductors 204 are encased in a dielectric above a sacrificial device region.

Abstract: An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed intentionally therein is provided.

Abstract: A method for forming a multilevel interconnect structure for an integrated circuit is disclosed. In an exemplary embodiment of the invention, the method includes forming a starting structure upon a substrate, the starting structure having a number of metallic conducting lines contained therein. A disk is bonded to the top of said starting structure, the disk including a plurality of mesh openings contained therein. The mesh openings are then filled with an insulative material, thereby forming a cap upon the startig structure, wherein the cap may structurally support additional interconnect layers subsequently formed thereatop.

Abstract: A method for forming a semiconductor device having air regions, the method comprises providing a base, forming a pattern of metal leads, depositing a layer of oxide over the metal leads, forming a layer of nitride over said layer of oxide, opening and etching a trench down to the base layer of material, and depositing and planarizing a dielectric layer. An alternate approach teaches the deposition of a layer of SOG over the layer of oxide that has been deposited over the metal leads, planarizing this layer of SOG down to the top of the metal leads, depositing a layer of PECVD oxide, patterning and etching this layer of PECVD oxide thereby creating openings that are in between the metal leads. The SOG that is between the metal leads can be removed thereby creating air gaps as the Intra-level dielectric for the metal leads.

Abstract: An integrated device comprises an epitaxial layer forming a first and a second region separated by at least one air gap. The first region forms, for example, a suspended mass of an accelerometer. A bridge element extends on the air gap and has a suspended electrical connection line electrically connecting the first and the second region and a protective structure of etch-resistant material, which surrounds the electrical connection line on all sides. The protective structure is formed by a lower portion of silicon nitride and an upper portion of silicon carbide, the silicon carbide surrounding the electrical connection line at the upper and lateral sides.

Abstract: A method for forming a semiconductor device having air regions, the method comprises providing a base, forming a pattern of metal leads, depositing a layer of oxide over the metal leads, forming a layer of nitride over said layer of oxide, opening and etching a trench down to the base layer of material, and depositing and planarizing a dielectric layer. An alternate approach teaches the deposition of a layer of SOG over the layer of oxide that has been deposited over the metal leads, planarizing this layer of SOG down to the top of the metal leads, depositing a layer of PECVD oxide, patterning and etching this layer of PECVD oxide thereby creating openings that are in between the metal leads. The SOG that is between the metal leads can be removed thereby creating air gaps as the intra-level dielectric for the metal leads.

Abstract: A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon spheres define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are rigid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperatures up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are “T-topped” (i.e., viewed cross-sectionally). Dielectric fill is deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off an internal void.

Abstract: An integrated circuit device includes electrical conductors providing electrical communication between a substrate and a silicon chip. The silicon chip has first electronics and second electronics. The second electronics are for operating at higher frequencies than the first electronics. A first portion of electrical conductors are in communication with the first electronics and a second portion of electrical conductors are in communication with the second electronics. A first medium is positioned adjacent to the first portion of electrical conductors and a second medium is positioned adjacent to the second portion of electrical conductors. The second medium is different from the solid first medium.

Abstract: A semiconductor chip is mounted over a flexible base plate. The base plate has an array of bubbles. Each bubble is coated with a metal tip, which is coupled by printed and leads bonds to the bonding pads of the chip. The metal tips are for making contacts to a printed circuit board when the package is mounted to a printed circuit board.

Abstract: Air gap insulation regions are formed selectively within high parasitic capacitance regions in which conductive lines are closely proximate and generates an intolerable amount of parasitic capacitance. The selective formation of air gap insulation regions improves circuit performance by reducing the parasitic capacitance and device reliability by reducing the stress fracture problem of conventional air gap insulation schemes.

Abstract: The integrated inductor comprises a coil of metal which is formed in the second metal level. The coil is supported by a bracket extending above spaced from a semiconductor material body by an air gap obtained by removing a sacrificial region formed in the first metal level. The bracket is carried by the semiconductor material body through support regions which are arranged peripherally on the bracket and are separated from one another by through apertures which are connected to the air gap. A thick oxide region extends above the semiconductor material body, below the air gap, to reduce the capacitive coupling between the inductor and the semiconductor material body. The inductor thus has a high quality factor, and is produced by a process compatible with present microelectronics processes.

Abstract: A multi-layer semiconductor circuit comprising a plurality of conductive lines having air as a dielectric between the sides of the conductive lines in a first layer and having a structurally supportive non-metal cap layer at least partially covering the top of the conductive lines in the first layer and separating the air dielectric and conductive lines in the first layer from any subsequent layers. In a multi-layer semiconductor circuit with a plurality of conductive lines, at least the top, the bottom, and the opposite sides of each line are encapsulated by an adhesion-promotion barrier layer, and the barrier layer on the top of each conductive line has an upper surface that is flush with (a) a planar lower surface of a cap layer over the barrier layer, (b) a planar upper surface of a dielectric layer between the conductive lines, or (c) a combination thereof. The dielectric layer between the conductive lines may be air.

Abstract: A ball grid array (BGA) or chips scale package (CSP) integrated circuit (IC) (20) is manufactured by first identifying the most unreliable solder ball joints in the IC. These worst case joints, or joints in the vicinity of the worst case joints, are changed in pad dimension and exposed to more ball/bump conductive material than the other more robust joints (14) in the IC (20) to create a ball (24) on a larger pad (22) that is larger than the normal sized ball (14). The larger balls (24) are formed by placing multiple smaller balls (14) together on a single pad (22) to form one larger ball (24) during a reflow operation. The larger ball (24) improves the overall IC reliability by improving the reliability of the weakest joints in the IC design. In addition, the standoff of both the larger balls (24) and the smaller balls (14) are engineered to be substantially equal.

Abstract: Strip-shaped ditches are formed on a sapphire substrate as a base material. Then, the sapphire substrate is set into a CVD chamber, and an AlxGayInzN (x+y+z=1,x>0,y,z≧0)film is epitaxially grown on the sapphire substrate so as to embed the ditches by a selective lateral epitaxial growth method. As a result, the AlxGayInzN film has low dislocation density areas on at least one of the concave portions and the convex portions of the strip-shaped ditches.

Abstract: A method of applying an adhesive material comprising the steps of: providing the adhesive material on an interconnect substrate; and pressure-bonding the adhesive material to the interconnect substrate. A base has a plurality of first regions to be punched out and second regions located between the first regions. An interconnect pattern is formed at least in the first regions. Part of the adhesive material located within the first regions is pressurized to flow toward the second regions to move air bubbles to the second regions.

Abstract: A CMOS circuit has all-around dielectrically insulated source-drain regions. Trenches are formed in the source-drain regions. The trenches are etched onto the mono-crystalline silicon and filled with undoped or very lightly doped silicon. The completely or nearly completely depleted silicon in the trenches represents a dielectrically insulating layer and insulates the source-drain regions towards the adjacent silicon substrate.

Abstract: The semiconductor structure has an interconnect that is isolated by a cavity from an underlying insulating layer on a support. The fabrication method provides for the interconnect firstly to be patterned on a double layer and to be provided with an insulating covering. Then, an opening is etched into the insulating covering, and the lower conductive layer is selectively removed. As a result, one the one hand, low-capacitance wiring can be fabricated and, on the other hand, this enables MOS transistors to be programmed in a simple manner.

Abstract: Semiconductor device in which wiring surface area is increased while the increase of the capacitance between adjacent micro-wires is inhibited. The device can be prepared by forming an insulating layer and a plating feed layer in this order on a semiconductor substrate, plating after masking the plating feed layer with a first photoresist to form a gold plating, etching off the gold plating and the plating feed layer except for a wiring portion by dry-etching after masking the resultant surface with a second photoresist, removing then the first and second photoresists to form micro-wires, in which the same direction of the side portion is opened. The cross section may be U-shape arranged with U being turned sideways.

Abstract: A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon spheres define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are rigid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperatures up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are “T-topped” (i.e., viewed cross-sectionally). Dielectric fill is deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off an internal void.

Abstract: Dummy patterns are formed in signal patterns of a first metal layer, an insulating film covering such patterns is flattened by CMP, and only dummy patterns are selectively etched by anisotropic etching through holes opened at specific intervals. Then the opened holes are filled with an insulating film, and cavities are formed. In the upper part of the cavity, a signal line of the second metal layer is formed. As a result, a semiconductor device is provided by the CMP flattening technology without being accompanied by increase of parasitic capacity between signal lines by metal dummy patterns or shorting due to dust and the like.

Abstract: A wire in a semiconductor device and the fabricating the same are disclosed in the present invention. A semiconductor device includes a semiconductor substrate, a plurality of conductive layers on the semiconductor substrate, and an insulating layer on the semiconductor substrate including the conductive layers, the insulating layer having at least one void between each adjacent conductive layer.

Abstract: A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed over the first insulator. A via hole is formed in the second insulator and is electrically coupled to the first conductor through the via hole. A second conductor is formed on the second insulator, and is electrically coupled to the first conductor by the via hole. The second conductor is patterned. A cavity is formed under the second conductor, and in the first and second insulators.

Abstract: Trench isolation structure includes a first conformal insulating film (preferably consisting of silicon nitride) which lines a trench etched in a silicon substrate, an insulating layer (preferably consisting of silicon dioxide) which caps the lined trench and thereby forms a cavity, and a gas (preferably consisting of carbon dioxide) within the cavity. Fabrication of the trench isolation structure is begun by depositing a first conformal insulating film onto the surface of a trench etched in a silicon substrate, thereby forming a lined trench. An amorphous carbon layer is deposited within the lined trench and the lined trench is capped by an insulating layer which encloses the amorphous carbon within a cavity. The solid amorphous carbon within the cavity is converted to carbon dioxide gas by annealing the substrate in an oxidizing ambient. Planarizing the insulating layer to the level of the substrate completes fabrication of the trench isolation structure.

Abstract: A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the drain.

Abstract: A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the drain.

Abstract: A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by the method. The method includes formation and patterning of a mask on a silicon substrate followed by anisotropic etching of the silicon to provide a dense array of deep holes. Isotropic etching may be used to form a cavity beneath the dense array of holes and coupling to bottoms of the holes. Sides of the holes are then thermally oxidized. A conventional dielectric is then formed, sealing tops of the holes. The conventional dielectric is optionally densified. Conventional chemical-mechanical polishing then planarizes the dielectric and further conventional processing may be carried out on the wafer to form active circuitry together with passive components such as high Q inductors.

Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer As a result, the first structured dielectric layer has a substantially planar surface A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.

Abstract: An integrated circuit and method of making the integrated circuit. Air gaps are formed between surfaces of current-conducting lines that face one another and dielectric material disposed between these surfaces of the current-conducting lines. A liner material is applied to these surfaces of the current-conducting lines and, after the dielectric material is introduced between the current-conducting lines, the liner material is removed, for example by etching, leaving air gaps between the current-conducting lines and the dielectric material. These air gaps eliminate or greatly reduce the effect of capacitive currents across the dielectric material between the current-conducting lines.

Abstract: The present invention discloses a polycrystalline silicon thin film transistor connected to a gate line and a data line, including a source electrode contacting the data line; a gate electrode contacting the gate line; a drain electrode spaced apart from the source electrode; a polysilicon layer having upper and lower surfaces, the lower surface having a contacting area and a noncontacting area, the polysilicon layer being positioned between and contacting the source and the drain electrodes, and acting as a channel in which electrons flow; and a buffer layer positioned under the polysilicon layer, the buffer layer having a supporting portion, the supporting portion supporting the lower surface of the polysilicon layer through the contact area of the lower surface of the polysilicon layer, thereby forming a space between the buffer layer and the noncontacting area of the lower surface of the polysilicon layer.