Abstract: Integrated circuit (1) comprising a substrate (2), an active component (13) above the substrate (2), a cavity (14) surrounding partially the active component (13), a low dielectric region (15) surrounding partially the cavity (14) and a protective barrier (16) arranged around the low dielectric region (15).

Abstract: Air gaps may be provided in a self-aligned manner with sub-lithography resolution between closely spaced metal lines of sophisticated metallization systems of semiconductor devices by recessing the dielectric material in the vicinity of the metal lines and forming respective sidewall spacer elements. Thereafter, the spacer elements may be used as an etch mask so as to define the lateral dimension of a gap on the basis of the corresponding air gaps, which may then be obtained by depositing a further dielectric material.

Abstract: Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase the effective gate length (“Leffective”) and the field gate oxide. In yet another embodiment, a V-shaped trench is formed in the semiconductor structure to increase the Leffective and the field gate oxide. Semiconductor structures formed by these methods are also disclosed.

Abstract: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metalized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.

Abstract: This document discusses, among other things, a method including providing a laminate having a first conductive layer, a second conductive layer and an insulator between the first and second conductive layers. A hollow conductive via is formed through the insulator, the conductive via electrically connects the first and second conductive layers. At least one conductive trace electrically connects the hollow conductive via to at least one of the first and second conductive layers. The method further includes forming a channel in the insulator adjacent to the hollow conductive via and the channel surrounds the via. Wherein the channel extends at least part way between the first and second conductive layers, the at least one conductive trace bridges the channel, and the via is isolated from the insulator by the surrounding channel formed adjacent to the hollow conductive via.

Abstract: A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film.

Abstract: A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

Abstract: The present invention relates to a method of manufacturing a semiconductor substrate, which enables a semiconductor device to have high speed operating characteristics and high performance characteristics such as lower electrical power consumption, and a method of manufacturing a semiconductor device including a method of manufacturing the semiconductor substrate thereof in a process, as well as to a semiconductor substrate manufactured by the method of manufacturing the same and a semiconductor device manufactured using the semiconductor substrate.

Abstract: A semiconductor device includes a damascene structure and an air gap embedded in the damascene dielectric layer. A method of manufacturing a semiconductor device includes depositing a metal barrier in advance as an etch stop, forming a copper damascene interconnect structure, forming an air gap, and depositing a photosensitive passivation material on the air gap.

Abstract: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.

Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

Abstract: An integrated circuit structure combining air-gaps and metal-oxide-metal (MOM) capacitors is provided. The integrated circuit structure includes a semiconductor substrate; a first metallization layer over the semiconductor substrate; first metal features in the first metallization layer; a second metallization layer over the first metallization layer; second metal features in the second metallization layer, wherein the first and the second metal features are non-capacitor features; a MOM capacitor having an area in at least one of the first and the second metallization layers; and an air-gap in the first metallization layer and between the first metal features.

Abstract: The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.

Abstract: Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.

Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

Abstract: A first semiconductor chip includes a fixed electrode formed on a first semiconductor substrate and a plurality of first metal spacers formed on a first interlayer dielectric. A second semiconductor chip includes a vibrating electrode formed on a second semiconductor substrate and a plurality of second metal spacers formed on a second interlayer dielectric. The first and second semiconductor chips are metallically bonded to each other using the first and second metal spacers. An air gap is formed in a region of the condenser microphone located between the first semiconductor chip and the second semiconductor chip except bonded regions of the first and second metal spacers.

Abstract: Nano semiconductor switch devices are provided that include a semiconductor substrate and a conductive layer on the semiconductor substrate. A first insulating layer is provided on the conductive layer and the semiconductor substrate. The first insulating layer defines a contact hole that exposes at least a portion of the conductive layer. Carbon nano tubes are provided on the exposed portion of the conductive layer in the contact hole. The carbon nano tubes are in a vertical direction with respect to the semiconductor substrate. Related methods of fabrication are also provided herein.

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

Abstract: A component having an airdome enclosure that protects the component from its external environment. An airdome enclosure according to the present techniques avoids the high costs of employing special materials and/or specialized process steps in the manufacture of a component. An electronic component according to the present techniques includes a set of substructures formed on a substrate and an airdome enclosure over the substructures that protects the substructures and that hinders the formation of parasitic capacitances among the substructures.

Abstract: An object of the present invention is to prevent formation of a badly situated via metal in a Damascene wiring portion in multiple layers having an air-gap structure. In the present invention, a via is completely separated from an air-gap 45 by forming an interlayer insulating film 44 having the air-gap 45 between adjacent Damascene wiring portions after forming a sacrifice film pillar 42 from a selectively removable insulating film in a formation region of a connection hole. The present invention can provide multiple-layered buried wiring in which a high reliable via connection and a reduced parasitic capacitance due to the air-gap are achieved.

Abstract: In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.

Abstract: Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is formed on the buried insulating layer. A first insulating layer is formed to enclose the silicon pattern.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to form a semiconductor structure includes removing a portion of a semiconductor material to form one or more suspended structures and a cavity, the cavity having a boundary that is below a surface of the semiconductor material and wherein the one or more suspended structures extend from the surface into the cavity. The method further includes altering the one or more suspended structures to form one or more altered suspended structures and forming a material over the one or more altered suspended structures and in a region between the one or more altered suspended structures. Other embodiments are described and claimed.

Abstract: A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.

Abstract: One air gap structure is disposed so as to circle around the outer wall of a seal ring in a loop by arranging, within first insulating films located in a chip outer area corresponding to an outer area of the seal ring, air gaps into a line in parallel to the seal ring, which air gaps are hermetically-closed holes that are provided respectively in wiring layers other than portions corresponding to a global wiring layer and are extended in the thickness direction of first insulating films. When a crack occurs at a chip peripheral edge due to dicing or the like, the advancing direction thereof is changed by the air gaps to an upward direction, thereafter the crack advances toward the uppermost position in the chip outer area along the extending direction of the one air gap structure, so that the crack cannot reach the seal ring.

Abstract: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.

Abstract: The semiconductor device having an air gap includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A metal line is formed to fill the metal line forming region of the insulation layer. An air gap is formed between the insulation layer and the metal line.

Abstract: A semiconductor device includes a substrate where an isolation region and a plurality of active regions are defined, an anti-interference layer formed over the substrate in the isolation region, and a gate line simultaneously crossing the active region and the anti-interference layer.

Abstract: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.

Abstract: A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.

Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a norbornene-type polymer is used as a sacrificial material to occupy a closed interior volume in a semiconductor structure. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, preferably by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the norbornene-type polymer. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween.

Abstract: A micro electromechanical system and a fabrication method thereof, which has trenches formed on a substrate to prevent circuits from interfering each other, and to prevent over-etching of the substrate when releasing a microstructure.

Abstract: One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench. After the metal layer is formed, voids are formed in the insulator layer. One aspect of the present subject matter relates to an integrated circuit. In various embodiments, the integrated circuit includes an insulator structure having a plurality of voids that have a maximum size, and a metal layer formed in the insulator structure. The maximum size of the voids is larger than the minimum photo dimension of the metal layer such that a maximum-sized void is capable of extending between a first and second metal line in the metal layer. Other aspects are provided herein.

Abstract: The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.

Abstract: A semiconductor interconnect structure is provided that includes a new capping layer/dielectric material interface which is embedded inside the dielectric material. In particular, the new interface is an air gap that is located in the upper surface of a dielectric material that is adjacent to a conductive region or feature. The air gap may be unfilled, partially filled or completely filled with either a dielectric capping layer or an upper dielectric material. The presence of the air gap in the upper surface of the dielectric material that is adjacent to the conductive region or feature provides a new interface that has a high mechanical strength and thus the resultant structure is highly reliable. Moreover, the new interface provided in the present invention has a high dielectric breakdown resistance which is important for future technology extendibility.

Abstract: A high-frequency transistor includes an intrinsic region provided to form an active element on the substrate, plural source and drain fingers alternately located with each other in the intrinsic region in parallel, each including a strip-form interconnect metal layer and contacts formed thereon, plural gate fingers respectively formed between the source and drain fingers and each gate finger including a strip-form gate semiconductor layer, a connecting region provided on the substrate adjacent to and outside of the intrinsic region, plural gate connection semiconductor layers provided in the connecting region according to groups of the gate fingers, each group including some gate fingers adjacent to each other, each gate connection semiconductor layer being connected to end portions of the some gate fingers, and gate connection interconnect metal layers respectively formed on the gate connection semiconductor layers connected thereto through third contacts.

Abstract: An intermediate semiconductor structure is disclosed. The semiconductor structure includes a substrate; a relaxed Si1-xGex layer on the substrate, the relaxed Si1-xGex layer having at least one trench; an un-etched Si layer portion on the substrate and beneath the relaxed Si1-xGex layer along a periphery of the substrate providing structural support for the relaxed Si1-xGex layer along the periphery of the substrate; and at least one void between the relaxed Si1-xGex layer and the substrate, wherein the void encompasses an entire surface area of the substrate but for a portion of the substrate in contact with the un-etched Si layer portion.

Abstract: A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity.

Abstract: There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity, and having a heating element on the micro-structure capable of heating itself and its immediate surroundings. A layer of protective material is then deposited on said micro-structure such that at least a top surface of the micro-structure and an opening of the micro-cavity is covered, wherein the protective material is in a solid state at room temperature and can protect the micro-structure during silicon wafer dicing procedures and subsequent packaging. The integrated circuit is packaged and an electric current is passed through the heating element such that a portion of the protective material is removed and an unobstructed volume is provided above and below the micro-structure.

Abstract: A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.

Abstract: A semiconductor device comprises a buffer layer 16 of an i-InAlAs layer formed over an SI-InP substrate 14, insulating films 24, 36 of BCB formed over the buffer layer 16, and a coplanar interconnection including a signal line 52 and ground lines 54 formed over the insulating film 36, a cavity 46 is formed in the SI-InP substrate 14, the buffer layer 16 and the insulating film below the signal line 52, and pillar-shaped supports in the cavity 46 support the insulating films 34, 36 which are the ceiling of the cavity 46.

Abstract: A semiconductor device include a plurality of active element cells including first element regions of a first conductivity type and second element regions of a second conductivity type, the second element regions disposed between the first element regions; and isolation regions disposed between the active element cells so as to isolate the active element cells from each other, the isolation regions being filled with a plurality of semi-insulating particles including granular insulators covered by semiconductor films.

Abstract: Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.

Abstract: Methods of forming a gas dielectric and a related structure are disclosed. In one embodiment, the method includes providing a wiring level including at least one conductive portion within a sacrificial dielectric; forming a nanofiber layer over the wiring level; vaporizing the sacrificial dielectric by heating; evacuating the vaporized sacrificial layer; and sealing pores in the nanofiber layer.

Abstract: An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a portion of the dielectric layer surrounding the interconnect features. The interconnect features may also be embedded in a dielectric layer having two or more phases with a different dielectric constant created. The interconnect structure is compatible with current back end of line processing.

Abstract: A method is provided for designing a wiring structure of a wiring layer of a semiconductor integrated circuit device. The method includes a wire width detecting step of detecting a wire width of each wire in a wiring pattern of layout data, a wire identifying step of identifying a wire having a predetermined wire width or more based on a result of detection by the wire width detecting step, a wiring pitch detecting step of detecting a wiring pitch between the wire identified by the wire identifying step and another wire, and an air gap-forbidden region forming and removing step of forming or removing an air gap-forbidden region, depending on a result of detection by the wiring pitch detecting step.

Abstract: The present invention provides a zeolite sol which can be formed into a porous film that can be thinned to an intended thickness by a method used in the ordinary semiconductor process, that excels in dielectric properties, adhesion, film consistency and mechanical strength, and that can be easily thinned; a composition for film formation; a porous film and a method for forming the same; and a high-performing and highly reliable semiconductor device which contains this porous film inside. More specifically, the zeolite sol is prepared by hydrolyzing and decomposing a silane compound expressed by a general formula: Si(OR1)4 (wherein R1 represents a straight-chain or branched alkyl group having 1 to 4 carbons, and when there is more than one R1, the R1s can be independent and the same as or different from each other) in a conventional coating solution for forming a porous film in the presence of a structure-directing agent and a basic catalyst; and then by heating the silane compound at a temperature of 75° C.

Abstract: A method for making a pressure sensor including the steps of providing a substrate and forming or locating a pressure sensing component on the substrate. The method further includes the step of, after the forming or locating step, etching a cavity in the substrate below the pressure sensing component to define a diaphragm above the cavity with the pressure sensing component located on the diaphragm. The pressure sensing component includes an electrically conductive electron gas which changes its electrical resistance thereacross upon movement of the diaphragm.

Abstract: Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device.