Abstract: A semiconductor device includes a first island and a first electrode. The first island includes a first semiconductor region, a first insulation region, and a first insulating film. The first semiconductor region has first and second side surfaces adjacent to the first insulation region and the first insulating film, respectively. The first electrode is adjacent to the first insulation region and the first insulating film. The first insulating film is between the first electrode and the first semiconductor region.

Abstract: An ESD protection device includes a first discharge electrode and a second discharge electrode arranged to oppose each other, a discharge supporting electrode formed so as to span between the first and second discharge electrodes, and an insulator substrate that retains the first and second discharge electrodes and the discharge supporting electrode. The discharge supporting electrode is constituted by a group of a plurality of metal particles each coated with a semiconductor film containing silicon carbide. This discharge supporting electrode is obtained by firing a semiconductor-metal complex powder in which a semiconductor powder composed of silicon carbide is fixed to surfaces of metal particles. Selection is made so that the relationship between a coating amount Q [wt %] of the semiconductor powder in the semiconductor-metal complex powder and a specific surface area S [m2/g] of the metal powder satisfies Q/S?8.

Abstract: Memory cell structures for phase change memory. An example memory cell structure comprising includes a bottom electrode comprised of electrically conducting material, and phase change material disposed above the bottom electrode. A layer of thermally insulating material is disposed, at least partially, between the bottom electrode and the phase change material. The thermally insulating material is comprised of Tantalum Oxide. A top electrode is comprised of electrically conducting material.

Abstract: When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.

Abstract: An electronic fuse structure including an Mx level including a first Mx metal, a second Mx metal, and an Mx cap dielectric above of the first and second Mx metal, an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, and a nano-pillar located within the via and above the second Mx metal.

Abstract: A semiconductor device includes a MIS transistor. The MIS transistor includes an active region surrounded by an isolation region in a semiconductor substrate, a gate insulating film formed on the active region and the isolation region, and having a high dielectric constant film, and a gate electrode formed on the gate insulating film. A nitrided region is formed in at least part of a portion of the gate insulating film that is located on the isolation region. A concentration of nitrogen contained in the nitrided region is nx, and a concentration of nitrogen contained in a portion of the gate insulating film that is located on the active region is n, wherein a relationship of nx>n is satisfied.

Abstract: An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The OTP device has an OTP element coupled to the diode. The OTP device can be used to construct a two-dimensional OTP memory with the N terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline.

Abstract: A reprocessing method of a semiconductor device, the reprocessing method includes adjusting a resistance value of a first resistor by first trimming the first resistor, wherein the first resistor is electrically connected between a first pad and a second pad, forming a second resistor on the first trimmed first resistor, and adjusting a resistance value of the second resistor by second trimming the second resistor.

Abstract: Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source.

Abstract: An electronic circuit arrangement in accordance with some embodiments has a substrate, the substrate including: a plurality of metallization layers located one above the other; a single fuse-link via coupled between a first metallization layer and a second metallization layer of the plurality of metallization layers, wherein the single fuse-link via is in the form of an electrical fuse link preferentially programmable by applying a sufficiently large current to melt or degenerate the fuse link; a plurality of through-contact vias coupled in parallel between a third metallization layer and a fourth metallization layer of the plurality of metallization layers, wherein the through-contact vias form a through-contact between the third and fourth metallization layers; and electrical circuit components, arranged in a circuit layer, which are electrically coupled to one another by means of the single fuse-link via and by means of the plurality of through-contact vias.

Abstract: A repairable memory cell in accordance with one or more embodiments of the present disclosure includes a storage element positioned between a first and a second electrode, and a repair element positioned between the storage element and at least one of the first electrode and the second electrode.

Abstract: A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse.

Abstract: A metal gate process includes the following steps. An isolating layer on a substrate is provided, where the isolating layer has a first recess and a second recess. A first metal layer covering the first recess and the second recess is formed. A material is filled in the first recess but exposing a top part of the first recess. The first metal layer in the top part of the first recess and in the second recess is simultaneously removed. The material is removed. A second metal layer and a metal gate layer in the first recess and the second recess are sequentially filled.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse is substantially less than a thickness of the metal line.

Abstract: A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.

Abstract: A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width.

Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.

Abstract: Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device's effective width improves targeting of both on-resistance and current-carrying capability.

Abstract: The present disclosure relates to an electrode manufacturing method, and a fuse device and manufacturing method therefor. The fuse device includes a fuse element including a phase change material, and a first electrode formed in contact with the fuse element. The phase change material may include doped or undoped chalcogenide. The first electrode may have a sublithographic dimension at a portion where the first electrode contacts the fuse element. When the phase change material has a layer thickness less than or equal to about 30 nm, and a pulse current less than or equal to about 3 mA is applied to the fuse element via the first electrode, the fuse element may undergo a phase change, so as to convert the fuse device into a blow-out state.

Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

Abstract: A memory device is provided, which includes a memory element including a first electrode, a second electrode, and a silicon layer disposed between the first electrode and the second electrode. The memory element is capable of being in a first state, a second state, and a third state. A first data is written to the memory element being in the first state so that a potential of the first electrode is higher than a potential of the second electrode, whereby the memory element being in the second state is obtained. A second data is written to the memory element being in the first state so that a potential of the second electrode is higher than a potential of the first electrode, whereby the memory element being in the third state is obtained.

Abstract: A method of forming a semiconductor device includes forming a field-effect transistor (FET), and forming a fuse which includes a graphene layer and is electrically connected to the FET.

Abstract: On a silicon substrate 120 of a semiconductor device, a field oxide film 101 is provided. On the field oxide film 101, two fuses 104 are provided. Directly below the fuses 104 in the silicon substrate 120, an n-type well 102 is provided. Besides the n-type well 102, a p-type well 103 is provided in such a manner as to surround a region directly under the fuses 104 in the silicon substrate 120. A cover insulating film 108 is provided over the silicon substrate 120 and the field oxide film 101. A seal ring composed of a contact 106 and an interconnection 107 is embedded in the cover insulating film 108 so as to surround the fuses 104.

Abstract: A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

Abstract: A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first the via hole wiring is surrounded.

Abstract: A method of forming a device includes forming a silicon-containing line continuously extending between a first node and a second node. A first silicide-containing portion and a second silicide-containing portion are formed over the silicon-containing line. The first silicide-containing portion is separated from the second silicide-containing portion by a predetermined distance, and the predetermined distance is substantially equal to or less than a length of the silicon-containing line.

Abstract: The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in contact with the second insulating layer and the metal layer.

Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

Abstract: An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon substrate with a Shallow Trench Isolation formation, and a process of fabricating same are provided. The eFuse structure enables use of low amounts of current to blow a fuse thus allowing the use of a smaller MOSFET.

Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

Abstract: A semiconductor device includes an interlayer dielectric film, a passivation film, made of an insulating material, formed on the interlayer dielectric film, an uppermost wire, made of a material mainly composed of copper, formed between the surface of the interlayer dielectric film and the passivation film, and a wire covering film, made of a material mainly composed of aluminum, interposed between the passivation film and the surface of the uppermost wire for covering the surface of the uppermost wire.

Abstract: A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.

Abstract: Embodiments of a system with first means for forming a chamber adjacent to a component formed on a substrate and a single orifice between the chamber and a first surface of the first means that is opposite a second surface of the first means adjacent to the substrate and second means for enclosing the chamber on at least a portion of the first surface that encompasses the single orifice are disclosed.

Abstract: An electronic circuit arrangement has a substrate which has at least one metallization layer. At least one electrical interconnect and/or at least one via are formed in the metallization layer such that the electrical interconnect and the via are in the form of an electrical fuse link. In addition, the substrate has electrical circuit components which are arranged in the circuit layer. The circuit components are electrically coupled to one another by means of the electrical interconnect and by means of a plurality of vias.

Abstract: A semiconductor system includes a controller; a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller, wherein the controller comprises: a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information.

Abstract: A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract: An electrical fuse is provided. The electrical fuse includes an anode formed on a substrate, a cathode formed on the substrate, a fuse link connecting the anode and the cathode to each other, a first contact formed on the anode, and a second contact formed on the cathode and arranged closer to the fuse link than the first contact.

Abstract: To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad.

Abstract: An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.

Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.

Abstract: To provide a semiconductor device capable of reducing the line width of a fuse. In the semiconductor device, a dummy fuse is provided adjacent to a fuse, each wiring width of the fuse and the dummy fuse is set to the minimum line width, and the interval between the fuse and the dummy fuse is set to the minimum interval. Consequently, the exposure condition of the fuse and the dummy fuse is optimized by OPC, and therefore, it is possible to form the fuse with the minimum line width.

Abstract: Embodiments of present invention provide methods and apparatuses for connecting and/or disconnecting nodes in a semiconductor device. Embodiments of the apparatus may include a plurality of metal layers formed above a substrate and an interconnect structure formed between first and second nodes in the plurality of metal layers. The interconnect structure includes one or more metal lines formed in each of the metal layers. The metal lines are connected by a plurality of vias. Modifying one of the metal lines in any one of the metal layers changes an electrical connection between the first and second nodes.

Abstract: Methods of forming a microelectronic structure are provided, the microelectronic structure including a first conductor, a discontinuous film of metal nanoparticles disposed on a surface above the first conductor, a carbon nano-film formed atop the surface and the discontinuous film of metal nanoparticles, and a second conductor disposed above the carbon nano-film. Numerous additional aspects are provided.

Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

Abstract: An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via.

Abstract: An apparatus comprising an integrated circuit, an interconnect layer within said integrated circuit, and one or more connections. The integrated circuit may be configured to provide an electrically measurable interconnect pattern by enabling one or more of a plurality of components. The one or more connections may each configured to enable a respective one of the components. The connections may be programmable while the apparatus is part of a wafer. The interconnect pattern may be configured to identify the apparatus after the apparatus has been manufactured.