Abstract: A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added to a standard laser fuse structure such that it intersects the fuses and the number of available fuses is doubled.

Abstract: An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device.

Abstract: The prior art requires the selective removal of antifuse material from the bottom of the standard via. This cannot always be accomplished without damage to the nearby antifuse. In addition, in the absence of antifuse structural isolation, problems were encountered at M2 etch in consistently removing the full thickness of metallic material at this level. Shorting due to underetch was often encountered. These problems were solved by first forming only the antifuse via. This allowed the via to be controlled and optimized for antifuse requirements and for the antifuse material to be patterned without regard to possible side effects on the standard vias. Design rules for overlaps of overfuse and M2 layers were amended such that each antifuse is individually isolated. The latter were then formed, without (as in the prior art) any concerns that the antifuse might be affected.

Abstract: A multi-bit programmable memory cell is provided that includes an access transistor and a plurality of N anti-fuse elements. The access transistor has a source coupled to a source line and a gate coupled to a word line. Each of the anti-fuse elements has a first terminal coupled to a drain of the access transistor, and a second terminal coupled to a corresponding bit line. At most, only one of the anti-fuse elements is programmed. The memory cell is capable of storing M bits, wherein N=2M−1. A method is provided for both programming and reading the memory cell. In another embodiment, the anti-fuse elements can be replaced with mask-programmable elements.

Abstract: A method of manufacturing a semiconductor device comprises forming a thin film over a semiconductor substrate, patterning the thin film to define a portion of a laser trimming registration position pattern while simultaneously forming a fuse element formed from the same thin film and separate from the portion of the laser trimming position registration pattern, and forming a metallic film on the portion of the laser trimming position pattern but not on the fuse element.

Abstract: A semiconductor device having an array of dummy interconnections in a fuse window are proposed. The each dummy interconnection comprised of a fuse body scheduled to be blown away by laser beam, a fuse wiring extended up to the bottom of the fuse body from one side of the fuse window, and another fuse wiring extended up to the bottom of the fuse body form the another side of the fuse window. Contact plugs are disposed on terminal portions of the fuse wirings respectively, the terminal portions facing to each other having a predetermined gap between them. The bottom surfaces of both terminal portions of the fuse body are electrically connected with the facing terminal portions of the fuse wirings through the contact plugs, respectively. The length of the fuse body is set so as to have a length not shorter than the predetermined gap and not exceeding a diameter of laser beam to blow off the fuse body.

Abstract: A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an op

Abstract: A one-time programmable memory cell includes a fuse and an anti-fuse in series. The memory cell has two states, an initial state and a written (programmed) state. In the initial state, a resistance of the cell is finite, typically dominated by the relatively high resistance of the anti-fuse. In the written state, the resistance is infinite because the breakdown of the fuse resulting in an open circuit. The cell may be programmed by applying a critical voltage across the cell generating a critical current to cause the fuse to become open. When critical voltage is applied, this generally causes the anti-fuse to break down, which in turn causes a pulse of high current to be applied to the fuse. The states are detected by applying a read voltage across the memory cell. If the memory has not been programmed, then a measurable amount flows. Otherwise, no current flows.

Abstract: Within both an anti-fuse structure and a method for operating the anti-fuse structure there is employed a semiconductor substrate having a first region adjoining a second region, where there is formed a metal oxide semiconductor field effect transistor within and upon the first region of the semiconductor substrate and a metal oxide semiconductor capacitor within the upon the second region of the semiconductor substrate. Further, within the anti-fuse structure: (1) a gate dielectric layer within the metal oxide semiconductor field effect transistor is thicker than a capacitive dielectric layer within the metal oxide semiconductor capacitor; and (2) the metal oxide semiconductor capacitor is formed employing as a first capacitor plate a doped well within the semiconductor substrate of equivalent polarity with and overlapping with a source/drain region within the metal oxide semiconductor field effect transistor.

Abstract: Electrode layers (1, 2) are arranged on both sides of a dielectric layer (3) facing each other so as to configure a capacitor. Lead electrodes (4, 5) are formed in the electrode layers (1, 2). A penetrating electrode (6) that is insulated from the electrode layers (1, 2) is formed. An electronic component (10) configured in this manner is mounted on a wiring board, and a semiconductor chip can be mounted thereon. Along with connecting the semiconductor chip to the wiring board via the penetrating electrode (6), the semiconductor chip or the wiring board is connected to the lead electrodes (4, 5). In this manner, while suppressing the size increase of a mounted area, the capacitor or the like can be arranged near the semiconductor chip. Thus, the semiconductor chip is driven with high frequency more easily.

Abstract: The present invention provides a semiconductor device comprising: antifuses having insulation films; and a breakdown-circuit transistor provided in a breakdown circuit for breaking down the insulation films to set the antifuses in a conductive state. The insulation films of the antifuses are made up of the same material as that for a gate insulation film of the breakdown-circuit transistor and formed such that the film thickness of the insulation films are thinner than that of the gate insulation film.

Abstract: A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shielding the bottom floor. A second or barrier layer deposited onto the dielectric layer is interrupted or non-continuous at the undercut. A third, or electrically conductive layer, is electrically continuous over the fuse. A weak spot in the third layer exists in the lack of structural support by the second layer at the interruption. A further weak spot in the third layer exists in the electrical isolation of the conductor layer, i.e. no leakage current through the barrier layer, at the interruption.

Abstract: An antifuse memory cell comprises a first antifuse having a first electrode and a second electrode, a second antifuse having a first electrode and a second electrode, and an MOS transistor having a gate, a source and a drain, wherein the first electrode of the first antifuse is connected to the first electrode of the second antifuse, and the drain of the MOS transistor is connected to said first electrode of the first antifuse and the first electrode of the second antifuse.

Abstract: A method of producing an antifuse, comprises the steps of:

Abstract: A severable horizontal portion of a fuse link is formed relative to a vertically configured structure in an IC to promote separation of the severable portion upon applying energy from a laser beam. The vertically configured structure may be a reduced vertical thickness of the severable portion, an elevated lower surface of the severable portion above adjoining portions of the fuse link, a protrusion which supports the severable portion at a height greater than a height of the adjoining portions of the fuse link, flowing the melted severable portion down sloped surfaces away from a break point, and a propellent material beneath the severable portion which explodes to ablate the severable portion.

Abstract: In a semiconductor device having fusible conductive links, dummy patterns are formed in the vicinity of the fusible conductive links. As a density of a fuse region becomes thick by the dummy patterns, the fusible conductive links can be precisely formed.

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

Abstract: A process of forming an anti-fuse. First, an inter-metal dielectric layer, in which a funnel-shaped via is formed, is formed on a substrate. Next, a first conductive layer is formed over the substrate and filled into the funnel-shaped via. Subsequently, by, for example, a chemical mechanical polishing process, the first conductive layer outside the funnel-shaped via is removed to form a conductive plug. Afterward, an oxide chemical mechanical polishing process is performed to smooth the surface of the conductive plug. Next, a dielectric layer is formed on the top side of the conductive plug, and then a top plate is formed on the dielectric layer. Subsequently, an insulating layer is formed over the substrate, wherein the insulating layer is provided with a via and the via exposes the top plate. Finally, a second conductive layer is formed over the substrate and filled into the via.

Abstract: The present invention provides a two-terminal Zener zap diode device structure that relies upon the formation of an anti-fuse through a silicon substrate with the melting and flow of an aluminum alloy to create the current path. The use of oversized contacts in the diode structure permits the Tungsten plug to be eliminated from the diode structure and, thus, permits an aluminum alloy melt and flow mechanism to be used with a Tungsten plug process.

Abstract: A semiconductor device, capable of improving integration density and solving problems that may occur in a laser repair process, and a method of fabricating the same are provided. A fuse circuit is formed in a cell region, not in a peripheral region, and thus it is possible to reduce the size of a semiconductor chip.

Abstract: An antifuse structure has an antifuse between first and second thermal conduction regions. Each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity. The portion having low thermal conductivity is between the respective portion of high thermal conductivity and the antifuse.

Abstract: A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors.

Abstract: A memory array and some addressing circuitry therefor are formed by creating circuit elements at the crossing-points of two layers of electrode conductors that are separated by a layer of a semiconductor material. The circuit elements formed at the crossing-points function as data storage devices in the memory array, and function as connections for a permuted addressing scheme for addressing the elements in the array. In order to construct the addressing circuitry, the electrode conductors are fabricated with a controlled geometry at selected crossing-points such that selected circuit elements have increased or decreased cross-sectional area. By applying a programming electrical signal to the electrodes, the electrical characteristics (e.g. resistance) of selected circuit elements can be changed according to the controlled electrode geometry.

Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

Abstract: A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

Abstract: A metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. An insulating layer is disposed above a lower metal interconnect layer. The insulating layer includes a via formed therethrough containing a tungsten plug in electrical contact with the lower metal interconnect layer. The tungsten plug forms a lower electrode of the antifuse. The upper surface of the tungsten plug is planarized with the upper surface of the insulating layer. In a first embodiment, an antifuse material layer comprising amorphous carbon, amorphous carbon doped with hydrogen or fluorine, or amorphous silicon carbide is disposed above the upper surface of the tungsten plug. A layer of a barrier metal disposed over the antifuse material layer forms an upper electrode of the antifuse. An oxide or tungsten hard mask provides high etch selectivity and the possibility to etch barrier metals without affecting the dielectric constant value and mechanical properties of the antifuse material.

Abstract: An anti-fuse structure is set on an isolation layer positioned on a substrate. The anti-fuse structure includes a silicon conductive layer positioned in the isolation layer, a dielectric layer positioned on the top surface of the silicon conductive layer, and a metal conductive layer positioned on the surface of the isolation layer and covering the dielectric layer.

Abstract: A one-time programmable memory cell includes a fuse and an anti-fuse in series. The memory cell has two states, an initial state and a written (programmed) state. In the initial state, a resistance of the cell is finite, typically dominated by the relatively high resistance of the anti-fuse. In the written state, the resistance is infinite because the breakdown of the fuse resulting in an open circuit. The cell may be programmed by applying a critical voltage across the cell generating a critical current to cause the fuse to become open. When critical voltage is applied, this generally causes the anti-fuse to break down, which in turn causes a pulse of high current to be applied to the fuse. The states are detected by applying a read voltage across the memory cell. If the memory has not been programmed, then a measurable amount flows. Otherwise, no current flows.

Abstract: A memory device includes memory cells having two tunnel junctions in series. In order to program a selected memory cell, a first tunnel junction in the selected memory cell is blown. Blowing the first tunnel junction creates a short across the first tunnel junction, and changes the resistance of the selected memory cell from a first state to a second state. The change in resistance is detectable by a read process. The second tunnel junction has different anti-fuse characteristic than the first tunnel junction, and is not shorted by the write process. The second tunnel junction can therefore provide an isolation function to the memory cell after the first tunnel junction is blown.

Abstract: A memory structure has an antifuse material that is unpatterned and sandwiched between each of a plurality of antifuse electrode pairs. The antifuse material is continuous between the antifuse electrode pairs. Furthermore the present invention includes a memory structure comprising a plurality of antifuse electrode pairs forming a plurality of row conductors and a plurality of middle conductors in electrical communication with a plurality of control elements.

Abstract: In an integrated circuit where one desires the most compact arrangement of fuses and active circuitry, an insulating layer is deposited over active circuitry which includes the associated interconnect layers. A protective layer made with a reflective material may be used as a conductive layer above the lower layers of the integrated circuit containing active circuitry which includes interconnect layers of any desired number. This protective layer is patterned below the areas that will later contain fuses (or antifuses or both). Above this protective layer another insulating layer is deposited. A fuse layer which may be metal or another conductive film is then deposited. This conductive layer is patterned to provide the desired fuses (and/or antifuses) as required, with some or all of the fuses aligned with the protective layer deposited underneath.

Abstract: A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are formed on a first insulation layer 36 and arranged at a specified pitch. Side surfaces and top surfaces of the fuses 20 are covered by a second insulation layer 19.

Abstract: A semiconductor wiring structure positioned between plurality conductors, comprisies spacers positioned on adjacent ones of the conductors and at least one wiring element positioned between the spacers.

Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.

Abstract: A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field oxide layer. In a further embodiment, the polysilicon layer comprises a bottom conductor layer in the antifuse. In another embodiment, a refractory metal silicide layer is formed between the polysilicon layer and the antifuse. In yet a further embodiment, the refractory metal silicide layer comprises the bottom conductor layer in the antifuse.

Abstract: The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material.

Abstract: A programmable anti-fuse is formed simultaneously with transistors and other devices on a semiconductor substrate. Embodiments include an anti-fuse comprising a doped active region in the substrate, such as an n+ region, a gate oxide layer, and a gate, such as polysilicon, of a minimum size according to design rules. The anti-fuse is programmed by passing a current through it sufficient to cause its gate oxide layer to fail. The inventive anti-fuse is formed by simply altering the patterning of layers that need to be formed for other devices on the substrate. Therefore, it is formed without added manufacturing costs.

Abstract: An integrated circuit anti-fuse is described which is fabricated as a capacitor using a layer of oxide. The two plates of the anti-fuse are coupled to appropriate voltage levels to rupture the oxide and form a conductive short between the plates. One of the plates is formed as a diffused well which is coupled to an external voltage during programming. The well is biased to an internal voltage during normal operation of the circuit incorporating the anti-fuse.

Abstract: An antifuse is disposed between a first and second conductor. An insulating diffusion barrier (for example, silicon nitride) covers the sidewalls of the antifuse to inhibit contaminants (for example, copper, chlorine, fluorine, sodium, potassium, and moisture) from diffusing laterally into the antifuse from the interlayer dielectric, where a damascene copper conductor and/or a low-k dielectric is used. In a damascene antifuse structure, the insulating diffusion barrier layer covers an upper surface of the damascene conductor that is not covered by the antifuse. This insulating diffusion barrier layer inhibits copper from diffusing up into an interlayer dielectric and then diffusing laterally into the antifuse.

Abstract: Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cell both using a single nanotube to form the individual devices.

Abstract: A semiconductor antifuse device that utilizes a resistive heating element as both a heating source or fuse blowing and as part of the fuse link. The antifuse device may also be utilized as a fuse and the antifuse or fuse embodiment can be programmed and read with the same two electrodes. The antifuse or fuse is well suited for use and efficient fabrication in a printhead apparatus or other circuit arrangements.

Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.

Abstract: A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor substrate. Vertical transistors may be formed in other of the trench openings formed within the semiconductor substrate. The fuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads contacting the semiconductor plug. The antifuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads formed over the semiconductor plug, at least one conductive lead isolated from the semiconductor plug by an antifuse dielectric. Each of the fuse and antifuse are fabricated using a sequence of process operations also used to simultaneously fabricate vertical transistors according to vertical DRAM technology.

Abstract: The present invention relates to a one-time programmable (OTP) device including three fuses connected in parallel to a logic element which determines that the device is programmed when at least one of the fuses open. The present invention comprises a one-time programmable device that, before the one-time programmable device is programmed, provides, in response to a test signal, a simulation output signal that simulates an output signal that the one-time programmable device provides if the one-time programmable device is programmed.

Abstract: A fusible link device and a method of making same. The fusible link device comprising a poly layer having a center undoped portion and two doped end portions. The center undoped portion having a first resistance and the two doped end portions each having a second resistance that is lower than the first resistance. A silicide layer is formed over the poly layer with the silicide layer having a third resistance lower than the second resistance. The silicide layer agglomerating to form an electrical discontinuity within a discontinuity area in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased. The agglomeration of the silicide layer occurring over the center undoped portion of the poly layer. Contacts are electrically coupled to the two doped poly layer end portions for receiving the programming potential.

Abstract: The present invention is directed to novel antifuse arrays and their methods of fabrication. According to an embodiment of the present invention an array comprises a plurality of first spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric extends above the top surface of the semiconductor material. An antifuse material is formed on the top of the semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor material is formed on the antifuse material.

Abstract: A cross point memory array is fabricated on a substrate with a plurality of memory cells, each memory cell including a diode and an anti-fuse in series. First and second conducting materials are disposed in separate strips on the substrate to form a plurality of first and second orthogonal electrodes with cross points. A plurality of semiconductor layers are disposed between the first and second electrodes to form a plurality of diodes between the cross points of the first and second electrodes. A passivation layer is disposed between the first electrodes and the diodes to form a plurality of anti-fuses adjacent to the diodes at the cross points of first and second electrodes. Portions of the diode layers are removed between the electrode cross points to form the plurality of memory cells with rows of trenches between adjacent memory cells to provide a barrier against crosstalk between adjacent memory cells. The trenches extend substantially to the depth of the n-doped layer in each diode.

Abstract: A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

Abstract: A lower interconnection connected to a short circuit or a spare circuit is formed on a substrate, and a dielectric film is formed so as to cover the lower interconnection. An opening section is formed in the dielectric film so as to extend to an upper surface of the lower interconnection. A plug is formed in the opening section. An upper interconnection is formed on the plug by way of a predetermined void and is connected to a load circuit. When the upper interconnection and the lower interconnection are subjected to antifuse connection, electromigration is induced in an aluminum interconnection on the upper interconnection, thereby interconnecting the upper interconnection and the plug.

Abstract: A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.