Anti-fuse Patents (Class 257/530)
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Publication number: 20040065941Abstract: A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a first terminal coupled to the common bus line is selected to be programmed by a control transistor in a program driver circuit coupled to a second terminal of the antifuse. The program driver circuit has a high-voltage transistor with a diode coupled to its gate to bear a portion of the elevated voltage after the antifuse has been programmed. The program driver circuit also has an impedance transistor between the high-voltage transistor and the control transistor to reduce leakage current and the possibility of a snap-back condition in the control transistor. A read circuit includes a transistor coupled between a read voltage source and the second terminal to read the antifuse in an active mode.Type: ApplicationFiled: October 6, 2003Publication date: April 8, 2004Applicant: Micron Technology, Inc.Inventor: Kenneth W. Marr
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Patent number: 6717234Abstract: Resistive memory elements and arrays for data storage devices are disclosed. An exemplar resistive memory element generally has a first conductive structure and a second conductive structure, each of the conductive structures having a width of less than 1&lgr;, anti-fuse material on each conductive structure, and conductive material on the anti-fuse material such that anti-fuse material is interposed between each conductive structure and the conductive material.Type: GrantFiled: May 1, 2002Date of Patent: April 6, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Frederick A. Perner, Andrew L. Van Brocklin, Steven C. Johnson
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Patent number: 6716678Abstract: A method for producing antifuse structures and antifuses by which adjacent conductive regions can be selectively electrically connected involve the application of a sacrificial layer to a first conductive region. The sacrificial layer is patterned with the aid of a photolithographic method. A fuse layer is applied and the sacrificial layer is then removed. A non-conductive layer is applied and a conductive material is introduced in an opening in the non-conductive layer for the purpose of forming a second conductive region.Type: GrantFiled: March 3, 2003Date of Patent: April 6, 2004Assignee: Infineon Technologies AGInventors: Matthias Lehr, Uwe Schilling, Veronika Polei, Irene Sperl
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Patent number: 6713839Abstract: An antifuse includes a grid having at least one n-well active stripe and at least one polysilicon stripe; a first oxide layer having a first oxide thickness, the first oxide layer adapted to electrically short the n-well active stripe with the polysilicon stripe; and a second oxide layer surrounding the first oxide and thicker than the first oxide layer.Type: GrantFiled: May 24, 2002Date of Patent: March 30, 2004Assignee: AirIPInventor: Raminda U. Madurawe
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Publication number: 20040051162Abstract: As disclosed herein, a structure and method is provided for forming an integrated circuit including a reduced programming voltage antifuse on a semiconductor substrate. The method includes doping a portion of a semiconductor substrate with nitrogen and a charge carrier dopant source, and forming a thin dielectric over the doped portion of the semiconductor substrate, wherein the thin dielectric is subject to breakdown upon application of a breakdown voltage. The method further includes forming a first conductor separated from the semiconductor substrate by the thin dielectric, and forming a second conductor conductively coupled to the doped portion of the semiconductor substrate.Type: ApplicationFiled: September 13, 2002Publication date: March 18, 2004Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Infineon Technologies North America Corp.Inventors: Dureseti Chidambarrao, Ulrich Frey, Suryanarayan G. Hegde, William Robert Tonti
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Patent number: 6707063Abstract: A process of fabricating a molecular electronic device that preserves the integrity of the active molecular layer of the electronic device during processing is described. In one aspect, a passivation layer is provided to protect a molecular layer from degradation during patterning of the top wire layer. A molecular electronic device structure and a memory system that are formed from this fabrication process are described.Type: GrantFiled: March 22, 2001Date of Patent: March 16, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventor: Yong Chen
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Patent number: 6704235Abstract: A memory cell for a two- or a three-dimensional memory array includes first and second conductors and set of layers situated between the conductors. This set of layers includes a dielectric rupture anti-fuse layer having a thickness less than 35 Å and a leakage current density (in the unruptured state) greater than 1 mA/cm2 at 2 V. This low thickness and high current leakage density provide a memory cell with an asymmetric dielectric layer breakdown voltage characteristic. The antifuse layer is formed of an antifuse material characterized by a thickness Tminlife at which the antifuse material is ruptured by a minimum number of write pulses having a polarity that reverse biases diode components included in the memory cell. The average thickness T of the antifuse layer is less than the thickness Tminlife.Type: GrantFiled: December 20, 2001Date of Patent: March 9, 2004Assignee: Matrix Semiconductor, Inc.Inventors: N. Johan Knall, James M. Cleeves, Igor G. Kouznetsov, Michael A. Vyvoda
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Publication number: 20040041233Abstract: The antifuse device comprises an insulating layer positioned in the trench, a conductive member positioned above the insulating layer, at least a portion of the conductive member being positioned within the trench, the conductive member adapted to have at least one programming voltage applied thereto, and at least one doped active region formed in the substrate adjacent the trench. The antifuse further comprises at least one conductive contact coupled to the conductive member, and at least one conductive contact coupled to the doped active region.Type: ApplicationFiled: August 29, 2002Publication date: March 4, 2004Inventor: Stephen R. Porter
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Patent number: 6700176Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.Type: GrantFiled: July 18, 2002Date of Patent: March 2, 2004Assignee: Broadcom CorporationInventors: Akira Ito, Douglas D. Smith, Myron J. Buer
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Patent number: 6693819Abstract: The present invention relates to a high voltage switch used with a one-time programmable memory device and a method of setting a state of a one-time programmable memory device using such a high voltage switch. The memory device includes a plurality of one time programmable memory cells arranged in an array and adapted to be programmed using a high voltage, wherein each of the memory cells includes at least one storage element and two gated fuses connected to the storage element. A high voltage switch is connected to at least one of the memory cells and is adapted to switch in a high voltage.Type: GrantFiled: January 8, 2002Date of Patent: February 17, 2004Assignee: Broadcom CorporationInventors: Douglas D. Smith, Myron Buer, Bassem Radieddine
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Publication number: 20040023441Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.Type: ApplicationFiled: April 8, 2003Publication date: February 5, 2004Inventor: Jigish D. Trivedi
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Publication number: 20040021200Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.Type: ApplicationFiled: November 7, 2002Publication date: February 5, 2004Inventor: Jigish D. Trivedi
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Publication number: 20040023440Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.Type: ApplicationFiled: July 18, 2002Publication date: February 5, 2004Applicant: Broadcom CorporationInventors: Akira Ito, Douglas D. Smith, Myron J. Buer
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Publication number: 20040021199Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the comers of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.Type: ApplicationFiled: August 1, 2002Publication date: February 5, 2004Inventor: Jigish D. Trivedi
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Patent number: 6686644Abstract: A high-strength protective member made of tungsten is disposed under a disconnecting point of a fuse. This protective member is formed simultaneously with formation of a via contact portion which connects the fuse with wiring, for example.Type: GrantFiled: March 22, 2002Date of Patent: February 3, 2004Assignee: Fujitsu LimitedInventors: Tsutomu Tatematsu, Kengi Togashi, Masayuki Nakada, Toyoji Sawada, Kazuo Sukegawa, Tomoyuki Yamada, Yoshikazu Arisaka
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Patent number: 6686646Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.Type: GrantFiled: September 25, 2002Date of Patent: February 3, 2004Assignee: Matrix Semiconductor, Inc.Inventor: Thomas H. Lee
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Publication number: 20040016991Abstract: Silicon nitride antifuses can be advantageously used in memory arrays employing diode-antifuse cells. Silicon nitride antifuses can be ruptured faster and at a lower breakdown field than antifuses formed of other materials, such as silicon dioxide. Examples are given of monolithic three dimensional memory arrays using silicon nitride antifuses with memory cells disposed in rail-stacks and pillars, and including PN and Schottky diodes. Pairing a silicon nitride antifuse with a low-density, high-resistivity conductor gives even better device performance.Type: ApplicationFiled: June 30, 2003Publication date: January 29, 2004Applicant: MATRIX SEMICONDUCTOR, Inc.Inventors: Mark G. Johnson, N. Johan Knall, S. Brad Herner
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Patent number: 6683365Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.Type: GrantFiled: August 1, 2002Date of Patent: January 27, 2004Assignee: Micron Technology, Inc.Inventor: Jigish D. Trivedi
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Publication number: 20040012074Abstract: The present invention provides a method for forming an antifuse via structure. The antifuse via structures comprising a substrate that having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer is formed on the first dielectric layer. Next, an etching process is performed to etch the first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to form a conductive plug, wherein the conductive plug is on the first conductive wire. Next, a buffer layer deposited on the partial first dielectric layer and on the surface of conductive plug. Then, another polishing process is performed to the buffer layer to expose the portion of the conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer.Type: ApplicationFiled: December 23, 2002Publication date: January 22, 2004Applicant: United Micorelectronics, Corp.Inventor: Tsong-Minn Hsieh
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Patent number: 6680519Abstract: Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided.Type: GrantFiled: April 26, 2001Date of Patent: January 20, 2004Assignee: Micron Technology, Inc.Inventor: H. Montgomery Manning
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Patent number: 6680520Abstract: The present invention describes an apparatus and method for fabrication of a precision circuit elements. In particular, the circuit elements are fabricated as part of an integrated circuit assembly. The processing of the circuit elements is such to provide a nominal circuit element value close in value to the desired value. Additional trim circuit elements are joined to the nominal circuit element through links. The links are fusible links or antifuses. By selectively blowing the fusible links or fusing the antifuses, trim circuit elements are added or subtracted to personalize the value of the nominal circuit element. A capacitor is used in an illustrative example.Type: GrantFiled: March 14, 2000Date of Patent: January 20, 2004Assignee: International Business Machines CorporationInventors: Steven H. Voldman, Anthony K. Stamper
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Publication number: 20040004269Abstract: A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.Type: ApplicationFiled: July 8, 2002Publication date: January 8, 2004Applicant: International Business Machines CorporationInventors: John A. Fifield, Russell J. Houghton, William R. Tonti
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Patent number: 6657277Abstract: The present invention provides a method for forming an antifuse via structure. The antifuse via structures comprising a substrate that having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer is formed on the first dielectric layer. Next, an etching process is performed to etch the first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to form a conductive plug, wherein the conductive plug is on the first conductive wire. Next, a buffer layer deposited on the partial first dielectric layer and on the surface of conductive plug. Then another polishing process is performed to the buffer layer to expose the portion of the conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer.Type: GrantFiled: July 19, 2002Date of Patent: December 2, 2003Assignee: United Microelectronics CorporationInventor: Tsong-Minn Hsieh
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Patent number: 6657278Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.Type: GrantFiled: September 25, 2002Date of Patent: December 2, 2003Assignee: Matrix Semiconductor, Inc.Inventor: Thomas H. Lee
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Publication number: 20030218234Abstract: An antifuse includes a grid having at least one n-well active stripe and at least one polysilicon stripe; a first oxide layer having a first oxide thickness, the first oxide layer adapted to electrically short the n-well active stripe with the polysilicon stripe; and a second oxide layer surrounding the first oxide and thicker than the first oxide layer.Type: ApplicationFiled: May 24, 2002Publication date: November 27, 2003Inventor: Raminda U. Madurawe
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Patent number: 6653712Abstract: A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.Type: GrantFiled: May 22, 2002Date of Patent: November 25, 2003Assignee: Matrix Semiconductor, Inc.Inventors: N. Johan Knall, Mark Johnson
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Patent number: 6653710Abstract: Thermal degradation of a low-k organic dielectric material is avoided or limited in the proximity of a heat source such as a fusible element by overlaying the low-k material with a thermally conductive material and providing a low thermal resistance path from the thermally conductive material, possibly having a low modulus of elasticity, to a heat sink. The thermally conductive material thus provides crack-stop protection for further layers of an integrated circuit or interconnect structure above the fusible element by mechanical, chemical and thermal encapsulation of the heat source and low-k material.Type: GrantFiled: February 16, 2001Date of Patent: November 25, 2003Assignee: International Business Machines CorporationInventors: James W. Adkisson, Edward Maciejewski, Peter Smeys, Anthony K. Stamper
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Publication number: 20030214014Abstract: A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.Type: ApplicationFiled: June 16, 2003Publication date: November 20, 2003Applicant: KAWASAKI MICROELECTRONICS, INC.Inventors: Ryuji Ariyoshi, Isamu Kuno, Takahito Fukushima, Junji Aoike
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Patent number: 6649997Abstract: A laminated dummy pattern formed of plural metals including aluminum and tungsten is formed below a fuse or anti-fuse and an influence by application of laser energy at the time of laser blow on an wiring or element can be prevented.Type: GrantFiled: October 4, 1999Date of Patent: November 18, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Hidetoshi Koike
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Patent number: 6642602Abstract: An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18). Each anti-fuse circuit comprising an anti-fuse (30) connected in a series with a blow or control transistor (36) and a control circuit (44) for monitoring the status of the anti-fuse (30), Control circuit (44) provides an “on” signal to the gate (38) of control transistor (36) only when a_“select_” signal is received at an input (46) of control circuit (44) and if anti-fuse (30) has not been blown. After the anti-fuse (30) is blown, control circuit (44) turns off the control transistor (36) thereby providing a constant power source voltage across each anti-fuse circuit (24, 26, 28, N) regardless of the number of parallel anti-fuses which have been blown.Type: GrantFiled: December 14, 2001Date of Patent: November 4, 2003Assignee: Infineon Technologies AGInventors: Gunther Lehmann, Ulrich Frey, Oliver Weinfurtner
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Patent number: 6642603Abstract: A memory cell for a 3-D integrated circuit memory is described. An antifuse region is sandwiched between two heavily doped regions of the same conductivity type.Type: GrantFiled: June 27, 2002Date of Patent: November 4, 2003Assignee: Matrix Semiconductor, Inc.Inventor: N. Johan Knall
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Patent number: 6642102Abstract: A method comprising forming as stacked materials on a substrate, a volume of programmable material and a signal line, conformably forming a first dielectric material on the stacked materials, forming a second dielectric material on the first material, etching an opening in the second dielectric material with an etchant that, between the first dielectric material and the second dielectric material, favors removal of the second dielectric material, and forming a contact in the opening to the stacked materials. An apparatus comprising a contact point formed on a substrate, a volume of programmable material formed on the contact point, a signal line formed on the volume of programmable material, a first dielectric material conformally formed on the signal line, a different second dielectric material formed on the first dielectric material, and a contact formed through the first dielectric material and the second dielectric material to the signal line.Type: GrantFiled: June 30, 2001Date of Patent: November 4, 2003Assignee: Intel CorporationInventor: Daniel Xu
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Publication number: 20030201515Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.Type: ApplicationFiled: April 15, 2003Publication date: October 30, 2003Applicant: International Business Machines CorporationInventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
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Publication number: 20030201514Abstract: A semiconductor device having an increased intersection perimeter between edge regions of a first conductor and portions of a second conductor is disclosed. In one embodiment, the intersection perimeter is the region where the perimeter of a gate structure overlaps an active area. The intersection perimeter between the conductors directs the breakdown of the dielectric material, increasing the likelihood that the programming event will be successful. In at least one embodiment, the portion of a current path that travels through a highly doped area is increased while the portion that travels through a non-highly doped area is decreased. This decreases post-program resistance, leading to better response time for the device.Type: ApplicationFiled: April 17, 2002Publication date: October 30, 2003Applicant: International Business Machines CorporationInventors: Carl J. Radens, William R. Tonti
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Patent number: 6633180Abstract: A semiconductor die is provided with an internally programmable router to assign signal paths to select connection points. A switching matrix incorporating at least one antifuse is utilized to selectively route signal paths on the semiconductor die. The chips can then be used individually, for example to reconfigure chip pin assignments to operate in a plurality of different socket layouts, or where features or controls of a chip are selectively enabled or disabled. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked against.Type: GrantFiled: September 12, 2002Date of Patent: October 14, 2003Assignee: Micron Technology, Inc.Inventor: Kevin Duesman
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Patent number: 6630724Abstract: A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a first terminal coupled to the common bus line is selected to be programmed by a control transistor in a program driver circuit coupled to a second terminal of the antifuse. The program driver circuit has a high-voltage transistor with a diode coupled to its gate to bear a portion of the elevated voltage after the antifuse has been programmed. The program driver circuit also has an impedance transistor between the high-voltage transistor and the control transistor to reduce leakage current and the possibility of a snap-back condition in the control transistor. A read circuit includes a transistor coupled between a read voltage source and the second terminal to read the antifuse in an active mode.Type: GrantFiled: August 31, 2000Date of Patent: October 7, 2003Assignee: Micron Technology, Inc.Inventor: Kenneth W. Marr
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Patent number: 6627969Abstract: A metal-to-metal conductive plug-type antifuse has a conductive plug disposed in an opening in an insulating layer. A programmable material feature (for example, amorphous silicon) overlies the conductive plug. A conductor involving a metal (for example, aluminum or copper) that migrates in the programmable material overlies the programmable material. To prevent migration of metal from the conductor into the programmable material when the antifuse is not programmed, the conductor has a layer of barrier metal between the metal that migrates and the programmable material. In some embodiments, there are two layers of barrier metal. An airbreak after formation of the first barrier metal layer improves the ability of the barrier metal to prevent diffusion between the programmable material and the overlying conductor.Type: GrantFiled: May 1, 2000Date of Patent: September 30, 2003Assignee: QuickLasic CorporationInventors: Rajiv Jain, Andre Stolmeijer, Mehul D. Shroff
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Patent number: 6627985Abstract: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.Type: GrantFiled: December 5, 2001Date of Patent: September 30, 2003Assignee: Arbor Company LLPInventors: Jon M. Huppenthal, D. James Guzy
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Patent number: 6627970Abstract: An integrated semiconductor circuit, in particular a semiconductor memory circuit, having at least one integrated electrical antifuse structure is described. The antifuse structure is located within an insulated well composed of semiconductor material.Type: GrantFiled: December 20, 2000Date of Patent: September 30, 2003Assignee: Infineon Technologies AGInventors: Robert Fuller, Helmut Schneider
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Publication number: 20030178693Abstract: Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that a programming pulse voltage is scalable with Vdd. One aspect of the present subject matter is an antifuse device that is positioned or coupled between a first metal level and a second metal level. One embodiment of the antifuse device includes a porous antifuse dielectric layer, and at least one injector Silicon-Rich-Insulator (SRI) layer in contact with the porous antifuse dielectric layer. In one embodiment, the porous antifuse dielectric layer includes SiO2 formed with air-filled voids. In one embodiment, the at least one injector SRI layer includes two injector Silicon-Rich-Nitride layers that sandwich the porous antifuse dielectric layer. Other aspects are provided herein.Type: ApplicationFiled: March 25, 2002Publication date: September 25, 2003Applicant: Micron Technology, Inc.Inventors: Arup Bhattacharyya, Joseph E. Geusic
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Publication number: 20030173643Abstract: An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.Type: ApplicationFiled: March 13, 2002Publication date: September 18, 2003Applicant: Matrix Semiconductor, Inc.Inventor: S. Brad Herner
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Patent number: 6621138Abstract: A semiconductor device includes a polysilicon layer in which a first region of a first conductivity type and a second region of a second conductivity type is formed. The first region and the second region form a p-n junction in the polysilicon layer. The semiconductor device further includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region. In operation, a low resistance path is formed between the first and second metallization region when a voltage or a current exceeding a predetermined threshold level is applied to the first or the second region. The voltage or current is applied for zap trimming of the p-n junction where the voltage or current exceeding a predetermined threshold level, together with the resulting current or resulting voltage, provides power sufficient to cause the low resistance path to be formed.Type: GrantFiled: October 21, 2002Date of Patent: September 16, 2003Assignee: Micrel, Inc.Inventor: Martin Alter
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Patent number: 6621095Abstract: An apparatus including a contact on a substrate, a dielectric material overlying the contact, a phase change element overlying the dielectric material on a substrate, and a heater element disposed in the dielectric material and coupled to the contact and the phase change element, wherein a portion of the dielectric material comprises a thermal conductivity less than silicon dioxide. A method including introducing over a contact formed on a substrate, a dielectric material, a portion of which comprises a thermal conductivity less than silicon dioxide, introducing a heater element through the dielectric material to the contact, and introducing a phase change material over the dielectric material and the heater element.Type: GrantFiled: August 29, 2001Date of Patent: September 16, 2003Assignee: Ovonyx, Inc.Inventors: Chien Chiang, Guy C. Wicker
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Patent number: 6617664Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.Type: GrantFiled: April 18, 2002Date of Patent: September 9, 2003Assignee: Fujitsu LimitedInventors: Manabu Hayashi, Junichi Yayanagi
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Patent number: 6617914Abstract: An antifuse having a dielectric disposed between a plurality of conductive elements is programmed with one of the conductive elements connected to a capacitor. The antifuse is programmed to an “on” state by precharging the capacitor and then applying a programming voltage to another one of the conductive elements. This results in the breakdown of the interposed dielectric to form a conductive link between the conductive elements. Immediately, following the formation of a conductive link, the electrical energy stored in the capacitor is released through the conductive link across the dielectric. Further, the capacitor can be common to a plurality of programmable antifuses and the application of the programming voltage serves to select one of the plurality of antifuses to be ‘blown’. This arrangement can be realized in a FET and the device can be easily integrated in the CMOS process commonly used for the manufacture of memory arrays and logic circuitry.Type: GrantFiled: March 5, 2002Date of Patent: September 9, 2003Assignee: Infineon Technologies AGInventor: Chandrasekharan Kothandaraman
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Publication number: 20030160298Abstract: The anti-fuse comprises a substitutable layer 14, an interconnection layer 20 connected to the substitutable layer, and the interconnection layer contains metal atoms which can be substituted with constituent atoms of the substitutable layer. The anti-fuse can be changed from the non-conduction state to the conduction state at a relatively low temperature of 300° C. to 600° C., and by application of not so intense laser beams, the anti-fuse can be changed from the non-conduction state to the conduction state. The anti-fuse can be changed from the non-conduction state to the conduction state by using an inexpensive equipment, which can realize decrease of fabrication costs and accordingly inexpensive semiconductor devices can be provided.Type: ApplicationFiled: January 22, 2003Publication date: August 28, 2003Applicant: FUJITSU LIMITEDInventor: Shunji Nakamura
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Patent number: 6611040Abstract: An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well. Gates over the p-well are positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into the write-register. The overstress voltage pulse is applied between the gate and the p-well and is created when a write-enable pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.Type: GrantFiled: June 2, 2001Date of Patent: August 26, 2003Inventors: Tito Gelsomini, Kemal Tamer San
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Publication number: 20030146491Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.Type: ApplicationFiled: February 21, 2003Publication date: August 7, 2003Inventor: Katsuhiko Tsuura
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Patent number: 6603187Abstract: The present invention relates to a high performance, high reliability antifuse using conductive electrodes. According to first and second embodiments, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing conductive electrode materials having a relatively lower thermal conductivity than prior art electrode materials and by utilizing relatively thin electrodes, thus increasing their thermal resistance. According to a third embodiment, a relatively thin barrier layer is placed between one or both of the low thermal conductivity electrodes and the antifuse material to prevent reaction between the conductive electrodes and the antifuse material, or the materials used in manufacturing. According to a fourth embodiment, low thermal conductivity conductors are used for both electrodes in the conductor-to-conductor antifuse to achieve enhanced reliability and freedom from switch-off.Type: GrantFiled: February 23, 2000Date of Patent: August 5, 2003Assignee: Actel CorporationInventors: Guobiao Zhang, Chenming Hu, Steve S. Chiang
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Patent number: 6603142Abstract: A metal-to-metal antifuse disposed above and insulated from a semiconductor substrate comprises a first metal layer disposed above and insulated from the semiconductor substrate. A layer of antifuse material is disposed over and in electrical contact with the first metal layer. A second metal layer is disposed over and in electrical contact with the layer of antifuse material. At least one barrier layer comprising a layer of TaN is disposed between the layer of antifuse material and one of the first and second metal layers.Type: GrantFiled: December 18, 2000Date of Patent: August 5, 2003Assignee: Actel CorporationInventors: Jeewika Ranaweera, Roy Lambertson