Abstract: In a semiconductor device having a fuse 11 which makes connection between a first interconnection 10 and a second interconnection 12, and a first low heat-conductive section 13 which makes connection between the first interconnection 10 and a third interconnection 14 at a site of the first interconnection 10 where the fuse 11 is not connected, the first low heat-conductive section 13 is fabricated from a material having a heat conductivity lower than that of the material to form the first interconnection 10. When the fuse is blown with the laser beam irradiation, the heat dissipation through the heat conduction along the fuse and the interconnection is to be suppressed, and thereby a satisfactory disconnection at the fuse is to be achieved.

Abstract: An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device.

Abstract: There is provided a trimming pattern enabling trimming to be implemented with ease and time required for trimming to be shortened without causing damage to internal elements. The invention provides the trimming pattern for use in trimming of a semiconductor integrated circuit, comprising two pads to which a voltage is applied, a thin line part interconnecting the two pads, and two connecting parts disposed away from each side of the thin line part, and connected to an adjustment circuit and the semiconductor integrated circuit, respectively. With the invention, trimming is executed by a method of turning the adjustment circuit connected to the connecting parts into the ON state by connecting fused metal of the thin line part to the connecting parts. In this case, since the fused metal can be caused to come into contact with the connecting parts nearby with greater ease than fusion cutting of the thin line part, trimming can be implemented with ease and in shorter time.

Abstract: A memory structure that includes a first electrode, a second electrode, a third electrode, a control element of a predetermined device type disposed between the first electrode and the second electrode, and a memory storage element of the predetermined device type disposed between the second electrode and the third electrode. The memory storage element has a cross-sectional area that is less than a cross-sectional area of the control element.

Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1+/?0.4, and the ratio of x to y in SixNy is in a range of about 0.75+/?0.225.

Abstract: A one-time programming memory element, capable of being manufactured in a 0.13 ?m or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current, and a switch having a voltage tolerance higher than that of the capacitor/transistor, wherein the capacitor/transistor is one-time programmable as an anti-fuse by application of a voltage across the oxide layer via the switch to cause direct gate tunneling current to thereby rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

Abstract: A low-density, high-resistivity layer of a PVD sputter-deposited material, preferably titanium nitride, when coupled with a dielectric, makes a superior low-leakage insulating barrier for use in semiconductor devices. The material is created by sputtering methods that cause the ions to strike the deposition surface with reduced energy, for example in an ion metal plasma chamber with no self-bias accelerating ions normal to the deposition surface, or in a standard PVD chamber with pressure increased.

Abstract: A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.

Abstract: The invention provides for a vertically oriented junction diode having a contact-antifuse unit in contact with one of its electrodes. The contact-antifuse unit is formed either above or below the junction diode, and comprises a silicide with a dielectric antifuse layer formed on and in contact with it. In preferred embodiments, the silicide is cobalt silicide, and the antifuse preferably silicon oxide, silicon nitride, or silicon oxynitride grown on the colbalt silicide. The junction diode and contact-antifuse unit can be used as a memory cell, which is advantageously used in a monolithic three dimensional memory array.

Abstract: Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that a programming pulse voltage is scalable with Vdd. One aspect of the present subject matter is an antifuse device that is positioned or coupled between a first metal level and a second metal level. One embodiment of the antifuse device includes a porous antifuse dielectric layer, and at least one injector Silicon-Rich-Insulator (SRI) layer in contact with the porous antifuse dielectric layer. In one embodiment, the porous antifuse dielectric layer includes SiO2 formed with air-filled voids. In one embodiment, the at least one injector SRI layer includes two injector Silicon-Rich-Nitride layers that sandwich the porous antifuse dielectric layer. Other aspects are provided herein.

Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.

Abstract: A memory structure that includes a first electrode, a second electrode, a third electrode, a control element disposed between the first electrode and the second electrode, and a memory storage element disposed between the second electrode and the third electrode. At least one of the control element and memory storage element is protected from contamination by at least one of the first electrode, second electrode and third electrode.

Abstract: According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.

Abstract: Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by applying a programming current to the fuse link. The silicon or polysilicon in the fuses may be provided with a p-n junction. When a fuse is programmed, the silicide or other conductive film forms an open circuit. This forces current though the underlying p-n junction. Unlike conventional silicided polysilicon fuses, fuses with p-n junctions change their qualitative behavior when programmed. Unprogrammed fuses behave like resistors, while programmed fuses behave like diodes. The presence of the p-n junction allows sensing circuitry to determine in a highly accurate qualitative fashion whether a given fuse has been programmed.

Abstract: A metal-to-metal capacitor in a semiconductor integrated circuit is converted to a conductive structure by connecting the first metal plate of the capacitor to ground and the second metal plate of the capacitor to a programming voltage, thus causing the insulator material to breakdown and conduct current from the first plate to the second plate.

Abstract: An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.

Abstract: Method for producing an antifuse in a substrate, a first interconnect being applied to the substrate, a dielectric layer being applied at an end face of the first interconnect, which end face essentially runs vertically with respect to the substrate, a second interconnect being applied in such a way that it adjoins the dielectric layer with an end face, with the result that an antifuse structure is formed.

Abstract: A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact to heat the gate. The current through the gate indirectly heats the channel region beneath the gate, causing localized annealing of the channel region. The heated gate causes dopants to diffuse from the source and drain into the channel region, permanently changing the properties of the transistor material and programming the fuse device. The fuse device functions as a transistor in an unprogrammed state, and acts as a shunt in a programmed state, caused by the shorting of the source and drain of the transistor during programming.

Abstract: In one aspect, a semiconductor device includes an array of memory cells. Individual memory cell of the array include a capacitor having first and second electrode, a dielectric layer disposed between the first and second electrodes. Select individual capacitors are energized so as to blow the dielectric layer to establish a connection between the first and second electrodes such that, after blowing the dielectric layer, the second electrode is coupled to a cell plate generator establish a bias connection therebetween. Cell plate bias connection methods are also described.

Abstract: The present invention relates to a high voltage switch used with a one-time programmable memory device and a method of setting a state of a one-time programmable memory device using such a high voltage switch. The memory device includes a plurality of one time programmable memory cells arranged in an array and adapted to be programmed using a high voltage, wherein each of the memory cells includes at least one storage element and two gated fuses connected to the storage element. A high voltage switch is connected to at least one of the memory cells and is adapted to switch in a high voltage.

Abstract: Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

Abstract: The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material.

Abstract: Phase change memory devices include a phase-change memory layer on a semiconductor substrate. The phase-change memory layer has a major axis that is substantially parallel to a major axis of the semiconductor substrate and has a first surface and a second surface opposite the first surface that are substantially parallel to the major axis of the phase-change memory layer. A first electrode is provided on the semiconductor substrate that is electrically connected to the first surface of the phase-change memory layer in a first contact region of the phase-change memory layer. A second electrode is provided on the semiconductor substrate that is electrically connected to the phase-change memory layer in a second contact region of the phase-change memory layer. The second contact region is space apart from the first contact region.

Abstract: An interconnect structure in which a patterned anti-fuse material is formed therein comprising: a substrate having a first level of electrically conductive features; a patterned anti-fuse material formed on said substrate, wherein said patterned anti-fuse material includes an opening to at least one of said first level of electrically conductive features; a patterned interlevel dielectric material formed on said patterned anti-fuse material, wherein said patterned interlevel dielectric includes vias, as least one of said vias includes a via space; and a second level of electrically conductive features formed in said vias and via spaces.

Abstract: The present invention discloses a circuit having a make-link type fuse. The circuit comprising a first make-link type fuse connected between a gate of a transistor and a first supply voltage.

Abstract: Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.

Abstract: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

Abstract: A method of forming an integrated circuit device can include forming a plurality of fuse wires on an integrated circuit substrate, and forming an insulating layer on the integrated circuit substrate and on the plurality of fuse wires so that the fuse wires are between the integrated circuit substrate and the insulating layer. A plurality of fuse cutting holes can be formed in the insulating layer wherein each of the fuse cutting holes exposes a target spot on a respective one of the fuse wires, and a cross-sectional area of the fuse wires can be reduced at the exposed target spots. Related structures are also discussed.

Abstract: A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are arranged at a pitch X, and an insulation layer 36 having a specified film thickness covers upper portions of the fuses 20. The fuses 20 may have a width W and a film thickness T that have a relation indicated by the following equation: T?0.4/W. Furthermore, the width W of the fuse 20 may be 3 ?m or less, and may be less than ½ of the pitch X of the fuses 20. Also, the film thickness of the fuse 20 may be 0.7 ?m or less.

Abstract: The anti-fuse comprises a substitutable layer 14, an interconnection layer 20 connected to the substitutable layer, and the interconnection layer contains metal atoms which can be substituted with constituent atoms of the substitutable layer. The anti-fuse can be changed from the non-conduction state to the conduction state at a relatively low temperature of 300° C. to 600° C., and by application of not so intense laser beams, the anti-fuse can be changed from the non-conduction state to the conduction state. The anti-fuse can be changed from the non-conduction state to the conduction state by using an inexpensive equipment, which can realize decrease of fabrication costs and accordingly inexpensive semiconductor devices can be provided.

Abstract: In programmable conductor memory cells, metal ions precipitate out of a glass electrolyte element in response to an applied electric field in one direction only, causing a conductive pathway to grow from cathode to anode. The amount of conductive pathway growth, and therefore the programming, depends, in part, on the availability of metal ions. It is important that the metal ions come only from the solid solution of the memory cell body. If additional metal ions are supplied from other sources, such as the sidewall edge at the anode interface, the amount of metal ions may not be directly related to the strength of the electric field, and the programming will not respond consistently from cell to cell. The embodiments described herein provide new and novel structures that block interface diffusion paths for metal ions, leaving diffusion from the bulk glass electrolyte as the only supply of metal ions for conductive pathway formation.

Abstract: A typical integrated circuit includes millions of microscopic transistors, resistors, and other components interconnected to define a circuit, for example a memory circuit. Occasionally, one or more of the components are defective and fabricators selectively replace them by activating spare, or redundant, components included within the circuit. One way of activating a redundant component is to rupture an antifuse that effectively connects the redundant component into the circuit. Unfortunately, conventional antifuses have high and/or unstable electrical resistances which compromise circuit performance and discourage their use. Accordingly, the inventors devised an exemplary antifuse structure that includes three normally disconnected conductive elements and a programming mechanism for selectively moving one of the elements to electrically connect the other two.

Abstract: A laser link structure used in semiconductor devices and a fuse box using the laser link structure preferably include a plurality of first conductive line patterns positioned in parallel at predetermined intervals, and a second conductive line pattern broadly formed on the plurality of first conductive line patterns for forming hole regions which link the second conductive line pattern to the plurality of first conductive line patterns. Preferably, at least one hole region is formed on each of the plurality of first conductive line patterns, and via holes are formed in the hole regions.

Abstract: A memory system, including a first electrode, a memory storage element, and a control element. The control element having a breakdown voltage. The breakdown voltage is increased by partially-processing the control element. In one aspect, the partial-processing results by processing the control element for a briefer duration than the memory storage element. In another aspect, the partial-processing results by forming the control element from a plurality of layers, some of the plurality of layers are unprocessed while other ones of the plurality of layers are fully processed.

Abstract: Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cell both using a single nanotube to form the individual devices.

Abstract: The present invention provides a fuse structure. The fuse structure comprises a substrate, a plurality of conductive layers, a plurality of dielectric layers and a plurality of conductive plugs. The novel fuse structure includes a plurality of fuse units, and a new layout of the fuse units to increase the pitch between the fuse units, preventing the fuse structure from failing when misalignment of the laser beam and thermal scattering of the laser beam damage the second layer of the fuse structure in the laser blow process, thus increasing reliability and yield.

Abstract: A semiconductor memory device comprises memory cells in rows and columns. Each memory is of the capacitor type and includes one portion of a dielectric layer. Antifuse-components are connected in series one after another between a power source electrode and an output terminal that is grounded when a MOS transistor is conductive.

Abstract: A microelectronic 3-dimensional solenoid of substantially circular or oval cross-section and a method for fabricating the solenoid. The solenoid is provided including a pre-processed semiconductor substrate, two supports upstanding from and spaced-apart on a top surface of the substrate, each support has a bottom end attached to the substrate. An inductor coil which has two spaced-apart ends each attached to one of two top ends of the two supports. The inductor coil is formed of a bi-layer metal laminate that has an inner metal layer and an outer metal layer. The outer metal layer is formed of a first metal that has a coefficient of thermal expansion larger than a coefficient of thermal expansion of a second metal that forms the inner metal layer.

Abstract: An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.

Abstract: A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

Abstract: The present invention comprises an antifuse having a hemispherical grained (HSG) layer and a method of forming antifuse having a hemispherical grained (HSG) layer. The antifuse of the present invention comprises a plurality of layers, the first being a lower electrode that is disposed on an impurity region in a semiconductor substrate. A dielectric layer is disposed on the lower electrode, wherein the dielectric layer has a planar surface. A non-conductive hemispherical grain (HSG) layer is formed on the planar surface of the dielectric layer and an upper electrode is disposed on said non-conductive hemispherical grain (HSG) layer forming the antifuse.

Abstract: An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programming voltage is coupled to a conductive terminal of the second conductivity type in the antifuse to create a current path through an insulator between the conductive terminal and the well to program the antifuse. The first programming voltage may be coupled to an ohmic contact in the well in the antifuse.

Abstract: The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material.

Abstract: A fuse structure (30) formed in a semiconductor device is provided. The fuse structure (30) includes a layer of fuse material (32), a first contact (40), and a second contact (42). The first contact (40) has a first edge (54). At least a portion of the first edge (54) abuts the fuse material layer (32). The second contact (42) has a second edge (55). At least a portion of the second edge (55) abuts the fuse material layer (32). The first edge (54) faces the second edge (55). The first edge (54) is separated from the second edge (55) by a spaced distance (58). A conductive portion of the fuse material layer (32) electrically connects between the first edge (54) and the second edge (55) within the spaced distance (58). The abutting portion of the first edge (54) has a first length. The abutting portion of the second edge (55) has a second length. The first length is greater than the second length.

Abstract: Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.

Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

Abstract: A semiconductor integrated circuit according to the invention includes a wiring member formed on a main face of a semiconductor substrate, a fusing member connected to the wiring member and having a predetermined thickness, a barrier member for covering a bottom face and a side face of the fusing member, a light absorbing member for covering at least a side face portion of the barrier member for covering the fusing member, and an insulating member for embedding the wiring member, the fusing member, the barrier member and the light absorbing member. A complex permittivity of the light absorbing member is provided with a real part smaller than that of the fusing member in absolute value and an imaginary part larger than that of the fusing member.

Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

Abstract: A semiconductor device having an increased intersection perimeter between edge regions of a first conductor and portions of a second conductor is disclosed. In one embodiment, the intersection perimeter is the region where the perimeter of a gate structure overlaps an active area. The intersection perimeter between the conductors directs the breakdown of the dielectric material, increasing the likelihood that the programming event will be successful. In at least one embodiment, the portion of a current path that travels through a highly doped area is increased while the portion that travels through a non-highly doped area is decreased. This decreases post-program resistance, leading to better response time for the device.