Anti-fuse Patents (Class 257/530)
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Patent number: 8278732Abstract: An antifuse element for an integrated circuit is provided, including a conductive region formed in a semiconductor substrate, extending along a first direction; a dielectric layer formed on a portion of the conductive region; a first conductive plug formed on the dielectric layer; a second conductive plug formed on another portion of the conductive region; and a first conductive member formed over the first and second conductive plugs, extending along a second direction perpendicular to the first direction; and a second conductive member formed over the second conductive plug extending along the second direction, wherein the first conductive member intersects with the conductive region, having a first overlapping area therebetween, and the dielectric layer and the conductive region have a second overlapping area therebetween, and a ratio between the first overlapping area and the second overlapping area is about 1.5:1 to 3:1.Type: GrantFiled: April 28, 2011Date of Patent: October 2, 2012Assignee: Nanya Technology CorporationInventors: Jar-Ming Ho, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8279700Abstract: A semiconductor device includes a first terminal, a second terminal, and a fuse link that connects between the first terminal and the second terminal. The first terminal and the fuse link have a polysilicon layer doped with an impurity ion and a layer containing a metal element laminated on the polysilicon layer. The second terminal has a polysilicon layer not doped with an impurity ion and a layer containing a metal element laminated on the polysilicon layer, in at least a part of an end side connected to the fuse link.Type: GrantFiled: February 18, 2010Date of Patent: October 2, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Wada, Toshimasa Namekawa
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Patent number: 8274132Abstract: An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.Type: GrantFiled: February 14, 2008Date of Patent: September 25, 2012Assignee: Infineon Technologies AGInventors: Christian Russ, Gunther Lehmann, Franz Ungar
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Patent number: 8274130Abstract: A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P?/N+ device or a P+/N?/P+ device.Type: GrantFiled: October 20, 2009Date of Patent: September 25, 2012Assignee: SanDisk 3D LLCInventors: Andrei Mihnea, Deepak C. Sekar, George Samachisa, Roy Scheuerlein, Li Xiao
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Patent number: 8258586Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.Type: GrantFiled: March 11, 2011Date of Patent: September 4, 2012Assignee: Texas Instruments IncorporatedInventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
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Patent number: 8242486Abstract: An object is to provide technology for manufacturing a higher-reliability memory device and a semiconductor device that is equipped with the memory device at low cost. A semiconductor device of the present invention has a first conductive layer, a first insulating layer that is provided to be in contact with a side end portion of the first conductive layer, a second insulating layer that is provided over the first conductive layer and the first insulating layer, and a second conductive layer that is provided over the second insulating layer. The second insulating layer is formed of an insulating material, and wettability against a fluidized substance when the insulating material is fluidized, is higher for the first insulating layer than the first conductive layer.Type: GrantFiled: February 7, 2006Date of Patent: August 14, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Gen Fujii
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Patent number: 8242573Abstract: There are provided a semiconductor device and a method of forming the same. The semiconductor device may include a semiconductor substrate including a digital circuit region and an analog circuit region, a device isolation layer on the boundary between the digital circuit region and the analog circuit region, a conductive region adjacent to the side surface and the bottom surface of the isolation layer, and a ground pad which is electrically connected to the conductive region and to which a ground voltage is applied.Type: GrantFiled: January 8, 2008Date of Patent: August 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Han-Su Kim, Jin-Sung Lim
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Patent number: 8242578Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.Type: GrantFiled: March 25, 2011Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Toshiharu Furukawa, William R. Tonti
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Publication number: 20120199943Abstract: An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region.Type: ApplicationFiled: April 16, 2012Publication date: August 9, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Sumio OGAWA
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Patent number: 8237241Abstract: A conventional semiconductor device has a problem that an on-current of a parasitic transistor flows through a surface portion of a semiconductor layer and thus a semiconductor element undergoes thermal breakdown. In a semiconductor device according to the present invention, a protection element is formed with use of an isolation region and N type buried layers. A PN junction region in the protection element is formed on a P type buried layer of the isolation region. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of a semiconductor element to be protected. This structure allows an on-current of a parasitic transistor to flow into the protection element, and thereby the semiconductor element is protected. In addition, the on-current of the parasitic transistor flows through a deep portion of the epitaxial layer, and thereby the protection element is prevented from thermal breakdown.Type: GrantFiled: January 22, 2010Date of Patent: August 7, 2012Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventor: Seiji Otake
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Patent number: 8237457Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).Type: GrantFiled: July 15, 2009Date of Patent: August 7, 2012Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc.Inventors: Satya N. Chakravarti, Dechao Guo, Chuck T. Le, Byoung W. Min, Thekkemadathil V. Rajeevakumar, Keith Kwong Hon Wong
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Patent number: 8232146Abstract: A fuse element is laminated on a resistor and the resistor is formed in a concave shape below a region in which cutting of the fuse element is carried out with a laser. Accordingly, there can be provided a semiconductor device which occupies a small area, causes no damage on the resistor in the cutting of the fuse element, has a small contact resistance occurred between elements, and has stable characteristics, and a method of manufacturing the same.Type: GrantFiled: October 27, 2010Date of Patent: July 31, 2012Assignee: Seiko Intruments Inc.Inventor: Yuichiro Kitajima
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Patent number: 8227890Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: GrantFiled: December 18, 2009Date of Patent: July 24, 2012Assignee: United Microelectronics CorporationInventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
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Patent number: 8203154Abstract: A device (10) comprises a semiconductor diode (12) and a switchable element (14) positioned in stacked adjacent relationship. The semiconductor diode (12) and the switchable element (14) are electrically connected in series with one another. The switchable element (14) is switchable from a low-conductance state to a high-conductance state in response to the application of a low-density forming current and/or a low voltage.Type: GrantFiled: May 8, 2003Date of Patent: June 19, 2012Assignee: Alliance for Sustainable Energy, LLCInventors: Qi Wang, James Scott Ward, Jian Hu, Howard M. Branz
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Patent number: 8198702Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.Type: GrantFiled: July 29, 2011Date of Patent: June 12, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-suk Shin, Andrew-Tae Kim, Hong-jae Shin
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Publication number: 20120126365Abstract: An anti-fuse element that includes an insulation layer; a pair of electrode layers formed on upper and lower surfaces of the insulation layer; and an extraction electrode contacting a section of the electrode layers forming electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section that includes a short circuit section short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by the engulfing of the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. The maximum diameter of a section of the extraction electrode in contact with the electrode layer is larger than the maximum diameter of the structural change section.Type: ApplicationFiled: January 19, 2012Publication date: May 24, 2012Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Shinsuke Tani, Toshiyuki Nakaiso
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Publication number: 20120126367Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Publication number: 20120126366Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 8183665Abstract: A high-density memory array. A plurality of word lines and a plurality of bit lines are arranged to access a plurality of memory cells. Each memory cell includes a first conductive terminal and an article in physical and electrical contact with the first conductive terminal, the article comprising a plurality of nanoscopic particles. A second conductive terminal is in physical and electrical contact with the article. Select circuitry is arranged in electrical communication with a bit line of the plurality of bit lines and one of the first and second conductive terminals. The article has a physical dimension that defines a spacing between the first and second conductive terminals such that the nanotube article is interposed between the first and second conducive terminals. A logical state of each memory cell is selectable by activation only of the bit line and the word line connected to that memory cell.Type: GrantFiled: November 19, 2008Date of Patent: May 22, 2012Assignee: Nantero Inc.Inventors: Claude L. Bertin, Eliodor G. Ghenciu, Thomas Rueckes, H. Montgomery Manning
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Patent number: 8178906Abstract: A laser activated phase change device for use in an integrated circuit comprises a chalcogenide fuse configured to connect a first patterned metal line and a second patterned metal line and positioned between an inter layer dielectric and an over fuse dielectric. The fuse interconnects active semiconductor elements manufactured on a substrate. A method for activating the laser activated phase change device includes selecting a laser condition of a laser based on characteristics of the fuse and programming a phase-change of the fuse with the laser by direct photon absorption until a threshold transition temperature is met.Type: GrantFiled: January 11, 2008Date of Patent: May 15, 2012Assignee: Electro Scientific Industries, Inc.Inventors: Andy E. Hooper, Allen Kawasaki, Robert Hainsey
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Patent number: 8178945Abstract: Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p? substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p? substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.Type: GrantFiled: February 2, 2010Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Ping-Chuan Wang, Robert C. Wong, Haining S. Yang
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Patent number: 8179709Abstract: An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region.Type: GrantFiled: August 22, 2008Date of Patent: May 15, 2012Assignee: Elpida Memory, Inc.Inventor: Sumio Ogawa
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Publication number: 20120112312Abstract: An integrated circuit, a method for making an integrated circuit product, and methods for customizing an integrated circuit are disclosed. Integrated circuit elements including programmable elements, such as fuses, PROMs, RRAMs, MRAMs, or the like, are formed on the frontside of a substrate. Vias are formed through the substrate from its frontside to its backside to establish conduction paths to at least some of the programmable elements from the backside. A programming stimulus is applied to at least some of the vias from the backside to program at least some of the frontside programmable elements.Type: ApplicationFiled: November 4, 2010Publication date: May 10, 2012Applicant: QUALCOMM IncorporatedInventors: Daniel W. Perry, Shiqun Gu
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Publication number: 20120112313Abstract: An anti-fuse element that includes an insulation layer; a pair of electrode layers on the upper and lower surfaces of the insulation layer; and an extraction electrode formed so as to make contact with a section of the electrode layers that form electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section including short circuit sections that are short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by engulfing the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. Furthermore, the extraction electrode has at least two or more sections in contact with the electrode layer.Type: ApplicationFiled: January 20, 2012Publication date: May 10, 2012Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Shinsuke Tani, Toshiyuki Nakaiso
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Patent number: 8174091Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.Type: GrantFiled: July 15, 2009Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kong-Beng Thei, Chung Long Cheng, Chung-Shi Liu, Harry Chuang, Shien-Yang Wu, Shi-Bai Chen
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Publication number: 20120104544Abstract: A semiconductor device adapted such that written information cannot be analyzed even by using a method of analyzing the presence or absence of electric charge, accumulated on a gate electrode, in which a substrate is a first conduction type, for example, p-type semiconductor substrate (for example, silicon substrate), an antifuse has a gate electrode and a second conduction type diffusion layer, the second conduction type diffusion layer is formed in the substrate and has, for example, an n-conduction type, a first contact is connected to the gate electrode, second contacts are formed in a layer identical with the first contact and connected to a region of the substrate in which the second conduction type diffusion layer is not formed, and the second contact is adjacent to the first contact.Type: ApplicationFiled: October 17, 2011Publication date: May 3, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Yoshitaka KUBOTA
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Publication number: 20120104545Abstract: An anti-fuse element that includes a capacitance unit having an insulation layer and at least a pair of electrode layers formed on upper and lower surfaces of the insulation layer. The capacitance unit has a protection function against electrostatic discharge. Because the capacitance unit has a protection function against electrostatic discharge, an anti-fuse element can be provided which is less likely to cause insulation breakdown due to electrostatic discharge at the time of, for example, mounting a component.Type: ApplicationFiled: January 6, 2012Publication date: May 3, 2012Inventors: Yutaka Takeshima, Toshiyuki Nakaiso, Shinsuke Tani
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Patent number: 8163593Abstract: A method is described to form a nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits. A conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.Type: GrantFiled: November 16, 2006Date of Patent: April 24, 2012Assignee: SanDisk CorporationInventors: Usha Raghuram, S. Brad Herner
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Publication number: 20120091557Abstract: An anti-fuse of a semiconductor device and a method for manufacturing the same are disclosed. In order to achieve stable operation of the anti-fuse, a gate rupture prevention film is formed between a gate pattern and a source/drain junction region and a gate oxide film is formed at both ends of a lower edge of the gate pattern. Therefore, when applying a voltage, the overlapped gate oxide film is ruptured so that a current level is stabilized and the anti-fuse is stably operated.Type: ApplicationFiled: October 14, 2011Publication date: April 19, 2012Applicant: Hynix Semiconductor Inc.Inventor: Jin Hwan LEE
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Patent number: 8159040Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.Type: GrantFiled: May 13, 2008Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Ephrem G. Gebreselasie, Zhong-Xiang He, Herbert Lei Ho, Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Robert Mark Rassel, John Matthew Safran, Kenneth Jay Stein, Norman Whitelaw Robson, Ping-Chuan Wang, Hongwen Yan
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Patent number: 8159042Abstract: An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.Type: GrantFiled: June 23, 2008Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Lawrence A. Clevenger, Timothy J. Dalton, Nicholas C. Fuller, Louis C. Hsu
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Patent number: 8143692Abstract: A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The plurality of fuses may be arranged to correspond to the plurality of capacitor layers, and/or the plurality of fuses may be configured to select corresponding ones of the plurality of capacitor layers for controlling a capacitance of the plurality of capacitor layers.Type: GrantFiled: February 27, 2008Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung-jun Jang, Tae-soo Park
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Publication number: 20120061797Abstract: According to one embodiment, a semiconductor device including a substrate, and an anti-fuse element including a first insulator formed on the substrate, a conductive film formed on the first insulator, the conductive film including a silicide film, a contact formed on the substrate, the contact being disposed adjacent to the conductive film with a second insulator interposed between the contact and the conductive film, the contact being short-circuited to the silicide film.Type: ApplicationFiled: March 7, 2011Publication date: March 15, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Masahiko Kanda
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Publication number: 20120061796Abstract: A mechanically programmable anti-fuse is configured in a thick, top metallic layer of a semiconductor. The metallic layer is selected of a material that possesses malleable properties. The metal anti-fuse programming pad is surrounded, either wholly or in part, by a pad segment. An intervening space between the anti-fuse pad and the pad segment is selected from a predetermined value such that capillary pressure, exerted when a ball-bond is placed atop the anti-fuse pad and the pad segment, causes the pads to deform and shorts to the anti-fuse pad to the pad segment. The shorting, created during the wire bonding process, programs the anti-fuse.Type: ApplicationFiled: September 14, 2010Publication date: March 15, 2012Inventor: James Jen-Ho Wang
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Patent number: 8134220Abstract: Nanotube switching devices having nanotube bridges are disclosed. Two-terminal nanotube switches include conductive terminals extending up from a substrate and defining a void in the substrate. Nantoube articles are suspended over the void or form a bottom surface of a void. The nanotube articles are arranged to permanently contact at least a portion of the conductive terminals. An electrical stimulus circuit in communication with the conductive terminals is used to generate and apply selected waveforms to induce a change in resistance of the device between relatively high and low resistance values. Relatively high and relatively low resistance values correspond to states of the device. A single conductive terminal and a interconnect line may be used. The nanotube article may comprise a patterned region of nanotube fabric, having an active region with a relatively high or relatively low resistance value. Methods of making each device are disclosed.Type: GrantFiled: June 16, 2008Date of Patent: March 13, 2012Assignee: Nantero Inc.Inventors: H. Montgomery Manning, Thomas Rueckes, Jonathan W. Ward, Brent M. Segal
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Patent number: 8125048Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: October 7, 2009Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 8124971Abstract: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.Type: GrantFiled: March 30, 2007Date of Patent: February 28, 2012Assignee: SanDisk 3D LLCInventor: Yoichiro Tanaka
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Patent number: 8120180Abstract: A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug fainted on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.Type: GrantFiled: July 16, 2010Date of Patent: February 21, 2012Assignee: Hynix Semiconductor Inc.Inventors: Jin-Hyock Kim, Jae-Sung Roh, Seung-Jin Yeom, Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim
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Patent number: 8115275Abstract: An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.Type: GrantFiled: September 8, 2009Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: Alberto Cestero, Byeongju Park, John M. Safran
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Patent number: 8110893Abstract: A fuse element utilizing a reaction between two layers by feeding current is manufactured. A fuse element including a first layer formed of an oxide or a nitride and a second layer that becomes high resistant by nitridation or oxidation, in which the first layer and the second layer are in contact with each other, is manufactured. For example, the fuse element is manufactured by using indium tin oxide for the first layer and aluminum for the second layer. By generating joule heat by applying voltage to the first layer and the second layer, oxygen in the indium tin oxide enters the aluminum, which changes the aluminum into aluminum oxide that presents an insulating property. The fuse element can be manufactured by a similar process as that of forming a TFT.Type: GrantFiled: July 15, 2010Date of Patent: February 7, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kengo Akimoto
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Publication number: 20120018841Abstract: A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region.Type: ApplicationFiled: October 3, 2011Publication date: January 26, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Eiji KITAMURA, Shinichi HORIBA, Nobuyuki NAKAMURA
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Patent number: 8101977Abstract: A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.Type: GrantFiled: December 21, 2007Date of Patent: January 24, 2012Assignee: Intersil CorporationInventor: Michael David Church
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Patent number: 8102023Abstract: A capacitor insulating film for use as an insulating film sandwiched between two electrodes is made of a crystal containing a hafnium element in a titanium site in place of a part of titanium elements contained in a crystal of a strontium titanate or barium strontium titanate.Type: GrantFiled: January 11, 2010Date of Patent: January 24, 2012Assignee: Elpida Memory, Inc.Inventor: Masami Tanioku
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Patent number: 8101938Abstract: A method of fabricating a chalcogenide memory cell is described. The cross-sectional area of a chalcogenide memory element within the cell is controlled by the thickness of a bottom electrode and the width of a word line. The method allows the formation of ultra small chalcogenide memory cells.Type: GrantFiled: September 20, 2007Date of Patent: January 24, 2012Assignee: Macronix International Co., Ltd.Inventor: Hsiang-Lan Lung
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Publication number: 20120012977Abstract: An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region.Type: ApplicationFiled: July 14, 2010Publication date: January 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
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Patent number: 8097931Abstract: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.Type: GrantFiled: December 24, 2008Date of Patent: January 17, 2012Assignee: Hynix Semiconductor Inc.Inventor: Byung-Duk Lee
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Publication number: 20120001296Abstract: A vertically oriented p-i-n diode is provided that includes semiconductor material crystallized adjacent a silicide, germanide, or silicide-germanide layer, and a dielectric material arranged electrically in series with the diode. The dielectric material has a dielectric constant greater than 8, and is adjacent a first metallic layer and a second metallic layer. Numerous other aspects are provided.Type: ApplicationFiled: September 11, 2011Publication date: January 5, 2012Inventor: S. Brad Herner
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Patent number: 8084830Abstract: The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si1-xGex (0<x<=1)). The second semiconductor region is formed of silicon (Si).Type: GrantFiled: September 9, 2009Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Kanno, Kenichi Murooka, Jun Hirota, Hideyuki Tabata
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Publication number: 20110309472Abstract: An anti-fuse element that includes first and second electrode films on both of upper and lower surfaces of a dielectric film to form an element body. When an operation voltage is applied to the element body, the first and second electrode films are fused by heat generation by electrification, whereby balled portions are formed, and a crack also occurs in the dielectric film. Then, the balled portions are enlarged, the dielectric film is completely divided, and the first and second electrode films are welded and integrated with each other in a mode of tangling end portions of the dielectric film, and form bonded portions that turn the anti-fuse element into a conducting state.Type: ApplicationFiled: August 26, 2011Publication date: December 22, 2011Inventors: Toshiyuki Nakaiso, Yutaka Takeshima
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Publication number: 20110309421Abstract: A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Inventors: Harry S. Luan, Yue-Song He, Ting-Wah Wong