Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.

Abstract: A semiconductor module parallel circuit includes: a plurality of power semiconductor modules; and a multilayer substrate that interconnects the plurality of power semiconductor modules, each of the power semiconductor modules includes: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, the multilayer substrate includes: an external connection terminal; first signal terminal connection patterns connected to the first signal terminals of the power semiconductor modules; and second signal terminal connection patterns connected to the second signal terminals of the power semiconductor modules, and inductances of gate wiring for the plurality of power semiconductor modules, from the external connection terminal to the first signal terminal connection pattern and from the second signal terminal connection pattern to the e

Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

Abstract: A semiconductor device has a substrate and a first semiconductor layer with a high resistivity, such as an epitaxial layer with a resistivity in the range of 3000-5000 ohms/cm2, formed over the substrate. A second semiconductor layer is formed at least partially in the first semiconductor layer. A capacitor is formed at least partially over the first semiconductor layer. The capacitor has a plurality of trenches extending through the first semiconductor layer and into the substrate, and a first insulating layer formed in the trench. The trenches can be parallel, serpentine, or other geometric shape. The capacitor also has a second insulating layer formed over the first insulating layer, and a polysilicon layer formed over the second insulating layer. A conductive layer is formed over the capacitor. The first semiconductor layer with high resistivity provides a vertical path to discharge high voltage events incident on the capacitor.

Abstract: A display apparatus includes a plurality of pixels each including a substrate on which are disposed: an interlayer insulating layer; a driving thin film transistor in which a driving semiconductor layer and a driving gate electrode are each disposed between the substrate and the first interlayer insulating layer; a first capacitor in which a first electrode, a first dielectric pattern and a second electrode are sequentially stacked, the first electrode being connected to the driving gate electrode; and a plurality of contact plugs extended through a thickness of the interlayer insulating layer, with which the driving thin film transistor and the first capacitor are respectively connected to electrodes outside thereof. Lateral surfaces of the first dielectric pattern are covered by the interlayer insulating layer, and the first dielectric pattern within the first capacitor is disposed spaced apart from each of the contact plugs.

Abstract: In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region. At least a majority of channel material of the dummy channel-material strings is replaced in the TAV region with insulator material and operative TAVs are formed in the TAV region. Other methods and structures independent of method are disclosed.

Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.

Abstract: A display device includes a plurality of pixels arranged in a matrix on a substrate along a first direction and a second direction intersecting the first direction. Each of the plurality of pixels includes a transistor, a first transparent electrode located over the transistor and electrically connected to the transistor, a second transparent electrode located over the first transparent electrode and electrically connected to the first transparent electrode via an opening, an insulating layer located over the second transparent electrode, a third transparent electrode located over the insulating layer; and a metal layer in contact with the third transparent electrode. The opening overlaps a gate electrode of the transistor. At least a part of the metal layer is provided in the opening and overlaps the gate electrode. The metal layer extends along the first direction and is commonly provided in the pixels arranged in the first direction.

Abstract: The present disclosure provides a method of manufacturing a capacitor connecting line of a memory and a memory. The method of manufacturing includes: forming a bit line layer and a first dielectric layer on a substrate sequentially; patterning the bit line layer and the first dielectric layer, and forming bit line structures arranged at intervals along a first direction and dielectric structures on tops of the bit line structures; forming an insulating layer on the substrate with the bit line structures and the dielectric structures formed thereon, to completely cover the bit line structures and the dielectric structures; forming second isolation structures arranged at intervals between adjacent bit line structures; and forming conductive structures between first isolation structures and the second isolation structures, and forming storage node contact structures.

Abstract: A multi-die package structure with an embedded die embedded in a substrate, a flip chip die mounted above the substrate, and an attached die attached onto the flip chip die. The package is compact and low cost.

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

Abstract: A semiconductor structure includes a first substrate having a wiring structure, a first semiconductor die disposed on the first substrate, and a multi-terminal capacitor structure disposed on the first substrate. The multi-terminal capacitor includes a second substrate, an insulating layer disposed over the second substrate, a first multi-terminal capacitor disposed over the insulating layer and electrically coupled to the first semiconductor die through the wiring structure, and a second multi-terminal capacitor disposed over the insulating layer and electrically coupled to the second semiconductor die through the wiring structure, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are electrically isolated from the second substrate.

Abstract: A device including a first structure and a second structure is provided.

Abstract: A semiconductor device includes; an active region extending in a first horizontal direction on a substrate, source/drain regions disposed on the active region, a buried trench formed between the source/drain regions, a buried insulating layer surrounding both side walls of the buried trench in the first horizontal direction between the source/drain regions, a wing trench formed in a lower part of the buried trench and having a width greater than a width of the buried trench, and a gate electrode extending in a second horizontal direction on the active region, and disposed within each of the buried trench and the wing trench.

Abstract: A semiconductor device includes an n? type layer on a first surface of the substrate, a p type region on a part of the n? type layer, a gate on the n? type layer and the p type region, a first gate protection layer on the gate and a second gate protection layer on the first gate protection layer, a source on the second gate protection layer and the p type region, and a drain on the second surface of the substrate.

Abstract: A device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. The second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. The device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.

Abstract: A display apparatus includes a display panel, a gate driver, a data driver and an emission driver. The display panel includes a pixel. The gate driver provides a gate signal to the pixel. The data driver provides a data voltage to the pixel. The emission driver provides an emission signal to the pixel. The pixel includes a light emitting element, a driving switching element which applies a driving current to the light emitting element, a storage capacitor connected to a control electrode of the driving switching element and a bias capacitor including a first electrode connected to the storage capacitor and a second electrode which receives a bias gate signal. A waveform of the bias gate signal varies based on an off ratio representing a ratio of an off period of the emission signal in a frame period.

Abstract: A charge trapping non-volatile organic memory device according to the present invention has a structure in which an organic matter-based blocking layer, a trapping layer, and a tunneling layer are sequentially positioned between a gate and an organic semiconductor layer positioned on an insulating substrate, the trapping layer including a metal oxide and a polymer, and has an organic-inorganic composite film in which the metal oxide is dispersed in a polymer matrix in units of atoms.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Abstract: A capacitor component includes a body having first surface and second surfaces opposing each other and including through-holes penetrating through the first surface and the second surface, a first electrode covering an inner wall of each of the plurality of through-holes, a first common electrode covering the first surface and connected to the first electrode, a dielectric layer surrounded by the first electrode in the through-hole, a second electrode surrounded by the dielectric layer in the through-hole, a second common electrode layer covering the second surface and connected to the second electrode, a first external electrode disposed on at least one of a plurality of side surfaces of the body and connected to the first common electrode layer, and a second external electrode disposed on at least one of the plurality of side surfaces of the body and connected to the second common electrode layer.

Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first semiconductor layer, a cell stack and a peripheral stack each disposed on the first semiconductor layer, a first slit structure extending in a first direction and penetrating the cell stack and the peripheral stack, a penetration structure penetrating the peripheral stack and being spaced apart from the first slit structure, and a support structure penetrating the peripheral stack. The support structure includes first sidewall portions spaced apart from each other and a second sidewall portion connecting the first sidewall portions to each other, and the penetration structure is disposed between the first sidewall portions.

Abstract: A substrate treating apparatus and a substrate treating method are provided. The substrate treating apparatus includes a first process chamber to apply an organic solvent to a substrate applied with a developer and introduced, and a second process chamber to treat the substrate applied with the organic solvent and introduced, through a supercritical fluid.

Abstract: Embodiments of the present application provide a semiconductor structure and its formation method. The method includes: the substrate being provided with a groove, a sidewall of the groove including a first sub-sidewall and a second sub-sidewall that extend upwards from a bottom of the groove sub-sidewall; blowing a first precursor to a surface of the substrate, so that the first precursor is attached to a top surface of the substrate and the second sub-sidewall; blowing a second precursor to the surface of the substrate, so that the second precursor reacts with the first precursor to form a dielectric layer; alternately blowing the first precursor and the second precursor to the surface of the substrate to form a plurality of dielectric layers until a top opening of the groove is blocked, a region enclosed by the first sub-sidewall, the dielectric layer and the bottom of the groove forming a void.

Abstract: A displaying base plate and a fabricating method thereof. The displaying base plate includes a substrate, and a first flat layer on one side of the substrate; a first metal layer on one side of the first flat layer that is further away from the substrate; a second flat layer on sides of the first metal layer and the first flat layer that are further away from the substrate; and a second metal layer on one side of the second flat layer that is further away from the substrate; wherein the first metal layer includes a first metal trace, an orthographic projection of the second metal layer on the substrate and an orthographic projection of the first metal trace on the substrate have an overlapping part, and an orthographic projection of the second flat layer on the substrate covers the orthographic projection of the first metal trace on the substrate.

Abstract: A semiconductor device includes: a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate; a first insulating plate disposed over the first conductive plate and the second conductive plate; a third conductive plate disposed over the first insulating plate; a second insulating plate disposed over the third conductive plate; a fourth conductive plate disposed over the second insulating plate; a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate, wherein the first conductive via is electrically coupled to the fourth conductive plate and the first conductive plate; and a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate, wherein the second conductive via is electrically coupled to the third conductive plate and the second conductive plate.

Abstract: There is provided a display substrate and a display device. The display substrate includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer which are stacked; wherein the metal oxide layer comprises a first pattern, a second pattern and a capacitance pattern, the first metal layer comprises a first electrode plate, there is at least a first overlapping region between the first electrode plate and the capacitance pattern to form a first storage capacitor, the second metal layer comprises a second electrode plate, there is at least a second overlapping region between the second electrode plate on the base substrate and the capacitance pattern to form a second storage capacitor, and the first electrode plate and the second electrode plate have same potential.

Abstract: A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.

Abstract: Provided is a semiconductor storage device that includes a substrate, a first storage element formed on the substrate and including a first insulating film, and a second storage element formed on the substrate and including a second insulating film having a film thickness of equal to or greater than 0.5 times and equal to or less than 2 times a film thickness of the first insulating film, the second storage element differing from the first storage element in power consumption at a time of writing.

Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.

Abstract: According to one embodiment, a device includes: a circuit on a first surface of a substrate and including a first contact; an aluminum oxide layer above the substrate in a first direction perpendicular to the first surface; a cell including a capacitor provided in the aluminum oxide layer; a first conductive layer provided between the substrate and the aluminum oxide layer in the first direction and connected to the cell; a first insulating layer between the first conductive layer and the substrate in the first direction; a second insulating layer adjacent to the aluminum oxide layer in a second direction parallel to the first surface and provided above the substrate in the first direction; and a second contact in the second insulating layer and above the first contact in the first direction to connect the cell to the first contact.

Abstract: According to various embodiments, a semiconductor memory device includes a substrate that includes a memory cell region and a test region. The semiconductor memory device further includes an active pattern on the memory cell region, a source/drain pattern on the active pattern, a dummy pattern on the test region, a first gate electrode on the dummy pattern, a first common contact, and a first wiring layer. The first wiring layer includes a first test line electrically connected to the first common contact. The first common contact includes a first contact pattern in contact with the dummy pattern, and a first gate contact connected to the first gate electrode. The first gate contact includes a body and a protrusion part. A lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern.

Abstract: A capacitor structure includes at least one first layer and at least one second layer that are alternately stacked. The at least one first layer includes first electrodes and second electrodes alternately arranged in a first direction, and the at least one second layer includes third electrodes and fourth electrodes alternately arranged in a second direction intersecting the first direction, the third electrodes and the fourth electrodes being electrically connected to the first electrodes and the second electrodes. Each of the first electrodes and the second electrodes includes a base portion and branch portions protruding from the base portion, and the third electrodes and the fourth electrodes are arranged side by side to correspond to the branch portions.

Abstract: A composite capacitor that includes a first capacitor and a second capacitor. Each of plural first columnar conductors and each of plural second columnar conductors have a nano-size outer diameter. The composite capacitor includes a connecting conductor layer and a reinforcement conductor. The reinforcement conductor is located between a first counter electrode layer and a second counter electrode layer of the first capacitor and the second capacitor, respectively, and is connected to each of the first counter electrode layer, the second counter electrode layer, and the connecting conductor layer. The material forming the reinforcement conductor is the same as each of the first counter electrode layer and the second counter electrode layer and is different from the material forming the connecting conductor layer.

Abstract: Integrated circuits (ICs), including capacitors and inductors, employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related fabrication methods. By directly coupled, it is meant that there is not an intermediate vertical interconnect access (via) layer with a via(s) interconnecting the metal lines in vertically-adjacent interconnect layers. An overlying and underlying metal line in respective and vertically-adjacent overlying and underlying interconnect layers are directly coupled to each other without the need for an intermediate via layer. For example, directly coupled metal in adjacent interconnect layers of IC can reduce contact resistance between the metal lines and reduce the overall height of the IC.

Abstract: Provided is a thin film capacitor comprising a capacitance portion in which at least one dielectric layer is sandwiched between a pair of electrode layers included in a plurality of electrode layers, wherein the capacitance portion has an opening which extends in a lamination direction in which the plurality of electrode layers and the dielectric layer are laminated and through which one electrode layer of the plurality of electrode layers is exposed, the one electrode layer has an exposed portion exposed at a bottom surface of the opening, the exposed portion is in contact with a wiring layer connecting the one electrode layer and an electrode terminal, and a thickness of the exposed portion of the one electrode layer is smaller than a thickness of other portions of the one electrode layer and is 50% or more of the thickness of the other portions of the one electrode layer.

Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.

Abstract: A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.

Abstract: A package structure includes a first thermal dissipation structure, a first semiconductor die, a second semiconductor die. The first thermal dissipation structure includes a semiconductor substrate, conductive vias embedded in the semiconductor substrate, first capacitors electrically connected to the conductive vias, and a thermal transmission structure disposed over the semiconductor substrate and the conductive vias. The first semiconductor die is disposed on the first thermal dissipation structure. The second semiconductor die is disposed on the first semiconductor die opposite to the first thermal dissipation structure.

Abstract: A method of manufacturing a silicon carbide semiconductor device, including forming a first-conductivity-type region in a SiC semiconductor substrate, selectively forming a plurality of second-conductivity-type regions in the first-conductivity-type region, forming an interlayer insulating film covering the first-conductivity-type region and the second-conductivity-type regions, selectively removing the interlayer insulating film to form a plurality of openings exposing the second-conductivity-type regions, forming, in each opening, a layered metal film having a cap film stacked on an aluminum film, thermally diffusing aluminum atoms in the aluminum film to thereby form a plurality of second-conductivity-type high-concentration regions, removing the layered metal film, selectively removing the interlayer insulating film to form a contact hole, forming a first electrode by sequentially stacking a titanium film and a metal film containing aluminum on the first surface of the semiconductor substrate in the conta

Abstract: An apparatus includes a controller a current mode controller that produces an output voltage by supplying output current from at least one power supply phase of a power supply to power a load. The controller produces an error current signal based on a difference between a magnitude of the output current supplied from the power supply to a load and a phase current setpoint. Based on a magnitude of the error current signal, control a pulse width setting of a pulse width modulation signal controlling the at least one power supply phase. The controller varies a leading edge and a falling edge of a pulse width ON-time of the pulse width modulation signal over each of multiple control cycles depending on variations in the magnitude of the pulse width setting.

Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of first metal strips extending in a first direction on a first plane; and forming a plurality of second metal strips extending in the first direction on a second plane over the first plane by executing a photolithography operation with a single mask, wherein a first second metal strip (FIG. 1, 131) is disposed over a first first metal strip; wherein the first first metal strip and the first second metal strip are directed to a first voltage source; wherein a distance between the first second metal strip and a second second metal strip immediate adjacent to the first second metal strip is greater than a distance between the second second metal strip and a third second metal strip immediate adjacent to the second second metal strip.

Abstract: To provide a wiring substrate, an electronic device, and an electronic module the size of which can be easily reduced and the strength of which can be maintained. A wiring substrate includes an insulation substrate and an electrical wiring structure. The insulation substrate includes a recess section in one surface. A frame portion of the insulation substrate that forms a side surface which connects an opened surface and a bottom surface of the recess section to each other includes a first conductive portion having a plate shape in the frame portion.

Abstract: A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer arranged in the vertical direction. A first semiconductor layer includes a plurality of memory cells, and a plurality of metal lines extending in a first direction, and including first bit lines, second bit lines, and a common source line tapping wire between the first bit lines and the second bit lines. A second semiconductor layer includes a page buffer circuit connected to the first bit lines and the second bit lines, and the page buffer circuit includes first transistors arranged below the first bit lines and electrically connected to the first bit lines, second transistors arranged below the second bit lines and electrically connected to the second bit lines, and a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction.

Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.

Abstract: A system on an integrated circuit (IC) chip includes an input terminal and a return terminal, a heater, a thermopile, and a switch device. The heater is coupled between the input terminal and the return terminal. The thermopile is spaced apart from the heater by a galvanic isolation region. The switch device includes a control input coupled to an output of the thermopile. The switch device is coupled to at least one output terminal of the IC chip.

Abstract: Disclosed is a Bulk Acoustic Wave (BAW) assist filter structure with a BAW resonator stacked onto an integrated passive device (IPD). In exemplary aspects disclosed herein, the BAW filter structure includes a transducer with electrodes and a piezoelectric layer between the electrodes. The IPD is electrically coupled to the BAW resonator and provides a high frequency of operation. In such a configuration, the BAW assist filter structure has a low insertion loss and mitigates electrical length parasitic loss due to the close electrically proximity of the BAW resonator stacked onto the IPD. Further, the BAW assist filter structure is able to filter high frequencies and provides improved filter performance and greater flexibility in design of a filter transfer function.

Abstract: Some embodiments include an integrated assembly having a first bottom electrode adjacent to a second bottom electrode. An intervening region is directly between the first and second bottom electrodes. Capacitor-insulative-material is adjacent to the first and second bottom electrodes. The capacitor-insulative-material is substantially not within the intervening region. Top-electrode-material is adjacent to the capacitor-insulative-material. Some embodiments include methods of forming integrated assemblies.