Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

Abstract: A distributed LC filter structure is disclosed. The distributed LC filter structure provides simultaneously a distributed inductance and a distributed capacitance in the same structure. Accordingly, discrete passive elements are eliminated and high, homogenous integration is achieved. Interconnections between the distributed inductance and the distributed capacitance are tailored to leverage a parasitic inductance of the distributed capacitance to increase the overall inductance of the distributed LC filter structure. Similarly, the interconnections are tailored to leverage a parasitic capacitance resulting from the distributed inductance to add up with the distributed capacitance augmenting the overall capacitance of the structure.

Abstract: A method of forming a package structure includes the following steps. A first package structure is formed. The first package structure is connected to a second package structure. The method of forming the first package structure includes the following steps. A redistribution layer (RDL) structure is formed. A die is bonded to the RDL structure. The RDL structure is electrically connected to the die. A through via is formed on the RDL structure and laterally aside the die. An encapsulant is formed to laterally encapsulate the through via and the die. A protection layer is formed over the encapsulant and the die. A cap is formed on the through via and laterally aside the protection layer, wherein the cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the protection layer. The cap is removed from the first package structure.

Abstract: A preparation method of a semiconductor structure includes: providing a substrate, and forming a groove on the substrate by etching; forming a first dielectric layer on a side wall of the groove; forming a first electrode on the bottom of the groove and on an inner surface of the first dielectric layer; forming a second dielectric layer on a surface of the first electrode; and forming a second electrode on a surface of the second dielectric layer.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a contact feature in a first dielectric layer, a first passivation layer over the contact feature, a bottom conductor plate layer disposed over the first passivation layer and including a first plurality of sublayers, a second dielectric layer over the bottom conductor plate layer, a middle conductor plate layer disposed over the second dielectric layer and including a second plurality of sublayers, a third dielectric layer over the middle conductor plate layer, a top conductor plate layer disposed over the third dielectric layer and including a third plurality of sublayers, and a second passivation layer over the top conductor plate layer.

Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

Abstract: The present disclosure relates to a top emitting AMOLED display panel, a manufacturing method thereof, and a display device. The top emitting AMOLED display panel includes a passivation layer and a protective conductive layer. The passivation layer is sandwiched between an interlayer insulating layer and a planarization layer of the top emitting AMOLED display panel; the protective conductive layer covers a metal layer and side walls of openings. The passivation layer covering the metal layer can physically protect and prevent the metal layer from oxidation, and the protective conductive layer coats the metal layer to prevent the metal layer from being etched or oxidized by anode etching solution.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes the following operations. A first integrated circuit component having a fuse structure is received. A second integrated circuit component having an inductor is received. The second integrated circuit component is bonded to the first integrated circuit component. The inductor is electrically connected to the fuse structure, wherein the inductor is electrically connected to a ground through the fuse structure.

Abstract: The present application discloses a semiconductor device with a horizontally arranged capacitor. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.

Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

Abstract: The invention relates to an energy storage device (21) comprising a substrate with a groove (3) having a first and a second face (9a, 9b). A capacitor material (5) in the groove (3), the capacitor material having an upper surface (25). The first and the second face (9a, 9b) of the groove (3) each having a coat of electrically conductive material (7) wherein the coats of electrically conductive materials (7) on the first and second faces (9a, 9b) are electrically separated. And wherein, a non-insulating element (23) is configured to be electrically contactable with the upper surface (25) of the capacitor material and when in electrical contact is electrically separated from the coats of electrically conductive materials (7) on the first and second surfaces by the capacitor material (9a, 9b).

Abstract: A display substrate includes: M rows of pixel circuits and M rows of scan signal lines. Each pixel circuit includes: a driving transistor connected to a first power line and a light-emitting device; a first storage sub-circuit connected to a gate electrode of the driving transistor; a second storage sub-circuit connected to the first power line and the gate electrode of the driving transistor; a gating sub-circuit connected to the first storage sub-circuit, an (m?1)th row of scan signal line, and an mth row of scan signal line, where the gating sub-circuit is configured to: provide a data voltage signal to the first storage sub-circuit, and provide a reference voltage signal to the first storage sub-circuit; and a threshold compensation sub-circuit connected to the (m?1)th row of scan signal line, and configured to perform, in response to control of connected scan signal line, threshold compensation on the driving transistor.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.

Abstract: A microelectronic device comprises a first deck structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, a second deck structure vertically overlying the first deck structure and comprising additional tiers of the conductive structures and insulative structures, a staircase structure within the first deck structure and having steps comprising edges of the tiers, a dielectric material covering the steps of the staircase structure and extending through the first deck structure, and a liner material interposed between the steps of the staircase structure and terminating at an interdeck region between the first deck structure and the second deck structure. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A nonvolatile memory device is provided, the device comprising a ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, whereby the ferroelectric memory capacitor at least partially overlaps a gate of the first transistor.

Abstract: The present disclosure relates to the field of display technology, and in particular, to a gate driving structure, an array substrate and a display device. The gate driving structure may include: a base substrate; a shift register, formed on the base substrate, and including a plurality of thin film transistors and at least one capacitor, the capacitor being coupled to the thin film transistor; and a signal wiring group, formed on the base substrate, and including a plurality of signal wirings spaced apart from each other, the signal wiring being coupled to the thin film transistor. An orthographic projection of the capacitor on the base substrate is at least partially overlapped with an orthographic projection of the signal wiring group on the base substrate.

Abstract: A capacitor includes: a lower electrode including a metal nitride represented by MM?N, wherein M is a metal element, M? is an element different from M, and N is nitrogen; a dielectric layer on the lower electrode; an interfacial layer between the lower electrode and the dielectric layer and including a metal nitrate represented by MM?ON, wherein M is a metal element, M? is an element different from M, N is nitrogen, and O is oxygen; and an upper electrode on the dielectric layer.

Abstract: A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.

Abstract: A semiconductor device includes a first power rail, a second power rail, and a first cell. The first cell has a first first-type active region and a first second-type active region, and a first cell height of the first cell is defined as a pitch between the first power rail and the second power rail. The semiconductor device further includes a second cell having a second first-type active region and a second second-type active region, wherein the second first-type active region extends in a second row and a third row on a first side of the first row and has a first width in the column direction greater than a second width of the first first-type active region in the column direction. The semiconductor device also includes a third cell having a first portion and a second portion arranged in the second row and a fourth row, respectively.

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

Abstract: A chip assembly may include a package substrate that includes one or more pins. The chip assembly may also include one or more pads. The one or more pads may be electrically coupled to the one or more pins. In addition, the chip assembly may include a board that includes one or more board pads. Further, the chip assembly may include an anisotropic layer. The anisotropic layer may be positioned between the board and the one or more pads and between the board and a portion of the package substrate. In addition, the anisotropic layer may mechanically couple the board to the one or more pads and to the portion of the package substrate. Further, the anisotropic layer may electrically couple the one or more pads to the one or more board pads.

Abstract: A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.

Abstract: Methods for forming hafnium oxide within a three-dimensional structure, such as in a high aspect ratio hole, are provided. The methods may include depositing a first hafnium-containing material, such as hafnium nitride or hafnium carbide, in a three-dimensional structure and subsequently converting the first hafnium-containing material to a second hafnium-containing material comprising hafnium oxide by exposing the first hafnium-containing material to an oxygen reactant. The volume of the second hafnium-containing material may be greater than that of the first hafnium-containing material. Voids or seams formed during the deposition of the first hafnium-containing material in the three-dimensional structure may be filled by the expanded material after exposing the first hafnium-containing material to the oxygen reactant. Thus, the three-dimensional structure, such as a high aspect ratio hole, can be filled with hafnium oxide substantially free of voids or seams.

Abstract: A ferroelectric random access memory device comprises: a memory cell array including a plurality of memory cells each having one ferroelectric transistor (FeFET) connected between a read line of a plurality of read lines and a source line of a plurality of source lines and one transistor connected between a bit line of a plurality of bit lines and a gate of the FeFET and having a gate connected to a corresponding word line of a plurality of word lines; and a read/write control unit, when address information for a memory cell to be written is applied with a write command and data, selecting a word line and a read line corresponding to a row address and applying a write voltage having a positive voltage level, and applying a ground voltage to the selected read line, and applying the write voltage to a bit line corresponding to a memory cell.

Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.

Abstract: A capacitor structure implemented as a layered structure including a plurality of alternating dielectric and metallization layers, and a method of manufacturing such capacitor structure. The capacitor structure including at least one lateral parallel plate capacitor part (LPP part) including two first electrodes on two different layers separated by dielectric material of a plurality of the alternating layers, and at least one vertical parallel plate capacitor part (VPP part) including two second electrodes each including a plurality of superimposed slabs or bars arranged on a plurality of the metallization layers. The at least one LPP part is electrically coupled with the at least one VPP part to form the capacitor structure. A variation in capacitance value of the at least one LPP part due to a variation of thickness of dielectric material is at least partially compensated by an opposite variation in capacitance value of the at least one VPP part.

Abstract: A capacitor includes a silicon substrate, a conductor layer, and a dielectric layer. The silicon substrate has a principal surface including a capacitance generation region and a non-capacitance generation region. The silicon substrate has a porous part provided in a thickness direction in the capacitance generation region. The conductor layer has a surface layer part at least covering part of a surface of the capacitance generation region and a filling part filled in at least part of fine pores of the porous part. The dielectric layer is provided between an inner surface of the fine pores and the filling part.

Abstract: Provided are a semiconductor memory device with guard pillars and a manufacturing method thereof. The semiconductor memory device includes a substrate having a memory region and a periphery region surrounding the memory region, a plurality of bit line structures, a plurality of contacts, a plurality of guard pillars and a plurality of capacitors. The bit line structures are arranged parallel to each other on the substrate in the memory region. The contacts are disposed between the adjacent bit line structures and electrically connected to the substrate. The guard pillars are disposed on the substrate and located between the adjacent bit line structures at the boundary between the memory region and the periphery region. The capacitors are disposed on the plurality of contacts to be electrically connected to the plurality of contacts.

Abstract: A semiconductor device includes a semiconductor substrate, a trench capacitor arranged on the semiconductor substrate, a first wiring layer, a second wiring layer, a first TSV penetrating the semiconductor substrate outside the trench capacitor, a second TSV penetrating the semiconductor substrate outside the trench capacitor, a first connecting terminal connected to the first TSV, a second connecting terminal connected to the first TSV, a third connecting terminal connected to the second TSV, and a fourth connecting terminal connected to the second TSV. A plurality of connecting terminals including the first through fourth connecting terminals are arranged dispersively over an entire area of the first wiring layer and the second wiring layer of the semiconductor device, thereby stabilizing voltage supplied to an image unit and achieving a stable image signal.

Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Abstract: The present invention is to provide a GePD, the optical sensitivity of which is independent from a temperature, and to achieve a photodetector in which heat applied from heaters is constant even when a plurality of GePDs are provided and in which a temperature and sensitivity of each of the GePDs are the same. The photodetector includes germanium photoreceivers including a silicon substrate, a lower clad layer, a silicon core layer, a silicon waveguide layer, a germanium layer, an upper clad layer, and electrodes. In the photodetector, two or more germanium photoreceivers are arranged adjacent to each other on the silicon substrate, and the photodetector includes resistors embedded in the upper clad layer to cover or surround respective germanium layers of the two or more germanium photoreceivers arranged adjacent to each other, the resistors being made of a metal or a metal compound.

Abstract: The present disclosure provides a packaging-level chip and a chip module packaged with a magnetic cover, and an electronic product. The packaging-level chip packaged with a magnetic cover comprises a die, a packaging material, a substrate and a magnetic cover. The packaging material is packaged on the outside of the die which is arranged on the substrate, and the magnetic cover is packaged on the top of the packaging material and is magnetic.

Abstract: A method for depositing a hafnium lanthanum oxide film on a substrate by a cyclical deposition in a reaction chamber is disclosed. The method may include: depositing a hafnium oxide film on the substrate utilizing a first sub-cycle of the cyclical deposition process and depositing a lanthanum oxide film utilizing a second sub-cycle of the cyclical deposition process.

Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

Abstract: A thin film structure includes a first conductive layer, a dielectric material layer on the first conductive layer, and an upper layer on the dielectric material layer. The dielectric material layer including HfxA1-xO2 satisfies at least one of a first condition and a second condition. In the first condition the dielectric material layer is formed to a thickness of 5 nm or less and in the second condition the x in HfxA1-xO2 is in a range of 0.3 to 0.5.

Abstract: Provided are MIM capacitor and semiconductor structure including MIM capacitor. The MIM capacitor includes a dielectric structure, a bottom electrode on the dielectric structure, a first insulating layer covering the bottom electrode and the dielectric structure, a middle electrode stacked on the bottom electrode, a spacer, a second insulating layer and a top electrode. The middle electrode is separate from the bottom electrode by the first insulating layer therebetween. A bottommost surface of the middle electrode is lower than a top surface of the bottom electrode and higher than a bottom surface of the bottom electrode. The spacer is disposed on the first insulating layer and laterally aside and covers a sidewall of the middle electrode. The second insulating layer covers the middle electrode and the spacer. The top electrode is stacked on the middle electrode and separate from the middle electrode by the second insulating layer therebetween.

Abstract: A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost.

Abstract: A printed circuit board (PCB) includes: an insulation substrate; a first pad on the insulation substrate; and a second pad on the insulation substrate and spaced apart from the first pad, wherein the second pad has a size substantially the same as a size of the first pad, wherein the first pad includes a first recess configured to receive a first electrode of a passive element, wherein the second pad includes a second recess receiving a second electrode of the passive element, wherein the first recess has a depth substantially the same as a thickness of the first pad, wherein the second recess has a depth substantially the same as a thickness of the second pad, wherein each of the first recess and the second recess exposes an upper surface of the insulation substrate.

Abstract: A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.

Abstract: A semiconductor memory structure includes a semiconductor substrate, a bit line disposed on the semiconductor substrate, and a capacitor contact disposed on the side of the bit line. The capacitor contact includes a semiconductor plug disposed on the semiconductor substrate, a metal plug disposed on the semiconductor plug, a metal silicide liner extending along the sidewalls and bottom of the metal plug, and a nitride layer disposed on the metal silicide liner. The top surface of the metal silicide liner is lower than the top surface of the metal plug. The nitride layer surrounds the top portion of the metal plug.

Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.

Abstract: A smartphone marine vessel location system utilizes global positioning to determine the location and trajectory of marine vessels. When two marine vessels have a trajectory that will bring the vessels within a warning zone a trajectory alert is activated and when the two vessels enter into a warning zone, a collision warning is activated. An App on the smartphones may produce a display showing the location of the marine vessels and may produce the alerts when required. The smartphone may also communicate with other navigational system on the marine vessel to produce a display and alerts, such as through Bluetooth. The location of marine vessels may be acquired through the App, through a crowd-sourcing application, and/or through a carrier sourced location.

Abstract: A semiconductor structure and its fabrication method are provided. The method includes: providing a substrate and a first metal layer in the substrate; forming a dielectric layer with a first opening exposing a portion of a top surface of the first metal layer on the substrate; bombarding the portion of the top surface of the first metal layer exposed by the first opening, by using a first sputtering treatment, to make metal materials on the top surface of the first metal layer be sputtered onto sidewalls of the first opening to form a first adhesion layer; and forming a second metal layer on a surface of the first adhesion layer and on the exposed portion of the top surface of the first metal layer using a first metal selective growth process.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.

Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. A conductive gating structure is adjacent to the active region. The conductive gating structure includes an inner region proximate the active region and includes an outer region distal from the active region. The inner region includes a first material containing titanium and nitrogen, and the outer region includes a metal-containing second material. The second material has a higher conductivity than the first material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Abstract: An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a first electrode layer formed over a substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure also includes a first dielectric layer formed on the first spacers, and an end of the first dielectric layer is in direct contact with the first pacer.