Abstract: It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the like, is formed over a substrate, separated from the substrate, and transferred onto a circuit board 100. An electrical conduction with a wiring pattern 114 provided in the circuit board 100 is made by a wire 112 or a solder 107, thereby forming a high frequency module or the like.

Abstract: A trench-type PIP capacitor having a small step at the end part of the capacitor without increasing manufacturing cost, and a power integrated circuit device that uses such a trench-type PIP capacitor are disclosed. A method of manufacturing the power integrated circuit device also is disclosed. A trench-type PIP capacitor has a construction, in the surface region of a semiconductor substrate, comprising an isolating insulation layer formed on an inner wall of a trench and a first polysilicon that fills the trench through the isolating insulation layer and becomes a lower electrode. Since this construction has a small step formed at the end region of the capacitor, a metal layer for wiring does not need to be made excessively thick, allowing a fine structure of the metal layer. Therefore, the power IC provided with such a trench-type PIP capacitor can have a fine structure.

Abstract: A capacitive chemical sensor, along with methods of making and using the sensor are provided. The sensors described herein eliminate undesirable capacitance by etching away the substrate underneath the capacitive chemical sensor, eliminating most of the substrate capacitance and making changes in the chemical-sensitive layer capacitance easier to detect.

Abstract: In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

Abstract: An example of a carbon nanotube capacitor may include (i) a carbon nanotube film having carbon nanotubes and voids with dielectric material, (ii) conductive contacts and (iii) a dielectric layer. The carbon nanotube film may switch from a conductive state to a non-conductive state when a voltage is applied by creating an electrical break within the carbon nanotube film and providing a first conductive region and a second conductive region within the carbon nanotube film. The electrical break may separate the first conductive region from the second conductive region. The first and second conductive regions may store charge. An integrated device may include one or more transistors and one or more carbon nanotube capacitors. A method of making a carbon nanotube capacitor is also disclosed.

Abstract: Oxide thin film, electronic devices including the oxide thin film and methods of manufacturing the oxide thin film, the methods including (A) applying an oxide precursor solution comprising at least one of zinc (Zn), indium (In) and tin (Sn) on a substrate, (B) heat-treating the oxide precursor solution to form an oxide layer, and (C) repeating the steps (A) and (B) to form a plurality of the oxide layers.

Abstract: A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.

Abstract: A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.

Abstract: Embodiments of the present disclosure include devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like.

Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.

Abstract: Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1?x): x (0.01?x?0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.

Abstract: A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.

Abstract: A semiconductor device includes a SOI (silicon on insulator) substrate having a first region and a second region, a multilayer wiring layer formed on the SOI substrate and having an insulating layer and a wiring layer alternately stacked in this order, a first inductor formed over the SOI substrate, and a second inductor formed over the SOI substrate and positioned above the first inductor.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: Disclosed are a semiconductor integrated circuit chip, a multilayer chip capacitor, and a semiconductor integrated circuit chip package. The semiconductor integrated circuit chip includes a semiconductor integrated circuit chip body, an input/output terminal disposed on the outside of the semiconductor integrated circuit chip body, and a decoupling capacitor disposed at a side face of the semiconductor integrated circuit chip body and electrically connected to the input/output terminal. The semiconductor integrated circuit chip cab be obtained, which can maintain an impedance of a power distribution network below a target impedance in a wide frequency range, particularly at a high frequency, by minimizing an inductance between a decoupling capacitor and a semiconductor integrated circuit chip.

Abstract: A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.

Abstract: A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.

Abstract: An integrated circuit device having a capacitor structure and methods of manufacture are disclosed. The device has a substrate, e.g., silicon wafer, silicon on insulator, epitaxial wafer. The device has a dielectric layer overlying the substrate and a polysilicon layer overlying the dielectric layer. The device has a tungsten silicide layer overlying the polysilicon layer and a first oxide layer overlying the tungsten silicide layer. A nitride layer overlies the oxide layer. A second oxide layer is overlying the nitride layer to form a sandwiched oxide on nitride on oxide structure to form a capacitor dielectric. The device also has an upper capacitor plate formed overlying the second oxide layer.

Abstract: Disclosed is a method of manufacturing a storage capacitor having increased aperture ratio: providing a substrate having a metal layer disposed thereon, and said metal layer is covered correspondingly with a first dielectric layer and a second dielectric layer in sequence; forming a photoresist layer with a uniform thickness to cover said second dielectric layer; performing a process of exposure-to-light and development to a portion of said photoresist layer that is correspondingly disposed over said metal layer sequentially, so that its thickness is less than its original thickness; removing said photoresist layer and etching said portion of said second dielectric layer, so that a thickness of said portion of said second dielectric layer is less than its original thickness, and the etching depth of said portion is greater than that of the other remaining portions of said second dielectric layer; and forming an electrode layer on said second dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: Provided is a semiconductor device including a MIM capacitor, and having excellent waterproof property and antioxidant property even when being formed between wiring layers. The semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first wiring layer embedded in the first insulating film, a wiring cap film for covering the first wiring layer, the MIM capacitor formed on the wiring cap film, a hydrogen barrier film for covering the MIM capacitor, a second insulating film formed on the hydrogen barrier film, conductive plugs passing through the second insulating film and the hydrogen barrier film, one of which being connected to an upper electrode of the MIM capacitor and the other of which being connected to a lower electrode of the MIM capacitor, and a second wiring layer connected to the conductive plugs, and the upper and lower electrodes of the MIM capacitor.

Abstract: A capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially stacked. The dielectric layer has a stacked layer structure including a predetermined number of hafnium oxide sublayers and predetermined number of tantalum oxide sublayers. The number, materials, and thicknesses of the sublayers are determined so that the thickness ratio has a range in which, in voltage-leakage current characteristics showing the relationship between the voltage between the first and second electrodes and the leakage current, a start voltage at which the slope of an increase in the current starts to discontinuously increase satisfies an electric field strength of 3 [MV/cm] or more when the ratio of the total thickness of the predetermined number of tantalum oxide sublayers to the total thickness of the dielectric layer is varied, and the thickness ratio is within the range such that the start voltage is within the range.

Abstract: A capacitor in an integrated circuit (“IC”) has a first plurality of conductive crosses formed in a layer of the IC electrically connected to and forming a portion of a first node of the capacitor and a second plurality of conductive crosses formed in the metal layer of the IC. The conductive crosses in the second plurality of conductive crosses are electrically connected to and form a portion of a second node of the capacitor and capacitively couple to the first node.

Abstract: Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Abstract: Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor.

Abstract: A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively.

Abstract: A semiconductor device includes: a first capacitor including an upper electrode, a lower electrode, an intermediate electrode arranged between the upper electrode and the lower electrode, and a shield line arranged in the same layer as the intermediate electrode; and a second capacitor, including an upper electrode, a lower electrode, and an intermediate electrode arranged between the upper electrode and the lower electrode, and arranged adjoining to the first capacitor. In the first capacitor and the second capacitor, the upper electrode, the lower electrode and the shield line are electrically connected to a ground electrode. The shield line lies between the first capacitor and the second capacitor. Accordingly, a MIM capacitor with excellent layout efficiency is provided while noise effects are reduced.

Abstract: A capacitor is described which includes a substrate with a doped area of the substrate forming a first electrode of the capacitor. A plurality of trenches is arranged in the doped area of the substrate, the plurality of trenches forming a second electrode of the capacitor. An electrically insulating layer is arranged between each of the plurality of trenches and the doped area for electrically insulating the trenches from the doped area. The doped area includes first open areas and at least one second open area arranged between neighboring trenches of the plurality of trenches, wherein the at least one open area is arranged below the at least one substrate contact. A shortest first distance between neighboring trenches is separated by the first open areas and is shorter than a shortest second distance between neighboring trenches separated by the at least one second open area.

Abstract: A memory includes first contact plugs; ferroelectric capacitors above the first contact plugs; second contact plugs in a first interlayer film being below an area which is between two adjacent ferroelectric capacitors, the second contact plug; first interconnections connected to the second contact plugs, the first interconnections extending in a first direction substantially perpendicular to an arrangement direction, in which the two ferroelectric capacitors are arranged, on the first interlayer film; a second interlayer film above the first interlayer film and the first interconnection; third contact plugs in the second interlayer film, the third contact plugs being respectively connected to the first interconnections at positions shifted from the second contact plugs in the first direction; and second interconnections electrically connecting the third contact plug to the upper electrodes of the two ferroelectric capacitors.

Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.

Abstract: The semiconductor device (100) comprises at least one semiconductor element (20), a metallization structure comprising a first (31) and a second line (32) and extending thereon a resistor. An electrically insulating protection layer (36) is present on the resistor (35) and is defined in a pattern that is substantially identical to the resistor pattern and has a temperature stability up to a temperature that is at least equal to a deposition temperature of a passivation layer (37) to be deposited thereon so as to cover the metallization structure. Both the resistor (35) and the protection layer (36) are deposited conformally on the metallization structure and any underlying substrate.

Abstract: The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the substrate and the recess, depositing a filler layer so as to overlie the first conductive layer and fill the recess, and etching the first and second conductive layers so as to define a lower electrode within the recess. The method further comprises forming a cap layer on the lower electrode so as to overlie the first conductive layer and the filler layer and etching at least a portion of the substrate away from the lower electrode to thereby at least partially isolate the lower electrode. Subsequently, the remainder of the capacitor structure may be formed by depositing a dielectric layer on the lower electrode and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.

Abstract: Apparatuses and methods for increasing well distributed, high quality-factor on-chip capacitance of integrated circuit devices are disclosed. In one aspect, an integrated circuit device structure includes a first metal line implemented on a metallization layer of a semiconductor substrate, the first metal line having a first set of metal fingers extending therefrom; and a second metal line electrically isolated from the first metal line, the second metal line having a second set of metal fingers extending therefrom, the first set of metal fingers and the second set of metal fingers capacitively coupled. The basic structure of metal lines with interlocking metal fingers may be repeated on multiple adjacent metallization layers, with the metal lines oriented either in parallel or perpendicular.

Abstract: The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode.

Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.

Abstract: A semiconductor device includes a first wiring layer which is provided above a semiconductor substrate and includes a first insulating film and a wiring buried in the first insulating film, a second insulating film provided above the first wiring layer, a third insulating film provided on the second insulating film, and a capacitor element provided on the third insulating film. The wiring includes an upper surface having a protruding portion. The capacitor element includes a lower electrode provided on the third insulating film, a capacitor insulating film provided on the lower electrode, and an upper electrode provided on the capacitor insulating film.

Abstract: A movable substrate is placed over a bottom substrate where both substrates contain Coulomb islands. The Coulomb islands can be adjusted in charge and are used to develop a force between two opposing Coulomb islands. Information from sensors is applied to a control unit to control the movement of the movable substrate. Coulomb islands are formed in the juxtaposed edges of a first substrate and second substrate, respectively. The islands generate edge Coulomb forces. These edge Coulomb forces can be used to detach, repel, move, attract and reattach the edges of substrates into new configurations. One possibility is to combine a plurality of individual substrates into one large planar substrate.

Abstract: Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.

Abstract: One or more embodiments relate to a semiconductor chip including a capacitor arrangement, the capacitor arrangement comprising: a first capacitor; and a second capacitor stacked above the first capacitor, the first capacitor and the second capacitor coupled in series between a first metallization level and a second metallization level adjacent the first metallization level.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.

Abstract: A capacitor includes a first capacitor structure on a substrate, the first capacitor structure including a first electrode, a first dielectric layer pattern, and a second electrode, a second capacitor structure on the first capacitor structure, the second capacitor structure including a third electrode, a second dielectric layer pattern, and a fourth electrode, at least one first contact pad on a side of the first electrode, and a wiring structure connecting the at least one first contact pad and the fourth electrode.

Abstract: A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).

Abstract: A semiconductor device includes a semiconductor substrate and a capacitor which is disposed on a principal surface of the semiconductor substrate. The capacitor includes a lower electrode film disposed on the principal surface of the semiconductor substrate, a dielectric film disposed on the lower electrode and an upper electrode film disposed on the dielectric film. The semiconductor device further includes an interconnection film which includes a portion disposed on the upper electrode film so as to be electrically coupled to the upper electrode film. Directions of residual stresses of the upper electrode film coincide with directions of residual stresses of the portion of the interconnection film. Each of the upper electrode film and the interconnection film may include at least one of platinum and iridium. Also, there is provided a method of manufacturing the semiconductor device.

Abstract: The invention provides an electronic component which has an improved breakdown limit value of withstand voltage and improved insulation properties and which can be made compact and provided with a multiplicity of layers and a great capacity. The electronic component includes a first conductor having a bottom conductor formed on a substrate and a raised conductor formed to protrude from the bottom conductor, a dielectric film formed on the raised conductor, and a second conductor formed on the dielectric film to constitute a capacitor element in combination with the raised conductor and the dielectric film.

Abstract: A ferroelectric capacitor including: a substrate; a first electrode formed above the substrate; a first ferroelectric layer formed above the first electrode and including a complex oxide shown by Pb(Zr,Ti)O3; a second ferroelectric layer formed above the first ferroelectric layer and including a complex oxide shown by Pb(Zr,Ti)1-xNbxO3; and a second electrode formed above the second ferroelectric layer.

Abstract: The capacitor structure includes a first electrode having a plurality of teeth protruding in a comb shape from an electrode base of a first electrode line and a second electrode having a plurality of teeth protruding in a comb shape from an electrode base of a second electrode line, both formed in a first wiring layer. The first and second electrodes face each other with their teeth interdigitated with each other via a dielectric. At least one of the teeth of the first electrode is electrically connected with a third electrode line formed in a second wiring layer.

Abstract: A semiconductor device includes a lower electrode provided on a semiconductor substrate, an upper electrode provided on the lower electrode to overlap a part of the lower electrode, a first insulating film provided between the lower electrode and the upper electrode, and a second insulating film provided in contact with an upper part of the upper electrode and on the upper part of the lower electrode, and having a density higher than that of the first insulating film, the second insulating film covering a side surface and a top surface of the upper electrode.