Abstract: An n-type first single crystal silicon layer is provided as collector region over a silicon substrate with a first insulating film interposed therebetween. A p-type first polysilicon layer is provided as an extension of a base region over the first single crystal silicon layer with a second insulating film interposed therebetween. A p-type second single crystal silicon layer is provided as intrinsic base region on a side of the first single crystal silicon layer, second insulating film and first polysilicon layer. An n-type third single crystal silicon layer is provided as emitter region on a side of the second single crystal silicon layer. And an n-type third polysilicon layer is provided on the first insulating film as extension of an emitter region and is connected to a side of the third single crystal silicon layer.

Abstract: The present invention is directed to an SOI LDMOS device having improved current handling capability, particularly in the source-follower mode, while maintaining an improved breakdown voltage capability. The improvement in current handling capability is achieved in a first embodiment by introducing an offset region between the source and thin drift regions. The offset region achieves an offset between the onset of the linear doping profile and the thinning of the SOI layer that results in the thin drift region. In a second embodiment a further increase in the current handling capability of an SOI device is achieved by fabricating an oxide layer over the offset region, with the thickness of the oxide layer layer varying up to about half the thickness of the oxide layer fabricated over the thin drift region.

Abstract: A substrate potential limiting device for an integrated circuit that includes a semiconductor substrate is provided. The device includes at least one unidirectional element connected between a substrate contact on the semiconductor substrate and a reference potential. The unidirectional element may be a bipolar transistor. The bipolar transistor includes a base and a collector connected to the at least one substrate contact and an emitter connected to the reference potential.

Abstract: A lateral PNP transistor (LPNP) (102) having the low resistance base buried N+ region (114) removed from below the emitter region (118). This leaves a high resistance n-well (116) below the emitter. The resistance from the center of the emitter region (118) to the N+ buried region (114) is greater than the resistance at the periphery of the emitter region (118) to the N+ buried region (114). Debiasing will occur in the center of the emitter region (118) where the parasitic base current is generated. Thus, the ratio of parasitic current to active collector current and peak beta will improve.

Abstract: An Si semiconductor device has an emitter region, a base region and a collector region formed on a substrate substantially in parallel to a plane of the substrate. And at least one of the emitter region the base region and the collector region includes an SiGe mixed crystal semiconductor region formed by ion implantation of Ge.

Abstract: A MOSBJT (Metal Oxide Semiconductor Bipolar Junction Transistor) is formed to have both the higher current drive capability of the BJT and the smaller device area of the scaled down MOSFET. The MOSBJT includes a collector region and an emitter region comprised of a semiconductor material with a first type of dopant. A base region is disposed between the collector region and the emitter region, and the base region is comprised of a semiconductor material with a second type of dopant that is opposite of the first type of dopant. Unlike a conventional BJT, a base terminal of the MOSBJT is comprised of a dielectric structure disposed over the base region and comprised of a gate structure disposed over the dielectric structure. Unlike a conventional MOSFET, the dielectric structure of the MOSBJT is relatively thin such that a tunneling current through the dielectric structure results when a turn-on voltage is applied on the gate structure. This tunneling current is a base current of the MOSBJT.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: A structure for the protection of a high-voltage pad includes a lateral bipolar transistor, an N-type diffusion of which, connected to the pad to be protected, is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-type implantation is made on the entire substrate outside the N-type tub except in the region in which the zone extends.

Abstract: A lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other NPN bipolar devices capable of being operated at high frequencies. The PNP device is incorporated to an electrically insulated multilayer structure which comprises a semiconductor substrate, doped for conductivity of the P-type, a first buried layer, doped for conductivity of the N-type to provide a base region, and a second layer, overlying the first and having conductivity of the N-type, to provide an active area distinguishable by a P-doped emitter region within the active area being located peripherally and oppositely from a P-doped collector region. The lateral PNP device can be operated at high frequencies with suitable collector current values and good amplification, to provide a superior figure of merit compared to that typical of conventional lateral PNP devices.

Abstract: A lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other NPN bipolar devices capable of being operated at high frequencies. The PNP device is incorporated to an electrically insulated multilayer structure which comprises a semiconductor substrate, doped for conductivity of the P-type, a first buried layer, doped for conductivity of the N-type to provide a base region, and a second layer, overlying the first and having conductivity of the N-type, to provide an active area distinguishable by a P-doped emitter region within the active area being located peripherally and oppositely from a P-doped collector region. The lateral PNP device can be operated at high frequencies with suitable collector current values and good amplification, to provide a superior figure of merit compared to that typical of conventional lateral PNP devices.

Abstract: A manufacturing method for semiconductor components is disclosed which will allow better precision in the definition of the doped areas of the components and the separation of differently doped areas. A selectively shaped area of, for example, polysilicon, defining the area or areas to be doped, is deposited on the component before the masks are applied. This makes the fitting of the masks less critical, as they only have to be fitted within the area of the polysilicon layer. In this way an accuracy of 0.1 .mu.m or better can be achieved.

Abstract: An improved structure and method for gated lateral bipolar transistors is provided. The present invention capitalizes on opposing sidewall structures and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. The conserved surface space allows a higher density of structures per chip. The conductive sidewall members couple to the gate of the gated lateral bipolar transistor and, additionally, to a retrograded, more highly doped bottom layer. The improved structure provides for both metal-oxide semiconductor (MOS) type conduction and bipolar junction transistor (BJT) type conduction beneath the gate of the gated lateral bipolar transistor.

Abstract: A lateral transistor includes a semiconductor substrate of a first conductivity type having a major surface; an emitter region of a second conductivity type in the semiconductor substrate on the major surface of the semiconductor substrate; a collector region of a second conductivity type in the semiconductor substrate on the major surface of the semiconductor substrate, spaced from and surrounding the emitter region, and including sides and corners; an electrically insulating layer on the major surface of the semiconductor substrate and including a first penetrating hole extending to the collector region except at a first of the corners and a second penetrating hole extending to the emitter region; a collector electrode contacting the collector region through the first penetrating hole and surrounding the emitter region except at the first corner; an emitter electrode at the same level as the collector electrode and contacting the emitter region through the second penetrating hole; and an emitter wiring laye

Abstract: A semiconductor device having a substrate with a first conductivity type. The substrate has a top substrate region that also has the first conductivity type. A first doped region, a second doped region and a third doped region are located in the top substrate region where the first and second doped regions have a second conductivity type opposite the first conductivity type while the third doped region has the first conductivity type and where the third doped region is between the first and second doped regions. A doped well region is also in the top substrate region and has the second conductivity type and has the second doped region and at least a portion of the third doped region located therein. A method of forming the device is also provided herein.

Abstract: A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages.

Abstract: A bipolar transistor (100) and a method for forming the same. A diffusion source dielectric layer (118) is deposited over a semiconductor body (101). An emitter window (116) is then etched through the diffusion source dielectric layer (118). An extrinsic base region (110) is diffused from the diffusion source dielectric layer (118). The intrinsic base region (108) is then implanted. Base-emitter spacers (120) are then formed followed by the emitter electrode (124) and emitter region (126). The extrinsic base region (110) is self-aligned to the emitter eliminating the alignment tolerances for the lateral diffusion of the extrinsic base implant and an extrinsic base implant.

Abstract: A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si substrate, the sheet resistance of the polycrystalline Si film forming the base outlet electrode of the npn transistor is decreased to two thirds of the sheet resistance of the polycrystalline Si film forming at least one electrode of at least one other device. The base outlet electrode can be made by first making the polycrystalline Si film on the entire surface of the substrate, then applying selective ion implantation of Si to a selective portion of the polycrystalline Si film for making the base outlet electrode to change it into an amorphous state, and then annealing the product to grow the polycrystalline Si film by solid-phase growth.

Abstract: A complementary bipolar transistor having a lateral npn bipolar trasistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral pnp bipolar transistor has an emitter region and a collector region which includes high-density regions and low-density regions, and the emitter region is formed in an n type tub region. In the integrated injection logic circuit, collector regions are surrounded by a high-density p type region, and low-density p type regions are formed under the collector regions. The diffusion capacitor and the polysilicon capacitor are formed in one substrate. The diffusion regions except the regions formed by diffusing the impurities in the polysilicon resistors into the epitaxial layer are formed before forming the polysilicon resistors, and polysilicon electrodes are formed along with the polysilicon resistors.

Abstract: An integrated circuit device comprising an active layer of a first conductivity type insulatively disposed over a semiconductor substrate, a lateral bipolar transistor fabricated in the active layer, the lateral bipolar transistor comprising a first base layer of a second conductivity type which is formed in the active layer, an emitter layer of the first conductivity, and a collector of the first conductivity which is formed in the active layer on a lateral side of the first base layer, a MOS transistor fabricated in the active layer, the MOS transistor comprising a second base layer of the second conductivity type, a source layer of the first conductivity type which is formed in the second base layer, a drain layer of the first conductivity type which is formed in the active layer, and a gate electrode insulatively disposed over the second base layer between the source layer and the drain layer, and an isolation layer formed in the active layer for separating the bipolar transistor and the MOS transistor fr

Abstract: An n.sup.- -type silicon active layer having a thickness of 6 .mu.m or less is formed on a silicon substrate via a silicon oxide film. An npn bipolar transistor with a low withstand voltage and an IGBT with a high withstand voltage are formed in the active layer. The two devices are insulated and isolated from each other through a trench. The bipolar transistor has an n-type well layer formed in the surface of the active layer. A p-type well layer is formed in the surface of the n-type well layer. The thickness of the n-type well layer under the p-type well layer is set to be 1 .mu.m or more. A first n.sup.+ -type diffusion layer is formed in the surface of the n-type well layer. A p.sup.+ -type diffusion layer and a second n.sup.+ -type diffusion layer are formed in the surface of the p-type well layer. The n-type well layer and the first n.sup.+ -type diffusion layer serve as a collector region. The p-type well layer and the p.sup.+ -type diffusion layer serve as a base region. The second n.sup.

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants.

Abstract: A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.

Abstract: In a method for the making of a lateral bipolar transistor, the formation of a field oxide layer on the surface of the substrate, between the collector and the emitter of the protection transistor, is avoided. The lateral bipolar transistors made by the disclosed method are advantageously used to protect MOS type integrated circuits against electrical discharges.

Abstract: A current mirror circuit comprises first and second lateral-type bipolar transistors having first and second conductive films each formed via an insulation film, on the portion of the surface of a base region between an emitter region and a collector region. The first and second emitter regions and the first and second collector regions formed in the surface region of the base region separately from each other. A diode is used as a bias circuit. The diode applies a bias voltage corresponding to the output current of the first transistor, that is, the reference current, to the first and second conductive films of the first and second transistors, so that the width of the channel formed in a base region is changed in accordance with the reference current, and therefore the current amplification rate of each transistor can be maintained at a high value even if a large operation current is supplied.

Abstract: A low-noise PNP transistor comprising a cutoff region laterally surrounding the emitter region in the surface portion of the transistor. The cutoff region has such a conductivity as to practically turn off the surface portion of the transistor, so that the transistor operates mainly in the bulk portion. The cutoff region is formed by an N.sup.+ -type enriched base region arranged between the emitter region and the collector region.

Abstract: A bipolar semiconductor integrated circuit has a pnp transistor through which a DC power is supplied from an external DC power to various elements of the bipolar IC and a constant current circuit for turning the pnp transistor on and regulating the base current of the pnp transistor to a constant level causing operation in the saturation range of the pnp transistor.

Abstract: A high-frequency lateral PNP transistor includes a base region laterally delimited by P type emitter and collector regions, and at the top by a surface portion of the N type semiconductor body housing the active area of the transistor. The surface portion delimiting the base region presents no formations of insulating material grown across the surface, so that the width (W.sub.B) of the base region is reduced and ensures optimum dynamic characteristics of the transistor. The base contact may be located directly over the surface portion facing the base region, to reduce the extrinsic base resistance and overall size of the device, or it may be located remotely and connected to the base region by a buried layer and sinker region to further reduce the base width.

Abstract: A semiconductor device has a p-n-p transistor structure having a collector implemented by a p.sup.- -substrate, a base formed as an n-diffused region in the surface region of the substrate, and an emitter formed as a p.sup.+ -diffused region in the first n-diffused layer. The p.sup.- -substrate and the n-base are maintained at a ground level, while the p.sup.+ -collector is maintained at a positive potential for biasing the p-n junction formed between the emitter and the base. The bias potential allows the p-n-p transistor structure to operate in its saturation region to activate the base region to define an enlarged carrier-incresed zone. An analog input pad is located within the carrier-increased zone and protected from a noise propagated from a digital circuit section located outside the carrier-increased zone.

Abstract: A lateral transistor includes a first conductivity type semiconductor substrate, a first second conductivity type region in the substrate, a second second conductivity type region in the substrate spaced from and partially surrounding the first region including a plurality of sides and corners; an electrically insulating film covering the semiconductor substrate and including respective penetrating holes extending to the first and second regions; a first metal film disposed on the insulating film and contacting the second region through a first of the penetrating holes; and a second metal film disposed on the insulating film and contacting the first region through a second of the penetrating holes wherein the first metal film is missing opposite a first of the corners of the second region and the second metal film extends across the second region at the first corner.

Abstract: A pnp-type bipolar transistor includes a highly dop p-conducting emitter zone, a base zone and a buried n-conducting zone below the emitter zone. An additional p-conducting region is connected to the highly doped emitter zone and is disposed between the highly doped emitter zone and the buried zone. A collector zone includes a highly doped collector connection zone and a p-conducting region reaching from the collector connection zone to the buried zone.

Abstract: A high performance, high voltage non-epi bipolar transistor including a substrate (12) with an n-type conductivity well (13) and an insulative layer (14) with first (15), second (17) and third (18) openings exposing the substrate in the well. A first p-type volume (19) surrounding the first and second openings (15, 17) beneath the insulative layer (14), and a second n-type volume (22) surrounding the third opening (18) beneath the insulative layer (14). A p-type intrinsic base (25) in the first opening (15) and in contact with the first volume (19). A p-type extrinsic base (30) in the second opening (17) and in contact with the first volume (19). An n-type collector (32) in the third opening (18) and in contact with the second volume (22), and an n-type emitter layer (27) in the first opening in overlying contact with the intrinsic base (25).

Abstract: A semiconductor device with an expanded range of a recommended condition for an input voltage is disclosed. In embodiment, the semiconductor device having input protection on an input terminal thereto, includes: a semiconductor region having a first conducting type, first and second diffusion regions defined in the semiconductor region and respectively having a second conducting type, and a transistor formed by using the semiconductor region as a base, the first diffusion region as a collector, and the second diffusion region as an emitter. The first diffusion region is connected to one of a high-potential power supply and a low-potential power supply, the second diffusion region is connected to the input terminal, and the semiconductor region is connected to another power supply having a voltage high enough to reverse bias the junction between the semiconductor region and the first diffusion region.

Abstract: A semiconductor device is provided with an emitter area and a collector area of a first conductive type and a base area of a second conductive type, arranged in a horizontal structure. The semiconductor device comprises an area constituting at least a part of the base area, being in contact with a part of the base area at least positioned between the emitter and collector areas, and having a narrower forbidden band than in the base area.

Abstract: A guard ring with the same conductivity as a device pocket surrounds the pocket and a pocket isolation ring to establish a parasitic transistor that conducts current between the guard ring and the pocket when the pocket voltage is driven sufficiently below the substrate voltage. The guard ring is connected to a voltage supply for the circuit which, together with its shorter current path, allows the parasitic transistor to harmlessly divert current away from unwanted inter-pocket parasitic transistors.

Abstract: In production of a Bi-CMOS semiconductor device, when forming a lateral PNP transistor in a bipolar section, an oxide film is deposited on this base area to prevent etching damages such as those in forming an LDD spacer for a MOS section, thus degradation of the lateral PNP bipolar transistor and drop of yield in production thereof being prevented and a high performance (low cost) Bi-CMOS LSI being realized.

Abstract: A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A base electrode (114) is formed over at least one end portion of the base-link diffusion source layer (118) and the exposed portions of the base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to form an intrinsic base region (108), emitter region (126), and emitter electrode (124).

Abstract: A back gate bias voltage is applied to the underside of a lateral bipolar transistor to desensitize a portion of the collector-base depletion region to changes in the collector-base voltage. Emitter-collector current flows through an active base region bypassing the portion of the collector-base depletion region that remains sensitive to the collector bias. This allows for a control over the charge in the active base region by the back gate bias, generally independent of the collector-base bias. The transistor is preferably implemented in a silicon-on-insulator-on-silicon (SOIS) configuration, with the back gate bias applied to a doped silicon substrate. The base doping concentration and the thickness of the underlying insulator are preferably selected to produce an inversion layer in the base region adjacent the insulating layer, thereby reducing the collector access resistance.

Abstract: A lateral transistor (14) is configured as a reverse protection diode that allows low and high current modes of operation while maintaining low forward voltage drop. The base region (38) of the lateral transistor is formed inside a collector ring (34) and adjacent to the emitter region (36). In low current mode, the transistor operates as a conventional diode. In high current mode, the excessive number of minority carriers injected into the base region causes the device to enter conductivity modulation that effectively increases the doping concentration and lowers the bulk resistance. The lower bulk resistance keeps the forward voltage drop low. By having the base region inside the collector ring, the bulk resistance is kept low to aid in the onset of conductivity modulation. Thus, the transition between low current mode and high current mode is minimized.

Abstract: A lateral bipolar transistor comprising a self-aligned polysilicon base contact, and polysilicon emitter and collector contacts is provided. The self-aligned base contact significantly reduces the base width and therefore the base resistance compared with conventional lateral bipolar transistors, thus improving f.sub.t and f.sub.max. The polysilicon emitter and collector contacts improve the emitter efficiency and current gain, and allows for more flexible contact placement. The process is compatible with conventional double-poly bipolar processes.

Abstract: A lateral bipolar transistor and method of making the transistor are disclosed. The device is made by etching a trench around a central region of a semiconductor body. An emitter is buried beneath the surface of this central area and contact to it is made via a self-alignment technique. The collector region of the transistor is contacted through the floor of the trench while the base region of the transistor is contacted in a region that surrounds the trench. The described method is compatible with the simultaneous manufacture of FET devices on the same chip.

Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.

Abstract: The electronic component comprises, topologically integrated within the same semiconductor structure (1), a first semiconductor area (12, 13, 3, 4, 20) capable of forming an insulated-gate field-effect transistor, and a second semiconductor area (12, 20, 18, 19, 11) capable of forming a lateral bipolar transistor, the two areas having a common semiconductor layer (20) in which the channel of the field-effect transistor is capable of being formed and/or the base current of the bipolar transistor is capable of flowing, the two areas being capable together of forming a structure capable of negative dynamic resistance.

Abstract: In an integrated circuit in which a first PN-junction-isolated island may momentarily become forward biased with respect to the surrounding substrate and inject unwanted charge that is collected by second islands adjacent one side of a first island, the injected charge is drawn away from the second islands and to a gatherer-collector island located at another side of the first island. The first island, gatherer-collector island and intervening substrate therebetween serve respectively as the emitter, collector, and base of a protective transistor. This transistor becomes a highly efficient collector of injected charge when the protective-transistor collector is hard wired to ground and the protective-transistor base is hard-wire connected to the substrate portion between the injecting first island and adjacent second island.

Abstract: A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.

Abstract: A transversal bipolar transistor is structured to have a single crystal semiconductor film provided on a single crystal semiconductor region which is provided on a semiconductor substrate. The semiconductor substrate is of a first conductivity type, and the single crystal semiconductor region is of a second conductivity type which is opposite to the first conductivity type. The single crystal semiconductor film is divided in the transversal direction into a central portion of the second conductivity type for a base region and left and right portions of the first conductivity type for emitter and collector regions. The transversal bipolar transistor may be integrated with a vertical bipolar transistor commonly on the semiconductor substrate.

Abstract: Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertically stacked region is fully depleted and thus reduces the parasitic capacitance between the semiconductor device and the well region.

Abstract: A bipolar lateral device is disclosed having a high BV.sub.ceo. The device is formed according to a single polysilicon process. In one embodiment silicide is excluded from the surface of the N+ doped polysilicon protecting the N- base width region of the device and the resulting device has a BV.sub.ceo of 8 to 10 V. In another embodiment, the silicide is excluded from the surface of the polysilicon protecting the n-base width region and the polysilicon is maintained as intrinsic polysilicon. The resulting device has a BV.sub.ceo of about 20 V. The devices are useful as voltage clamping devices in programmable logic circuits which must withstand a collector to emitter reverse bias voltage that is sufficient to program either vertical fuse or lateral fuse devices.

Abstract: A photosensor includes a semiconductor substrate of a first-conductivity type with a photoelectric conversion element such as photodiode thereon. The photodiode has a second, opposite conductivity and is surrounded at all of the bottom and sides by a domain having the second conductivity and a high impurity concentration. A first-conductivity domains forms a junction with the second-conductivity domain, and the photodiode is separated from other semiconductor elements by a first-conductivity domain.

Abstract: A semiconductor device including a vertical transistor, for example of the pnp type, having a p-type substrate (1) which forms the collector, with at its surface an epitaxial n-type layer (3) in which a p-type emitter region (15, 16) is formed, while the portion (9) of the epitaxial layer (3) lying between the emitter (15, 16) and the collector (1) forms the base. In this vertical transistor, the current gain is very strongly increased when the emitter is formed by a first partial emitter region which is weakly p-type doped and which extends below an insulating layer (6) and by a second partial emitter region (16) which is strongly p.sup.++ -type doped and which extends below the contact zone (26) of the emitter defined by an opening in the insulating layer (6). The respective thicknesses and doping levels of the first (15) and second (16) emitter regions are provided such that the first region is transparent to electrons and the second forms a screen against electrons.

Abstract: A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming "well" regions through the collector area. The operation determines the formation of a "collector extension region" extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between IcIsubstrate is incremented from about 8 to about 300 and the Early voltage from about 20V to about 100V. The V.sub.CEO, BV.sub.CBO and BV.sub.CES voltages are also advantageously increased by the presence of said "well" region formed in the collector zone.