Abstract: A matrix converter utilizes a bidirectional lateral insulated gate bipolar transistor (IGBT) including two gate electrodes. The IGBT can conduct in two directions. The matrix converter preferably is a three phase matrix converter including nine bidirectional IGBT switches. The IGBT switches are controlled by a control circuit which includes eighteen control lines, two for each IGBT. Additionally, the bidirectional IGBT can be used in a precharge circuit of a power inverter or in a dynamic brake associated with a motor controller.

Abstract: A semiconductor device in which at least one IIL transistor is formed, the semiconductor device having, a base region (6) provided against a semiconductor substrate (1), a plurality of collector regions (9) formed in the base region (6), each of the collector regions (9) aligning in a direction parallel to a spreading surface of the semiconductor substrate (1), and a metal wiring having a plurality of contact portions (10), each of the contact portions being connected electrically to predetermined one of the collector regions (9), characterized in that, each of the contact portions of the metal wiring (10) is connected electrically to the collector region (9) corresponding thereto via a polysilicon cap (11) formed so as to cover the collector region (9).

Abstract: A semiconductor device with an expanded range of a recommended condition for an input voltage is disclosed. In embodiment, the semiconductor device having input protection on an input terminal thereto, includes: a semiconductor region having a first conducting type, first and second diffusion regions defined in the semiconductor region and respectively having a second conducting type, and a transistor formed by using the semiconductor region as a base, the first diffusion region as a collector, and the second diffusion region as an emitter. The first diffusion region is connected to one of a high-potential power supply and a low-potential power supply, the second diffusion region is connected to the input terminal, and the semiconductor region is connected to another power supply having a voltage high enough to reverse bias the junction between the semiconductor region and the first diffusion region.

Abstract: A logic circuit (3) comprises IIL aggregates (4a, 4b, 4c) each consisting of a plurality of IIL elements. Each of the IIL aggregates (4a, 4b, 4c) is supplied with an injector current (I.sub.inj) from an injector current source (2) through a wiring (5). A monitoring element (6) is formed by utilizing an IIL element which needs the longest time until the injector current therein attains a predetermined value. When the injector current applied to an injector current input end (9) attains the predetermined value, potentials of an output terminal (10) and a reset signal input terminal (7) fall. Therefore, a reset operation is performed in accordance with the IIL element which needs the longest time until the injector current attains the predetermined value.

Abstract: A self aligned lateral BJT is disclosed which has a lightly doped first region of a first conductivity type, e.g., P-type. A heavily doped poly region, of a second conductivity type, e.g., N-type, is provided on a portion of a surface of the first region. A heavily doped second region of the second conductivity type, is disposed in the first region below the poly region. An oxide region is provided on a portion of the first region surface adjacent to the poly region. A third region of the first conductivity type is disposed in the first region adjacent to the second region and below the oxide region. A heavily doped fourth region of the second conductivity type is disposed in the first region adjacent to the third region. The fabrication of the lateral BJT includes the step of forming a poly region on a portion of the first region. Then, the second region is formed by diffusing an impurity from the poly region into the first region. The third region is then formed adjacent to the second region.

Abstract: In production of a Bi-CMOS semiconductor device, when forming a lateral PNP transistor in a bipolar section, an oxide film is deposited on this base area to prevent etching damages such as those in forming an LDD spacer for a MOS section, thus degradation of the lateral PNP bipolar transistor and drop of yield in production thereof being prevented and a high performance (low cost) Bi-CMOS LSI being realized.

Abstract: A high-concentration n-type buffer layer and a low-concentration n-type buffer layer are provided between a p-type collector layer and a high-resistance n-type base layer, and respective impurity concentrations of the low-concentration n-type buffer layer and the high-concentration n-type buffer layer are set so that concentrations of carriers that propagate through the low-concentration n-type buffer layer and the high-concentration n-type buffer layer are in excess of the respective impurity concentrations thereof in an ON state. Thus, an insulated gate bipolar transistor having excellent withstand voltage, ON-state voltage and turn-off characteristics is obtained.

Abstract: A bipolar transistor (10) includes a collector region (13), a base region (14) in the collector region (13), and an emitter region (20) in the base region (14). A portion (18) of an electrical conductor (16) is located over a base width (23) of the bipolar transistor (10). The emitter region (20) is self-aligned to the portion (18) of the electrical conductor (16) and is preferably diffused into the base region (14) in order to decrease the base width (23) without relying on extremely precise alignment between base region (14) and the portion (18) of the electrical conductor (16). The portion (18) of the electrical conductor (16) is used to deplete a portion of the base width (23) of the bipolar transistor (10).

Abstract: A process for fabricating a BJT device on a semiconductor substrate is disclosed. The substrate serves as the collector. The process comprises the steps of, first, forming a shielding layer over the designated location over the surface of the substrate for defining the active region. The process further utilizes the shielding layer as the shielding mask for implanting impurities of into the substrate for forming an doped region. Then, a first field oxide layer is formed over the doped region and then removed. Sidewall spacers for the shielding layer are then formed. The process then utilizes the shielding layer and the sidewall spacers as the shielding mask for implanting impurities into portions of the doped region, forming a heavily-doped region, and the remaining portion of the doped region defines the base region. A second field oxide layer is then formed over the heavily-doped region. The sidewall spacers are then removed to form trenches in the places of the sidewall spacers.

Abstract: This transistor is a pnp transistor having a heterojunction of p-type diamond (or BP.sub.x N.sub.1-x, 6HSiC) and n-type SiC (3CSiC)and having a structure in which a p.sup.+ -SiC (3CSiC ) layer, a p-SiC (3CSiC) layer, an n.sup.+ -SiC (3CSiC) layer, a p-diamond (or BP.sub.x N.sub.1-x, 6HSiC ) layer, and a p.sup.+ -diamond (or BP.sub.x N.sub.1-x, 6HSiC) layer are formed on a substrate, and a collector electrode, a base electrode, and an emitter electrode are formed on and electrically connected to the p.sup.+ -Sic layer, the n.sup.+ -SiC layer, and the layer, respectively. This semiconductor device has a high resistance to environment.

Abstract: To provide a type of logic circuit, characterized by the fact that the novel-configuration logic circuit can be easily manufactured in a bipolar process, having a high integration degree and allowing a high-speed operation. For standard longitudinal-type NPN transistor TR0, its emitter E0 is connected to bias terminal BIAS, base B0 is connected to voltage source +Vcc, and collector C0 is connected to base B1 of PNP transistor TR1. For lateral-type PNP transistor TR1, emitter E1 is connected to voltage source Vxx, base B1 is connected to both the collector Co of NPN transistor TR0 and input terminal IN, and collectors C1, C2, C3, . . . Cn are connected to output terminals OUT1, OUT2, PUT3, . . . OUTn, respectively. Schottky diodes SBD1, SBD2, SBD3, . . . SBDn are connected between base B1 and collectors C1, C2, C3, . . . Cn of NPN transistor TR1 with a cathode on the side of the base and with an anode on the side of the collector.

Abstract: Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterned insulating layer as a mask to form first and second pillarss separated by a trench therein; injecting an impurity using a mask to form a collector under the first and second pillars and in the second pillar; depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base; etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; depositing a second oxide layer and a second polysilicon layer thereon; polishing the s

Abstract: A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an injector of an IIL are integrated on a P-type silicon substrate. The emitter leading-out part opening of the superhigh speed vertical NPN transistor and the collector leading-out part opening of the vertical NPN transistor having a reverse direction structure are self-aligned to the base leading-out electrode. Since both the superhigh speed vertical NPN transistor having a reverse direction structure and the superhigh speed vertical NPN transistor are self-aligned, the superhigh speed vertical NPN transistor and the IIL device may be integrated on the same chip. In addition, the intrinsic base layer of the vertical NPN transistor having a reverse direction structure is deeper in junction than the base layer of the polysilicon emitter electrode for the superhigh speed NPN transistor of self-aligned type.

Abstract: An ESD protection circuit which provides protection for CMOS devices against ESD potentials of up to about 10 kV is provided. The ESD protection circuit is able to provide protection against both positive-going and negative-going high energy electrical transients, and is able to maintain a high impedance state when driven to a voltage beyond the supply rails of CMOS integrated circuit, but less than tile breakdown voltage of the ESD protection circuit. The ESD protection circuit routes currents associated with ESD potentials to a predetermined arbitrary point which may be selected during the fabrication process to meet the needs of a particular application. The structure of the ESD protection circuit permits the holding current to be adjusted to accommodate the current capacity of various external circuits.

Abstract: n type epitaxial layers are formed on the main surface of a p type semiconductor substrate. A field oxide film is selectively formed in the surface of n type epitaxial layers. An n type diffusion region is formed in n type epitaxial layers positioned directly under field oxide film. A base region and a collector region are respectively formed in the surface of n type epitaxial layer positioned between field oxide films. As a result, a semiconductor device having an IIL circuit is obtained which can suppress the parasitic bipolar operation between base regions, reduce the junction capacitance between the base region and the emitter region and which can be reduced in size.

Abstract: A bipolar integrated circuit with N-type wells (2) formed in a P-type substrate (1) includes in first wells, first transistors (EBC), the well of which constitutes the collector. P-type base region (7a) is formed in the first well with an N+ emitter region (8) formed in the base region. In at least a second well forming a collector, a composite second transistor (E'B'C') is constituted by an elemental third transistor (E.sub.1 B.sub.1 C') comprising regions of the same doping level as the first transistor and an elemental fourth transistor (E.sub.2 B.sub.2 C') having a base region (11) with a high doping level with respect to that of the bases of the first transistor. Emitter regions (8b, 12) of the elemental transistors are of the same doping level as that of the first transistors. The emitters and bases of the third and fourth elementary transistors are interconnected and constitute the emitter and the base of the composite second transistor.

Abstract: A process for fabricating lateral bipolar junction transistor semiconductor device. Base and emitter regions are precisely aligned. The resulting lateral width of the base region of the transistor device is able be precisely controlled. A heavily-doped implantation region is formed underneath the base region of the transistor structural configuration such that electron carriers in the transistor are prevented from escaping from beneath the base region of the transistor.

Abstract: To provide a type of logic circuit, characterized by the fact that the novel-configuration logic circuit can be easily manufactured in a bipolar process, having a high integration degree and allowing a high-speed operation. For standard longitudinal-type NPN transistor TR0, its emitter E0 is connected to bias terminal BIAS, base B0 is connected to voltage source+Vcc, and collector C0 is connected to base B1 of PNP transistor TR1. For lateral-type PNP transistor TR1, emitter E1 is connected to voltage source Vxx, base B1 is connected to both the collector Co of NPN transistor TR0 and input terminal IN, and collectors C1, C2, C3, . . . Cn are connected to output terminals OUT1, OUT2, PUT3, . . .OUTn, respectively. Schottky diodes SBD1, SBD2, SBD3, . . .SBDn are connected between base B1 and collectors C1, C2, C3, . . . Cn of NPN transistor TR1 with a cathode on the side of the base and with an anode on the side of the collector.

Abstract: There is provided a high-speed heterojunction transistor which is excellent in heat and radiation resistances with its emitter injection efficiency improved due to heterojunction. A .beta. silicon carbide layer (44) acting as base region is grown on an .alpha. silicon carbide substrate (42) acting as emitter region. Due to the difference in forbidden band between the .alpha. silicon carbide substrate (42) and the .beta. silicon carbide layer (44), heterojunction can be obtained. Because the .alpha. silicon carbide substrate (42) has a wider forbidden band, emitter efficiency is improved, allowing a high-speed transistor to be realized. Further, the device is made of silicon carbide, it is excellent in heat and radiation resistances. This invention may be used in an embodiment in which a heterojunction bipolar transistor or a heterojunction IIL is manufactured.

Abstract: A lateral pnp transistor for use in programmable logic arrays. The lateral pnp has a layer of oxide disposed between a polysilicon layer and the base along the base width. The oxide layer prevents diffusion of the N+ dopant contained in the polysilicon layer into the N- base region. The base region thus remains N- and the resulting transistor has improved breakdown voltage characteristics while retaining the speed advantages of polysilicon contact layers. The lateral pnp transistor is manufactured by a method which requires minimal deviation from other methods used to manufacture lateral pnp transistors.

Abstract: A lateral transistor includes a semiconductor substrate, a buried layer formed on the semiconductor substrate, an epitaxial layer formed on the buried layer in such a manner that the epitaxial layer is a p-type or n-type (first conductivity-type), a diffusion zone having a second conductivity-type opposite to the first conductivity-type and including an emitter zone and collector zone formed on the epitaxial layer, and a base zone. The base zone includes an epitaxial layer interposed between the emitter zone and the collector zone. The collector zone is formed within a well zone in such a manner that the well zone has the same type conductivity as the collector zone and a lower concentration than the collector zone.

Abstract: There is disclosed a heterojunction bipolar transistor (HBT) which operates as either the emitter top mode performance or the collector top mode performance and also operates for low power dissipation due to lower ON voltages. A high gain, ultra-high speed semiconductor device is also disposed which includes a collector top type pnp HBT as a switching transistor and a lateral npn bipolar transistor as a current injection source, together with an integration method thereof which meets high density requirement with simple processes. The HBT is implemented with an InP substrate and a collector or emitter layer of p type In.sub.x Al.sub.1-x As lattice matched at least to the InP substrate, a base layer of n type In.sub.x Ga.sub.1-x As, a first spacer layer interposed between the base and collector and a second spacer layer between the base and emitter, both the spacer layers being made of p type In.sub.x Ga.sub.

Abstract: A bipolar transistor of the multi-emitter type which is provided with a large number of emitter diffusion layers formed in the two-dimensionally arranged state on a base diffusion layer of a substrate, a large number of emitter electrode films formed respectively correspondingly on the emitter diffusion layers, a base electrode film formed on the base diffusion layer, and a collector electrode film formed on the substrate, and the transistor is further provided with a wiring film commonly connected to the large number of emitter electrode films except at least one of the emitter electrode films.

Abstract: A bipolar memory array and memory cell. The memory cell has a pair of cross coupled NPN storage transistors and a pair of PNP load transistors. The collector of each of the load transistors is connected to one of the storage transistors. A base, common to both load transistors, are connected to a drain line. The word line is connected to an emitter common to both of the load transistors. The cell is connected to a bit line pair through Schottky Barrier Diodes (SBD's) or, alternatively, through emitters of transistors which share a common base and a common collector with the cross coupled storage transistors.

Abstract: A C-up HBT is made to operate in the microwave/millimeter frequency range by self-aligning the collector uprisers on the base relative to proton damaged emitter regions and the base contacts which minimizes carrier injection into the extrinsic base. The use of about 7-10% indium in the indium gallium arsenide base is sufficient to stop the FREON-12 etch at the base after totally etching through the collector and single self-aligning mask.

Abstract: In one embodiment, this method forms PNP and NPN transistors in a same epitaxial layer. The P-type regions for both the PNP and the NPN transistors are initially defined using a single masking step. Therefore, the emitter and collector region pattern for the PNP transistor is self-aligned with the base region of the NPN transistor. All the defined regions are then doped to achieve a desired base region concentration. A next masking step forms a layer of resist over the base region, and the remainder of the previous masking pattern is retained to define the emitter and collector regions of the PNP transistor. P-type dopants are then implanted in the previously defined emitter and collector regions to form the heavily doped P++ emitter and collector regions of the PNP transistor. Thus, the P++ emitter and collector regions of the PNP transistor will be self-aligned with the P-type base region of the NPN transistor.

Abstract: A lateral PNP transistor having either of the collector or the emitter diffusion layers layered with an n.sup.+ type diffusion layer, is shown. The added layer serves to increase the static electricity withstand stress along a transistor discharging path. A low withstand stress contributes to transistor damage at high breakdown voltages. When an n.sup.+ diffusion layer is formed within a diffusion layer in a lateral PNP transistor the transistor behaves as a combination of two transistors, PNP and NPN, selectively configured.

Abstract: The present invention provides a P-N-P diamond transistor and a method of manufacture thereof. The transistor comprises a diamond substrate having two p-type semiconducting regions separated by an insulating region with an n-type semi-conducting layer established by chemical vapour deposition. Preferably the p-type regions are obtained by doping with boron and controlling the concentration of nitrogen impurities by the use of nitrogen getters. The n-type layer preferably contains phosphorus.