Abstract: In a GaN-based semiconductor device, an active layer of a GaN-based semiconductor is formed on a silicon substrate. A trench is formed in the active layer and extends from a top surface of the active layer to a depth reaching the silicon substrate. A first electrode is formed on an internal wall surface of the trench and extends from the top surface of the active layer to the silicon substrate. A second electrode is formed on the active layer to define a current path between the first electrode and the second electrode via the active layer in an on-state of the device. A bottom electrode is formed on a bottom surface of the silicon substrate and defines a bonding pad for the first electrode. The first electrode is formed of metal in direct ohmic contact with both the silicon substrate and the active layer.

Abstract: A nitride semiconductor device has a nitride semiconductor layer structure. The structure includes an active layer of a quantum well structure containing an indium-containing nitride semiconductor. A first nitride semiconductor layer having a band gap energy larger than that of the active layer is provided in contact with the active layer. A second nitride semiconductor layer having a band gap energy smaller than that of the first layer is provided over the first layer. Further, a third nitride semiconductor layer having a band gap energy larger than that of the second layer is provided over the second layer.

Abstract: Disclosed are an Indium Tin Oxide (ITO) film, wherein nitrogen-containing compounds produced by reactions of nitrogen with at least one atom selected from the group consisting of In, Sn and O atoms which are constitutional elements of ITO, or deposited nitrogen-containing compounds are present on a surface of the ITO film; and a method for preparing an ITO film, comprising the step of treating a surface of the ITO film with nitrogen plasma. An organic elect roluminescent device using the ITO film provided by the present invention as an anode shows a low voltage, a high efficiency and a long lifetime.

Abstract: A field effect transistor includes a Schottky layer; a stopper layer formed of InGaP and provided in a recess region on the Schottky layer; a cap layer provided on the stopper layer and formed of GaAs; and a barrier rising suppression region configured to suppress rising of a potential barrier due to interface charge between the stopper layer and the cap layer. The cap layer includes a high concentration cap layer; and a low concentration cap layer provided directly or indirectly under the high concentration cap layer and having an impurity concentration lower than the high concentration cap layer.

Abstract: A method for manufacturing a light emitting device according to an embodiment of the present invention includes preparing a growth substrate; selectively forming a projection pattern on the growth substrate; forming a first conductive type semiconductor layer on the growth substrate and the projection pattern; forming an active layer on the first conductive type semiconductor layer; forming a second conductive type semiconductor layer on the active layer; and executing an isolation etching for selectively removing the first conductive type semiconductor layer, the active layer, and the second conductive type semiconductor layer including the projection pattern.

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate.

Abstract: Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.

Abstract: Disclosed is a technique capable of preventing occurrence of warping in a nitride compound semiconductor layer, and by which a nitride compound semiconductor layer having small variations in the in-plane off angle can be grown with good reproducibility. Specifically disclosed is a method for producing a nitride compound semiconductor substrate using an HVPE process, wherein a low-temperature protective layer is formed on a rare earth perovskite substrate at a first growth temperature (a first step), and a thick layer composed of a nitride compound semiconductor is formed on the low-temperature protective layer at a second growth temperature that is higher than the first growth temperature (a second step). In the first step, the supply amounts of HCl and NH3 are controlled so that the supply ratio of HCl to NH3, namely the supply ratio III/V is 0.016-0.13, and the low-temperature protective layer has a film thickness of 50-90 nm.

Abstract: Methods for integrating wide-gap semiconductors with synthetic diamond substrates are disclosed. Diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited or formed on a layered structure including at least one layer of gallium nitride, aluminum nitride, silicon carbide, or zinc oxide. The resulting structure is a low stress process compatible with wide-gap semiconductor films, and may be processed into optical or high-power electronic devices. The diamond substrates serve as heat sinks or mechanical substrates.

Abstract: A method according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor layer from a gas containing gallium, a gas containing nitrogen, and a gas containing indium. The concentration of indium in the III-nitride semiconductor structure is greater than zero and less than 1020 cm?3. A structure according to embodiments of the invention includes a super lattice of alternating first and second III-nitride layers. The first layers are more highly doped than the second layers. The average dopant concentration in the super lattice is less than 1020 cm?3.

Abstract: The present invention provides a method for producing a trialkyl gallium comprising the steps of reacting gallium, magnesium, and an alkyl halide in an ether, and diluting during the reaction the reaction system with an ether; a method for producing a trialkyl gallium comprising the steps of heating in a vacuum a mixture of magnesium and molten gallium, and reacting the mixture with an alkyl halide in a solvent; and a method for producing a trialkyl gallium comprising the step of reacting an alkyl metal with an alkylgallium halide compound represented by the formula Ga2RmX6?m wherein R is a methyl or ethyl group, X is a halogen atom, and m is an integer from 1 to 5.

Abstract: To improve an adhesion to a substrate holder, and improve a device production yield by uniformizing a temperature distribution in a surface of a substrate and uniformizing characteristics such as a film thickness.

Abstract: A method for producing a compound semiconductor crystal, includes; a sacrificial layer formation step of forming a sacrificial layer containing Cx1Siy1Gez1Sn1-x1-y1-z1 (0?x1<1, 0?y1?1, 0?z1?1, and 0<x1+y1+z1?1), on a base wafer whose surface is made of a silicon crystal; a crystal formation step of forming, on the sacrificial layer, a compound semiconductor crystal lattice-matching or pseudo lattice-matching the sacrificial layer; and a crystal removal step of removing the compound semiconductor crystal from the base wafer, by etching the sacrificial layer.

Abstract: A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.

Abstract: A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.

Abstract: There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.

Abstract: A group III nitride crystal substrate is provided wherein, a uniform distortion at a surface layer of the crystal substrate is equal to or lower than 1.9×10?3, and wherein the main surface has a plane orientation inclined in a <11-20> direction at an angle equal to or greater than 10° and equal to or smaller than 81° with respect to one of (0001) and (000-1) planes of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.

Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.

Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).

Abstract: A solid-state far ultraviolet light emitting element is formed by a hexagonal boron nitride single crystal, excited by electron beam irradiation to emit far ultraviolet light having a maximum light emission peak in a far ultraviolet region at a wavelength of 235 nm or shorter.

Abstract: Semipolar wurtzite Group III nitride-based semiconductor layers and semiconductor components based thereon are described. Group III nitride layers have a broad range of applications in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and, more recently, Si(111). The layers obtained are generally polar or have c-axis orientation in the direction of growth. For many applications in the field of optoelectronics, as well as acoustic applications in SAWs, the growth of non-polar or semipolar Group III nitride layers is interesting or necessary. The process according to the invention permits simple and inexpensive growth of polarisation-reduced Group III nitride layers without prior structuring of the substrate.

Abstract: A gallium nitride crystal with a polyhedron shape having exposed {10-10} m-planes and an exposed (000-1) N-polar c-plane, wherein a surface area of the exposed (000-1) N-polar c-plane is more than 10 mm2 and a total surface area of the exposed {10-10} m-planes is larger than half of the surface area of (000-1) N-polar c-plane. The GaN bulk crystals were grown by an ammonothermal method with a higher temperature and temperature difference than is used conventionally, and using an autoclave having a high-pressure vessel with an upper region and a lower region. The temperature of the lower region of the high-pressure vessel is at or above 550° C., the temperature of the upper region of the high-pressure vessel is set at or above 500° C., and the temperature difference between the lower and upper regions is maintained at or above 30° C. GaN seed crystals having a longest dimension along the c-axis and exposed large area m-planes are used.

Abstract: There are provided a semiconductor device of low cost and high quality, a combined substrate used for manufacturing the semiconductor device, and methods for manufacturing them. The method for manufacturing the semiconductor device includes the steps of: preparing a single-crystal semiconductor member; preparing a supporting base; connecting the supporting base and the single-crystal semiconductor member to each other through a connecting layer containing carbon; forming an epitaxial layer on a surface of the single-crystal semiconductor member; forming a semiconductor element using the epitaxial layer; separating the single-crystal semiconductor member from the supporting base by oxidizing and accordingly decomposing the connecting layer after the step of forming the semiconductor element; and dividing the single-crystal semiconductor member separated from the supporting base.

Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.

Abstract: A method for growing an In(x)Al(y)Ga(1?x?y)N layer (where x is greater than zero and less than or equal to one, y is greater than or equal to zero and less than or equal to one and the sum of x and y is less than or equal to one). The method includes supplying plasma-activated nitrogen atoms as a source of nitrogen for the In(x)Al(y)Ga(1?x?y)N layer to a growth surface, where a flux of the plasma-activated nitrogen atoms supplied to the growth surface is at least four times higher than a total flux of aluminium and gallium atoms also supplied to the growth surface, where either the aluminium or gallium flux may or may not be zero; and simultaneously supplying indium atoms and nitrogen-containing molecules to the growth surface.

Abstract: Provided are a high-quality non-polar/semi-polar semiconductor device having reduced defect density of a nitride semiconductor layer and improved internal quantum efficiency and light extraction efficiency, and a manufacturing method thereof. The method for manufacturing a semiconductor device is to form a template layer and a semiconductor device structure on a sapphire, SiC or Si substrate having a crystal plane for a growth of a non-polar or semi-polar nitride semiconductor layer. The manufacturing method includes: forming a nitride semiconductor layer on the substrate; performing a porous surface modification such that the nitride semiconductor layer has pores; forming the template layer by re-growing a nitride semiconductor layer on the surface-modified nitride semiconductor layer; and forming the semiconductor device structure on the template layer.

Abstract: A device includes a silicon substrate, and a III-V compound semiconductor region over and contacting the silicon substrate. The III-V compound semiconductor region has a U shaped interface with the silicon substrate, with radii of the U shaped interface being smaller than about 1,000 nm.

Abstract: A method for growth of indium-containing nitride films is described, particularly a method for fabricating a gallium, indium, and nitrogen containing material. On a substrate having a surface region a material having a first indium-rich concentration is formed, followed by a second thickness of material having a first indium-poor concentration. Then a third thickness of material having a second indium-rich concentration is added to form a sandwiched structure which is thermally processed to cause formation of well-crystallized, relaxed material within a vicinity of a surface region of the sandwich structure.

Abstract: A nitride-based semiconductor device according to the present disclosure includes a nitride-based semiconductor multilayer structure 20 with a p-type semiconductor region, of which the surface 12 defines a tilt angle of one to five degrees with respect to an m plane, and an electrode 30, which is arranged on the p-type semiconductor region. The p-type semiconductor region is made of an AlxInyGazN (where x+y+z=1, x?0, y?0 and z?0) semiconductor layer 26. The electrode 30 includes an Mg layer 32, which is in contact with the surface 12 of the p-type semiconductor region, and a metal layer 34 formed on the Mg layer 32. The metal layer 34 is formed from at least one metallic element that is selected from the group consisting of Pt, Mo and Pd.

Abstract: To provide a nitride semiconductor crystal, comprising: laminated homogeneous nitride semiconductor layers, with a thickness of 2 mm or more, wherein the laminated homogeneous nitride semiconductor layers are constituted so that a nitride semiconductor layer with low dopant concentration and a nitride semiconductor layer with high dopant concentration are alternately laminated by two cycles or more.

Abstract: A nitride semiconductor substrate is featured in comprising: a GaN semiconductor layer grown on a base layer, which has a substantially triangular cross-section along the thickness direction thereof, a periodic stripe shapes, and uneven surfaces arranged on the stripes inclined surfaces; and an overgrown layer composed of AlGaN or InAlGaN on the GaN semiconductor layer.

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

Abstract: Manufacturing an III-V engineered substrate involves providing a base substrate comprising an upper layer made of a first III-V compound with a <110> or a <111> crystal orientation, forming an intermediate layer comprising at least a buffer layer of a second III-V compound, wherein the intermediate layer is overlying and in contact with the upper layer of the base substrate. Then a pseudomorphic passivation layer made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer. This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices.

Abstract: The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.

Abstract: A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer.

Abstract: A laminated substrate system containing a metamorphic transition region (2) made from multiple and alternating layers of AlxGa1-xN (5) and the supporting substrate material (4) (or a material having the same general chemical composition thereto). A III-Nitrides semiconductor device (2) with a low dislocation density is formed on top of the laminated substrate system. The multiple layers (4,5) of the metamorphic transition region form a superlattice structure whose lattice constant and structure changes along its growth direction from that of the supporting substrate (1) (in the vicinity of the supporting substrate) to that of the device (3) (in the vicinity of the device).

Abstract: The present invention provides nitride semiconductors having a moderate density of basal plane stacking faults and a reduced density of threading dislocations, various products based on, incorporating or comprising the nitride semiconductors, including without limitation substrates, template films, templates, heterostructures with or without integrated substrates, and devices, and methods for fabrication of templates and substrates comprising the nitride semiconductors.

Abstract: A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 11} GaN films deposited on {100} MgAl2O4 spinel substrate miscut in the <011> direction. Mg atoms may be intentionally incorporated in the growing semipolar nitride thin film to introduce available electronic states in the band structure of the semiconductor crystal, resulting in p-type conductivity. Other impurity atoms, such as Zn or C, which result in a similar introduction of suitable electronic states, may also be used.

Abstract: A semiconductor device has a satisfactory ohmic contact on a p-type principal surface tilting from a c-plane. The principal surface 13a of a p-type semiconductor region 13 extends along a plane tilting from a c-axis (axis <0001>) of hexagonal group-III nitride. A metal layer 15 is deposited on the principal surface 13a of the p-type semiconductor region 13. The metal layer 15 and the p-type semiconductor region 13 are separated by an interface 17 such that the metal layer functions as a non-alloy electrode. Since the hexagonal group-III nitride contains gallium as a group-III element, the principal surface 13a comprising the hexagonal group-III nitride is more susceptible to oxidation compared to the c-plane of the hexagonal group-III nitride. The interface 17 avoids an increase in amount of oxide after the formation of the metal layer 15 for the electrode.

Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm).

Abstract: Regarding a base substrate, a plurality of steps are formed stepwise on the principal surface (c-face). Each step has a height difference of 10 to 40 ?m, and an edge is formed parallel to an a-face of a hexagonal crystal of GaN. Meanwhile, the terrace width of each step is set at a predetermined width. The predetermined width is set in such a way that after a GaN crystal is grown on the principal surface of the base substrate, the principal surface is covered up with grain boundaries when the grown GaN crystal is observed from the surface side. The plurality of steps can be formed through, for example, dry etching, sand blasting, lasing, and dicing.

Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an ?-axis direction comprising a 0.15° or greater miscut angle towards the ?-axis direction and a less than 30° miscut angle towards the ?-axis direction.

Abstract: A manufacturing method of a group III nitride semiconductor includes the steps of: depositing a metal layer on an AlN template substrate or an AlN single crystal substrate formed by depositing an AlN single crystal layer with a thickness of not less than 0.1 ?m nor more than 10 ?m on a substrate made of either one of sapphire, SiC, and Si; forming a metal nitride layer having a plurality of substantially triangular-pyramid-shaped or triangular-trapezoid-shaped microcrystals by performing a heating nitridation process on the metal layer under a mixed gas atmosphere of ammonia; and depositing a group III nitride semiconductor layer on the metal nitride layer.

Abstract: A method for enhancing light extraction efficiency of GaN light emitting diodes is disclosed. By cutting off a portion from each end of bottom of a sapphire substrate or forming depressions on the bottom of the substrate and forming a reflector, light beams emitted to side walls of the substrate can be guided to the light emitting diodes.

Abstract: Methods and apparatus for producing a gallium nitride semiconductor on insulator structure include: bonding a single crystal silicon layer to a transparent substrate; and growing a single crystal gallium nitride layer on the single crystal silicon layer.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.

Abstract: A light emitting semiconductor device (401) has an active region (405) formed of Bismuth (Bi) and one or more other group V elements. In a particular embodiment the III-V material comprises Gallium Arsenide (GaAs) in addition to Bismuth. The inclusion of Bismuth in the III-V material raises the spin-orbit splitting energy of the material while reducing the band gap. When the spin-orbit splitting energy exceeds the band gap, Auger recombination processes are inhibited, reducing the sensitivity of the light emitting semiconductor device (401) to changes in ambient temperature.

Abstract: A light-emitting device package structure includes a carrier, at least one light-emitting device and a magnetic element. The magnetic element aids in enhancing overall luminous output efficiency.

Abstract: A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 102 microns per hour.