Abstract: To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.

Abstract: A semiconductor device may include a silicon (Si) substrate including a hole, a hard mask around the hole on the Si substrate, a first material layer filling the hole and on a portion of the hard mask, an upper material layer on the first material layer, and a device layer on the upper material layer. The first material layer may be a Group III-V material layer. The Group III-V material layer may be a Group III-V compound semiconductor layer. The upper material layer may be a portion of the first material layer. The upper material layer may include one of a same material as the first material layer and a different material from the first material layer.

Abstract: An enhancement mode gallium nitride (GaN) transistor with a Mg doped layer and a Mg growth interruption (diffusion barrier) layer to trap excess or residual Mg dopant. The Mg growth interruption (diffusion barrier) layer is formed by growing GaN, stopping the supply of gallium while maintaining a supply of ammonia or other nitrogen containing source to form a layer of magnesium nitride (MgN), and then resuming the flow of gallium to form a GaN layer to seal in the layer of MgN.

Abstract: A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.

Abstract: A method of selective dry etching of N-face (Al,In,Ga)N heterostructures through the incorporation of an etch-stop layer into the structure, and a controlled, highly selective, etch process. Specifically, the method includes: (1) the incorporation of an easily formed, compatible etch-stop layer in the growth of the device structure, (2) the use of a laser-lift off or similar process to decouple the active layer from the original growth substrate, and (3) the achievement of etch selectivity higher than 14:1 on N-face (Al,In,Ga)N.

Abstract: Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.

Abstract: A bonded substrate, the surface roughness of which is reduced, and a method of manufacturing the same. The bonded substrate includes a base substrate and an intermediate layer disposed on the base substrate. The intermediate layer has a greater bubble diffusivity than the base substrate. A thin film layer is bonded onto the intermediate layer, and has a different chemical composition from the base substrate.

Abstract: The invention relates to a monolithic integrated semiconductor structure comprising a carrier layer on the basis of doped Si or doped GaP and a III/V semiconductor disposed thereupon and having the composition GaxInyNaAsbPcSbd, wherein x=70-100 mole-%, y=0-30 mole-%, a=0.5-15 mole-%, b=67.5-99.5 mole-%, c=0-32.0 mole-% and d=0-15 mole-%, wherein the total of x and y is always 100 mole-%, wherein the total of a, b, c and d is always 100 mole-%, and wherein the ratio of the totals of x and y on the one hand, and of a to d on the other hand, is substantially 1:1, to methods for the production thereof, new semiconductors, the use thereof for the production of luminescence diodes and laser diodes or also modulator and detector structures, which are monolithically integrated in integrated circuits on the basis of the Si or GaP technology.

Abstract: A method of manufacturing a group III nitride semiconductor substrate includes the growth step of epitaxially growing a first group III nitride semiconductor layer on an underlying substrate, and the process step of forming a first group III nitride semiconductor substrate by cutting and/or surface-polishing the first group III nitride semiconductor layer. In the growth step, at least one element selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an impurity element by at least 1×1017 cm?3 to the first group III nitride semiconductor layer. A group III nitride semiconductor substrate having controlled resistivity and low dislocation density and a manufacturing method thereof can thus be provided.

Abstract: A process for preparing smoothened III-N, in particular smoothened III-N substrate or III-N template, wherein III denotes at least one element of group III of the Periodic System, selected from Al, Ga and In, utilizes a smoothening agent comprising cubic boron nitride abrasive particles. The process provides large-sized III-N substrates or III-N templates having diameters of at least 40 mm, at a homogeneity of very low surface roughness over the whole substrate or wafer surface. In a mapping of the wafer surface with a white light interferometer, the standard deviation of the rms-values is 5% or lower, with a very good crystal quality at the surface or in surface-near regions, measurable, e.g., by means of rocking curve mappings and/or micro-Raman mappings.

Abstract: Provided is an epitaxial substrate using a silicon substrate as a base substrate. An epitaxial substrate, in which a group of group-III nitride layers are formed on a (111) single crystal Si substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a surface of the substrate, includes: a first group-III nitride layer made of AlN with many defects configured of at least one kind from a columnar or granular crystal or domain; a second group-III nitride layer whose interface with the first group-III nitride layer is shaped into a three-dimensional concave-convex surface; and a third group-III nitride layer epitaxially formed on the second group-III nitride layer as a graded composition layer in which the proportion of existence of Al is smaller in a portion closer to a fourth group-III nitride.

Abstract: A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. The thickness of each sacrificial material layer of the stack increases upwards from the sacrificial material layer that is formed nearest to the base substrate. Because of this difference in thicknesses, each sacrificial material layer etches at different rates, with thicker sacrificial material layers etching faster than thinner sacrificial material layers. An etch is performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially.

Abstract: In one embodiment, a semiconductor structure is provided which includes a base substrate, and a multilayered stack located on the base substrate. The multilayered stack includes, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness.

Abstract: High temperature semiconducting materials in a freestanding epitaxial chip enables the use of high temperature interconnect and bonding materials. Process materials can be used which cure, fire, braze, or melt at temperatures greater than 400 degrees C. These include, but are not limited to, brazing alloys, laser welding, high-temperature ceramics and glasses. High temperature interconnect and bonding materials can additionally exhibit an index of refraction intermediate to that of the freestanding epitaxial chip and its surrounding matrix. High index, low melting point glasses provide a hermetic seal of the semiconductor device and also index match the freestanding epitaxial chip thereby increasing extraction efficiency. In this manner, a variety of organic free semiconducting devices, such as solid-sate lighting sources, can be created which exhibit superior life, efficiency, and environmental stability.

Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, an emitter device can include monolithic quantum well (QW) lasers directly disposed on a SOI or silicon substrate for waveguide coupled integration. In another exemplary embodiment, a superlattice (SL) photodetector and its focal plane array can include a III-Sb active region formed over a large GaAs substrate using SLS technologies.

Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.

Abstract: III-nitride crystal composites are made up of especially processed crystal slices cut from III-nitride bulk crystal having, ordinarily, a {0001} major surface and disposed adjoining each other sideways, and of III-nitride crystal epitaxially on the bulk-crystal slices. The slices are arranged in such a way that their major surfaces parallel each other, but are not necessarily flush with each other, and so that the [0001] directions in the slices are oriented in the same way.

Abstract: Bulk mono-crystalline gallium-containing nitride, grown on the seed at least in the direction essentially perpendicular to the direction of the seed growth, essentially without propagation of crystalline defects as present in the seed, having the dislocation density not exceeding 104/cm2 and considerably lower compared to the dislocation density of the seed, and having a large curvature radius of the crystalline lattice, preferably longer than 15 m, more preferably longer than 30 m, and most preferably of about 70 m, considerably longer than the curvature radius of the crystalline lattice of the seed.

Abstract: Provided are a crystalline film in which variations in the crystal axis angle after separation from a substrate for epitaxial growth have been eliminated, and various devices in which the properties thereof have been improved by including the crystalline film. And the crystalline film has a thickness of 300 ?m or more and 10 mm or less and reformed region pattern is formed in an internal portion of the crystalline film.

Abstract: Systems and methods for preparing freestanding films using laser-assisted chemical etch (LACE), and freestanding films formed using same, are provided. In accordance with one aspect a substrate has a surface and a portion defining an isotropically defined cavity; and a substantially continuous film is disposed at the substrate surface and spans the isotropically defined cavity. In accordance with another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a film is disposed at the substrate surface and spans the isotropically defined cavity, the film including at least one of hafnium oxide (HfO2), diamond-like carbon, graphene, and silicon carbide (SiC) of a predetermined phase. In accordance with still another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a multi-layer film is disposed at the substrate surface and spans the isotropically defined cavity.

Abstract: A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate. In an illustrative implementation, a laser diode is oriented on a GaN substrate wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001>direction predominantly towards either the <11 20> or the <1 100> family of directions. For a <11 20> off-cut substrate, a laser diode cavity may be oriented along the <1 100> direction parallel to lattice surface steps of the substrate in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For a <1 100> off-cut substrate, the laser diode cavity may be oriented along the <1 100> direction orthogonal to lattice surface steps of the substrate in order to provide a cleaved laser facet that is aligned with the surface lattice steps.

Abstract: Provided is a biological component detection device with which a biological component can be detected at high sensitivity by using an InP-based photodiode in which a dark current is reduced without using a cooling mechanism and the sensitivity is extended to a wavelength of 1.8 ?m or more. An absorption layer 3 has a multiple quantum well structure composed of group III-V semiconductors, a pn-junction 15 is formed by selectively diffusing an impurity element in the absorption layer, and the concentration of the impurity element in the absorption layer is 5×1016/cm3 or less, the diffusion concentration distribution control layer has an n-type impurity concentration of 2×1015/cm3 or less before the diffusion, the diffusion concentration distribution control layer having a portion adjacent to the absorption layer, the portion having a low impurity concentration.

Abstract: Disclosed herein is a nitride based semiconductor device. The nitride based semiconductor device includes: a base substrate; an epitaxial growth layer disposed on the base substrate and having a defect generated due to lattice disparity with the base substrate; a leakage current barrier covering the epitaxial growth layer while filling the defect; and an electrode part disposed on the epitaxial growth layer.

Abstract: A group III nitride composite substrate includes a support substrate, an oxide film formed on the support substrate, and a group III nitride layer formed on the oxide film. The oxide film may be a film selected from the group consisting of a TiO2 film and a SrTiO3 film, and an impurity may be added to the oxide film. Accordingly, the group III nitride composite substrate having a high bonding strength between the support substrate and the group III nitride layer is provided.

Abstract: Semiconductor structures including one, or more, III-nitride material regions (e.g., gallium nitride material region) and methods associated with such structures are provided. The III-nitride material region(s) advantageously have a low dislocation density and, in particular, a low screw dislocation density. In some embodiments, the presence of screw dislocations in the III-nitride material region(s) may be essentially eliminated. The presence of a strain-absorbing layer underlying the III-nitride material region(s) and/or processing conditions can contribute to achieving the low screw dislocation densities. In some embodiments, the III-nitride material region(s) having low dislocation densities include a gallium nitride material region which functions as the active region of the device. The low screw dislocation densities of the active device region (e.g., gallium nitride material region) can lead to improved properties (e.g.

Abstract: The invention concerns a method for preparing a NIII-V semiconductor. According to the invention, the method includes at least one step of doping a semiconductor of general formula AlxGa1-xN, wherein the atomic number x represents the number between 0 and 1 with a p-type electron-accepting dopant, as well as a co-doping step with a codopant capable of modifying the structure of the valency band. The invention also concerns a semiconductor as well as its use in electronics or optoelectronics. The invention further concerns a device as well as a diode using such a semiconductor.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.

Abstract: Group III nitride semiconductor crystals of a size appropriate for semiconductor devices and methods for manufacturing the same, Group III nitride semiconductor devices and methods for manufacturing the same, and light-emitting appliances. A method of manufacturing a Group III nitride semiconductor crystal includes a process of growing at least one Group III nitride semiconductor crystal substrate on a starting substrate, a process of growing at least one Group III nitride semiconductor crystal layer on the Group III nitride semiconductor crystal substrate, and a process of separating a Group III nitride semiconductor crystal, constituted by the Group III nitride semiconductor crystal substrate and the Group III nitride semiconductor crystal layer, from the starting substrate, and is characterized in that the Group III nitride semiconductor crystal is 10 ?m or more but 600 ?m or less in thickness, and is 0.2 mm or more but 50 mm or less in width.

Abstract: Provided is a crack-free epitaxial substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a first and a second lamination unit being alternately laminated such that each of an uppermost and a lowermost portion of the buffer layer is formed of the first lamination unit. The first lamination unit is formed of a first and a second composition layer having different compositions being alternately laminated so as to increase the thickness of the second composition layer in a portion more distant from the base substrate side, to thereby cause a compressive strain to exist in the first lamination unit such that it increases in a portion more distant from the base substrate. The second lamination unit is formed as an intermediate layer that is substantially strain-free and formed with a thickness of 15 nm or more and 150 nm or less.

Abstract: Provided is a laminate comprising a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×10? cm or more.

Abstract: A method for forming a nanowhisker of, e.g., a III-V semiconductor material on a silicon substrate, comprises: preparing a surface of the silicon substrate with measures including passivating the substrate surface by HF etching, so that the substrate surface is essentially atomically flat. Catalytic particles on the substrate surface are deposited from an aerosol; the substrate is annealed; and gases for a MOVPE process are introduced into the atmosphere surrounding the substrate, so that nanowhiskers are grown by the VLS mechanism. In the grown nanowhisker, the crystal directions of the substrate are transferred to the epitaxial crystal planes at the base of the nanowhisker and adjacent the substrate surface.

Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.

Abstract: A method of producing a Group-III nitride crystal by coating at least one surface of the seed with a thin wetting layer or film comprised of one or more Group-III and alkali metals.

Abstract: A power semiconductor device and a manufacturing method thereof are provided. The power semiconductor device includes an anode electrode including an anode electrode pad, electrode bus lines connected to a first side and a second side on the anode electrode pad, the electrode bus lines each having a decreasing width in a direction away from the anode electrode pad, and pluralities of first anode electrode fingers and second anode electrode fingers connected with a third side and a fourth side on the anode electrode pad and with both sides of the electrode bus line, a cathode electrode including a first cathode electrode pad and a second cathode electrode pad, a plurality of cathode electrode fingers connected with the first cathode electrode pad, and a plurality of second cathode electrode fingers connected with the second cathode electrode pad, and an insulation layer disposed at an external portion of the anode.

Abstract: A method of forming a semiconductive substrate material for an electronic device including forming a plurality of semiconductive layers on a substrate during a continuous growth process in a reaction chamber, wherein during the continuous growth process, a release layer is formed between a base layer and an epitaxial layer by altering at least one growth process parameter during the continuous growth process. The method also including separating the plurality of semiconductive layers from the substrate.

Abstract: The present invention relates to a method that involves providing a stack of a first substrate and a InGaN seed layer formed on the first substrate, growing an InGaN layer on the InGaN seed layer to obtain an InGaN-on-substrate structure, forming a first mirror layer overlaying the exposed surface of the grown InGaN layer, attaching a second substrate to the exposed surface of the mirror layer, detaching the first substrate from the InGaN seed layer and grown InGaN layer to expose a surface of the InGaN seed layer opposite the first mirror layer, and forming a second mirror layer overlaying the opposing surface of the InGaN seed layer.

Abstract: Gallium nitride material devices and related processes are described. In some embodiments, an N-face of the gallium nitride material region is exposed by removing an underlying region.

Abstract: In one embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a partial vacuum atmosphere at a temperature conducive for air adsorbed molecules to desorb, surface molecule groups to decompose, and elemental Sb to evaporate from a surface of the AlSb crystal and exposing the AlSb crystal to an atmosphere comprising oxygen to form a crystalline oxide layer on the surface of the AlSb crystal. In another embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a non-oxidizing atmosphere at a temperature conducive for decomposition of an amorphous oxidized surface layer and evaporation of elemental Sb from the AlSb crystal surface and forming stable oxides of Al and Sb from residual surface oxygen to form a crystalline oxide layer on the surface of the AlSb crystal.

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and smaller coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area t

Abstract: A method for manufacturing a semiconductor layer according to an embodiment of the present invention comprises preparing a first compound, preparing a second compound, making a semiconductor layer forming solution, and forming a semiconductor layer including a group compound by using this semiconductor layer forming solution. The first compound contains a first chalcogen-element-containing organic compound, a first Lewis base, a I-B group element, and a first III-B group element. The second compound contains an organic ligand and a second III-B group element. The semiconductor layer forming solution contains the first compound, the second compound, and an organic solvent.

Abstract: A compound semiconductor device includes a substrate; and a compound semiconductor multilayer structure which is formed above the substrate and which contains compound semiconductors containing Group III elements, wherein the compound semiconductor multilayer structure has a thickness of 10 ?m or less and a percentage of aluminum atoms is 50% or more of the number of atoms of the Group III elements.

Abstract: A semiconductor device includes a semiconductor substrate formed of at least two kinds of group III elements and nitrogen, an active layer formed on the semiconductor substrate, and a nitride semiconductor layer formed on a surface of the semiconductor substrate and formed between the semiconductor substrate and the active layer. The nitride semiconductor layer is formed of the same constituent elements of the semiconductor substrate. A composition ratio of the lightest element among the group III elements of the nitride semiconductor layer is higher than a composition ratio of the corresponding element of the semiconductor substrate.

Abstract: The present invention describes a hybrid integrated circuit comprising both CMOS and III-V devices, monolithically integrated in a single chip. It allows the almost complete elimination of the contamination issues related to the integration of different technologies, maintaining at the same time a good planarization of the structure. It further simplifies the fabrication process, allowing the growth of high quality III-V materials on (100) silicon substrates lowering the manufacturing cost. Moreover, differently from many prior art attempts, it does not require silicon on insulator technologies and/or other expensive process steps. This invention enables the consolidation on the same integrated circuit of a hybrid switching power converter that takes advantage of the established circuit topologies of CMOS circuitries and of the higher mobility and voltage withstanding of III-V HEMT devices.

Abstract: The method for producing a group III nitride semiconductor crystal comprises preparing a seed crystal having a non-polar plane followed by growing a group III nitride semiconductor from the non-polar plane in a vapor phase, wherein the growing includes growing the group III nitride semiconductor so as to extend in the +C-axis direction of the seed crystal. A group III-V nitride semiconductor crystal having high quality and a large-area non-polar plane can be obtained by the method.

Abstract: According to an embodiment, a semiconductor light emitting device includes a foundation layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The foundation layer has an unevenness having recesses, side portions, and protrusions. A first major surface of the foundation layer has an overlay-region. The foundation layer has a plurality of dislocations including first dislocations whose one ends reaching the recess and second dislocations whose one ends reaching the protrusion. A proportion of a number of the second dislocations reaching the first major surface to a number of all of the second dislocations is smaller than a proportion of a number of the first dislocations reaching the first major surface to a number of all of the first dislocations. A number of the dislocations reaching the overlay-region of the first major surface is smaller than a number of all of the first dislocations.

Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group III-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods.

Abstract: A group III nitride semiconductor free-standing substrate includes an as-grown surface, more than half of a region of the as-grown surface including a single crystal plane. The single crystal plane includes an off-angle inclined in an m-axis or a-axis direction from a C-plane with a group III polarity, or in a c-axis or a-axis direction from an M-plane.

Abstract: Affords methods of manufacturing bulk III-nitride crystals whereby at least the surface dislocation density is low globally. The present III-nitride crystal manufacturing method includes: a step of preparing an undersubstrate (1) containing a III-nitride seed crystal, the III-nitride seed crystal having a matrix (1s), and inversion domains (1t) in which the polarity in the <0001> directions is inverted with respect to the matrix (1s); and a step of growing a III-nitride crystal (10) onto the matrix (1s) and inversion domains (it) of the undersubstrate (1) by a liquid-phase technique; and is characterized in that a first region (10s), being where the growth rate of III-nitride crystal (10) growing onto the matrix (1s) is greater, covers second regions (10t), being where the growth rate of III-nitride crystal (10) growing onto the inversion domains (1t) is lesser.

Abstract: The method for manufacturing a semiconductor device comprises steps of: forming a growth mask with a plurality of openings directly or indirectly upon a substrate that comprises a material differing from GaN-based semiconductor; and growing a plurality of island-like GaN-based semiconductor layers upon the substrate using the growth mask in the (0001) plane orientation in a manner such that the 1-100 direction extends in a direction parallel to the striped openings of the growth mask.