With Specified Crystal Plane Or Axis Patents (Class 257/627)
  • Patent number: 7875960
    Abstract: A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: January 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Louis Lu-Chen Hsu, Jack Allan Mandelman, William Robert Tonti
  • Patent number: 7871876
    Abstract: Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing material that stresses the center semiconductor fin region. The strain inducing material contacts the bulk silicon substrate, wherein the strain inducing material comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: January 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7863713
    Abstract: For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: January 4, 2011
    Assignees: Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Kazufumi Watanabe
  • Patent number: 7863712
    Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane <110> direction of the (011) DSB layer is aligned with an in-plane <110> direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane <100> directions of the (001) base substrate, followed by recrystallization using the base substrate as a template.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Haizhou Yin, John A. Ott, Katherine L. Saenger, Chun-Yung Sung
  • Patent number: 7859086
    Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 ?m. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: December 28, 2010
    Assignee: Samsung LED Co., Ltd.
    Inventors: Cheol Kyu Kim, Yung Ho Ryu, Soo Min Lee, Jong In Yang, Tae Hyung Kim
  • Patent number: 7858992
    Abstract: A nitride semiconductor laser device has a nitride semiconductor substrate that includes a dislocation-concentrated region 102 and a wide low-dislocation region and that has the top surface thereof slanted at an angle in the range of 0.3° to 0.7° relative to the C plane and a nitride semiconductor layer laid on top thereof. The nitride semiconductor layer has a depression immediately above the dislocation-concentrated region, and has, in a region thereof other than the depression, a high-quality quantum well active layer with good flatness and without cracks, a layer that, as is grown, readily exhibits p-type conductivity, and a stripe-shaped laser light waveguide region. The laser light waveguide region is formed above the low-dislocation region. This helps realize a nitride semiconductor laser device that offers a longer life.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: December 28, 2010
    Assignees: Sharp Kabushiki Kaisha, Sumitomo Electric Industries, Ltd.
    Inventors: Yoshihiro Ueta, Teruyoshi Takakura, Takeshi Kamikawa, Yuhzoh Tsuda, Shigetoshi Ito, Takayuki Yuasa, Mototaka Taneya, Kensaku Motoki
  • Publication number: 20100314722
    Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.
    Type: Application
    Filed: February 19, 2009
    Publication date: December 16, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tohru Ishizuka, Nobuhiko Noto, Norihiro Kobayashi, Masatake Nakano
  • Patent number: 7834356
    Abstract: To provide a thin film transistor having a high field effect mobility and a small variation in characteristics thereof, a second amorphous semiconductor layer patterned in a predetermined shape is formed on a first crystalline semiconductor layer 17 for constituting source and drain regions. By irradiating an irradiated region 21 of continuous wave laser beam while scanning along a channel length direction, the second amorphous semiconductor layer is crystallized to form a second crystalline semiconductor layer 22. The first crystalline semiconductor layer 17 is crystallized by selectively adding nickel and therefore, an orientation rate of {111} is increased.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: November 16, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masahiko Hayakawa
  • Patent number: 7834425
    Abstract: The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Meikei Ieong, Xinlin Wang, Min Yang
  • Patent number: 7812398
    Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: October 12, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Saito, Digh Hisamoto, Yoshinobu Kimura, Nobuyuki Sugii, Ryuta Tsuchiya
  • Patent number: 7808082
    Abstract: The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: October 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: Haining Yang, Thomas W. Dyer, Keith Kwong Hon Wong, Chih-Chao Yang
  • Publication number: 20100244054
    Abstract: A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.
    Type: Application
    Filed: March 24, 2010
    Publication date: September 30, 2010
    Applicant: OKI DATA CORPORATION
    Inventors: Mitsuhiko OGIHARA, Tomohiko SAGIMORI, Takahito SUZUKI, Masataka MUTO
  • Publication number: 20100237474
    Abstract: Unpolished semiconductor wafers are produced by: (a) pulling a single crystal of a semiconductor material, (b) grinding the single crystal round, (c) separating a semiconductor wafer from this crystal, (d) rounding the edge of the semiconductor wafer, (e) surface-grinding at least one side of the semiconductor wafer, (f) treating the semiconductor wafer with an etchant, and (g) cleaning the semiconductor wafer. The unpolished semiconductor wafers have, on at least the front side, a reflectivity of 95% or more, a surface roughness of 3 nm or less, have a thickness of 80-2500 ?m, an overall planarity value GBIR of 5 ?m or less with an edge exclusion of 3 mm and a photolithographic resolution of at least 0.8 ?m, and which furthermore contain a native oxide layer with a thickness of 0.5-3 nm on both sides.
    Type: Application
    Filed: June 1, 2010
    Publication date: September 23, 2010
    Applicant: SILTRONIC AG
    Inventors: Wolfgang Hensel, Rudolf Lehner, Helmut Schwenk
  • Patent number: 7800202
    Abstract: In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has a planar structure having a channel region only on the (110) plane. Further, both the transistors are substantially equal to each other in the areas of the channel regions and gate insulating films. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: September 21, 2010
    Assignees: Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto
  • Publication number: 20100233539
    Abstract: A method is described of selectively etching a silicon substrate in small local areas in order to form columns or pillars in the etched surface. The silicon substrate is held in an etching solution of hydrogen fluoride, a silver salt and an alcohol. The inclusion of the alcohol provides a greater packing density of the silicon columns.
    Type: Application
    Filed: January 23, 2007
    Publication date: September 16, 2010
    Inventors: Mino Green, Feng-Ming Liu
  • Patent number: 7795680
    Abstract: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: September 14, 2010
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Huang Liu, Alex K. H. See, James Lee, Johnny Widodo, Chung Woh Lai, Wenzhi Gao, Zhao Lun, Shailendra Mishra, Liang-Choo Hsia
  • Patent number: 7790522
    Abstract: A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Louis C. Hsu, Rajiv V. Joshi, Xu Ouyang
  • Patent number: 7781278
    Abstract: The present invention relates to a field effect transistor (FET) containing a channel extending perpendicularly across at least one V-shaped trench and along the interior surfaces thereof. In one aspect, a semiconductor device is provided that includes a semiconductor substrate having first and second device regions that are isolated from each other by an isolation region. The first device region has a planar surface with a first crystalline orientation, and the second device region has at least one V-shaped trench which has interior surfaces with a second, different crystalline orientation. A first FET is located at the first device region and contains a channel extending along the planar surface of the first device region. A second, complementary FET is located at the second device region and contains a channel extending perpendicularly across the at least one V-shaped trench and along the interior surfaces thereof.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventor: Huilong Zhu
  • Publication number: 20100207136
    Abstract: The present invention provides an inexpensive substrate which can realize m-plane growth of a crystal by vapor phase growth. In a sapphire substrate, an off-angle plane slanted from an m-plane by a predetermined very small angle is prepared as a growth surface, which is a template of the crystal, at the time of growing a crystal of GaN or the like, by a polishing process to prepare a stepwise substrate comprising steps and terraces. According to the above-described configuration, even if an inexpensive sapphire substrate, which normally does not form an m-plane (nonpolar plane) GaN film, is used as a substrate for crystal growth, the following advantages can be attained.
    Type: Application
    Filed: October 19, 2007
    Publication date: August 19, 2010
    Applicants: PANASONIC ELECTRIC WORKS CO., LTD., RIKEN
    Inventors: Robert David Armitage, Yukihiro Kondo, Hideki Hirayama
  • Patent number: 7777306
    Abstract: A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Louis C. Hsu, Rajiv V. Joshi, Xu Ouyang
  • Patent number: 7777305
    Abstract: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al0.25Ga0.75N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al0.25Ga0.75N layer is on (0 0 0 1) plane as a main surface, and concaves are arranged in a checkerboard pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al0.25Ga0.75N layer, and the sides of the concaves are on non-polar surfaces such as (1 1 ?2 0) plane or (1 ?1 0 0) plane.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 17, 2010
    Assignee: Panasonic Corporation
    Inventors: Masayuki Kuroda, Tetsuzo Ueda
  • Publication number: 20100200962
    Abstract: Provided is a method applicable to the production of silicon wafers having crystal orientation <100> or <110> and consisting in specifying wafer-supporting positions on the occasion of heat treatment in a vertical heat treatment furnace as well as a heat treatment jig for use in carrying out that method. It becomes possible to suppress the shear stress which contributes to the extension of the slip generated at each wafer-supporting element contact point as an initiation, suppress slip growth and thus markedly improve the yield of heat-treated silicon wafers. The heat-treated wafer obtained by using the supporting method and the heat treatment jig has few slip, in particular has no long and large slip, and is high in quality.
    Type: Application
    Filed: October 15, 2007
    Publication date: August 12, 2010
    Inventor: Takayuki Kihara
  • Patent number: 7768030
    Abstract: A GaN layer is grown on a sapphire substrate, an SiO2 film is formed on the GaN layer, and a GaN semiconductor layer including an MQW active layer is then grown on the GaN layer and the SiO2 film using epitaxial lateral overgrowth. The GaN based semiconductor layer is removed by etching except in a region on the SiO2 film, and a p electrode is then formed on the top surface of the GaN based semiconductor layer on the SiO2 film, to join the p electrode on the GaN based semiconductor layer to an ohmic electrode on a GaAs substrate. An n electrode is formed on the top surface of the GaN based semiconductor layer.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: August 3, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Nobuhiko Hayashi, Takashi Kano
  • Publication number: 20100187660
    Abstract: A 3-D stacked semiconductor device is formed by forming a trench is formed through a top surface in a dielectric layer to expose the crystalline silicon layer having a (100) crystal plane, such that the trench walls are parallel to a <100> direction. Epitaxial silicon is grown between the trench walls to a level that is below the top surface of the dielectric layer. Epitaxial silicon is laterally grown using the top portion of the epitaxially grown silicon as a seed to form a laterally grown epitaxial layer having a (100) crystal plane on the dielectric layer.
    Type: Application
    Filed: January 26, 2009
    Publication date: July 29, 2010
    Inventors: Sanh Tang, David Wells, Eric Blomiley
  • Patent number: 7763915
    Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: July 27, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Pierre Joly, Olivier Faynot, Laurent Clavelier
  • Patent number: 7759179
    Abstract: Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically, semiconductor fins are formed in a chevron layout oriented along the centerline of a wafer. Gates are formed adjacent to the semiconductor fins such that they are approximately perpendicular to the centerline. Then, masked implant sequences are performed, during which halo and/or source/drain dopants are implanted into the sidewalls of the semiconductor fins on one side of the chevron layout and then into the sidewalls of the semiconductor fins on the opposite side of the chevron layout. The implant direction used during these implant sequences is substantially orthogonal to the gates in order to avoid mask shadowing, which can obstruct dopant implantation when separation between the semiconductor fins in the chevron layout is scaled (i.e., when device density is increased).
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 7759772
    Abstract: A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Meikei Ieong, Devendra K. Sadana, Ghavam Shahidi
  • Patent number: 7759749
    Abstract: When metallic material is employed for various metallic films, it is possible to improve at least one of the mechanical strength, the durability against abrasion, and the uniformess as a film while keeping unchanged the chemical property and the electric property of the metallic material. Due to the gel three-dimensional mesh structure 406, the dislocations 407 of the tangle in the mesh form are introduced in the crystal of the metal 401 at high density; therefore, when the tensile stress 403 is applied thereto, these dislocations slightly shift. As a result, the metal 401 deforms by uniformly dispersing distortion in the order of crystal grains, and hence there does not occur concentration of stress, which leads to the breakage or the severance at the grain interface 402. Therefore, the metallic material of the present invention improves the mechanical strength and the durability against abrasion.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: July 20, 2010
    Assignee: NEC Corporation
    Inventor: Akio Tanikawa
  • Patent number: 7759684
    Abstract: A nitride semiconductor light emitting device includes a nitride semiconductor multilayer film. The nitride semiconductor multilayer film is formed on a substrate and made of nitride semiconductor crystals, and includes a light emitting layer. In the nitride semiconductor multilayer film, facets of a cavity are formed, and a protective film made of aluminum nitride crystals is formed on at least one of the facets. The protective film has a crystal plane whose crystal axes form an angle of 90 degrees with crystal axes of a crystal plane of the nitride semiconductor crystals constituting the facet of the cavity having the protective film formed thereon.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: July 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Atsunori Mochida, Yoshiaki Hasegawa
  • Patent number: 7755172
    Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: July 13, 2010
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Tadao Hashimoto, Hitoshi Sato, Shuji Nakamura
  • Patent number: 7755104
    Abstract: A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first <110> crystal orientation, and channels are located at sidewall of the semiconductor layer, a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a gate electrode that is formed on the semiconductor layer in a direction of a second <110> crystal orientation perpendicular to the curre
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: July 13, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsushi Yagishita
  • Patent number: 7755171
    Abstract: A transistor structure having a recessed source/drain and buried etch stop layer (e.g., a silicon germanium layer), and a related method, are disclosed. In one embodiment, the transistor structure includes a substrate including a substantially trapezoidal silicon pedestal over an etch stop layer; a gate atop the substantially trapezoidal silicon pedestal; a source/drain region extending into tapered surfaces of the substantially trapezoidal silicon pedestal and into the etch stop layer; and a stress liner overlying the gate and the source/drain region, the stress liner imparting a stress to the source/drain region and a channel of the gate. The recessed source/drain allows recessing without contacting the P-N junction, and allows improved application of stress to the channel.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: July 13, 2010
    Assignee: International Business Machines Corporation
    Inventor: Huilong Zhu
  • Patent number: 7750406
    Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ethan Harrison Cannon, Toshiharu Furukawa, John Gerard Gaudiello, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, III, Jack Allan Mandelman, William Robert Tonti
  • Publication number: 20100148320
    Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 ?m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm?2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. Both upper and lower surfaces may be offcut. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 17, 2010
    Applicant: CREE, INC.
    Inventors: Xueping Xu, Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes
  • Publication number: 20100148319
    Abstract: A three-dimensional thin-film semiconductor substrate having a plurality of ridges on the surface of the semiconductor substrate which define a base opening of an inverted pyramidal cavity and walls defining the inverted pyramidal cavity is provided. And a fabrication method for a 3-D TFSS by forming a porous silicon layer on a silicon template having a top surface aligned along a (100) crystallographic orientation plane of the silicon template and a plurality of walls each aligned along a (111) crystallographic orientation plane of the silicon template and forming an inverted pyramidal cavity. The porous silicon layer forms substantially conformal on the silicon template. Then forming a substantially conformal epitaxial silicon layer on the porous silicon layer and releasing the epitaxial silicon layer from the silicon template.
    Type: Application
    Filed: November 13, 2009
    Publication date: June 17, 2010
    Applicant: SOLEXEL, INC.
    Inventors: David Xuan-Qi Wang, Mehrdad M. Moslehi
  • Publication number: 20100148318
    Abstract: A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template.
    Type: Application
    Filed: November 13, 2009
    Publication date: June 17, 2010
    Applicant: SOLEXEL, INC.
    Inventors: David Xuan-Qi Wang, Mehrdad M. Moslehi
  • Patent number: 7737532
    Abstract: A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: June 15, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hu Ke, Chih-Hsin Ko, Hung-Wei Chen, Wen-Chin Lee, Min-Hwa Chi
  • Patent number: 7732865
    Abstract: The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Carl Radens, William R. Tonti, Richard Q. Williams
  • Patent number: 7723201
    Abstract: A method for manufacturing a device includes forming trenches of different morphologies into a substrate. At the upper surfaces, the trenches have different orientations with respect to each other. In an aspect, windows for the trenches are aligned along the <100> and <110> directions of a silicon substrate. The trenches of different morphologies may be formed into capacitors having different capacitance levels. Also included are devices prepared by the method.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Geng Wang
  • Patent number: 7723791
    Abstract: The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Bruce B. Doris, Huajie Chen, Patricia M. Mooney, Stephen W. Bedell
  • Patent number: 7719020
    Abstract: An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: May 18, 2010
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Akihiko Murai, Christina Ye Chen, Daniel B. Thompson, Lee S. McCarthy, Steven P. DenBaars, Shuji Nakamura, Umesh K. Mishra
  • Patent number: 7719089
    Abstract: A semiconductor device is provided that includes a semiconductor substrate, an n-channel MOSFET formed on the substrate and a p-channel MOSFET formed on the substrate. A first layer is formed to cover the n-channel MOSFET, wherein the first layer has a first flexure-induced stress. A second layer is formed to cover the p-channel MOSFET, wherein the second layer has a second flexure-induced stress.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: May 18, 2010
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Koichi Matsumoto
  • Publication number: 20100117203
    Abstract: A process for forming an oxide-containing film from silicon is provided that includes heating the silicon substrates to a process temperature of between 250° C. and 1100° C. with admission into the process chamber of diatomic reductant source gas Z-Z? where Z and Z? are each H, D and T and a stable source of oxide ion. Multiple exhaust ports exist along the vertical extent of the process chamber to create reactant across flow. A batch of silicon substrates is provided having multiple silicon base layers, each of the silicon base layers having exposed <110> and <100> planes and a film residual stress associated with the film being formed at a temperature of less than 600° C. and having a <110> film thickness that exceeds a <100> film thickness on the <100> crystallographic plane by less than 20%, or a film characterized by thickness anisotropy less than 18% and an electrical breakdown field of greater than 10.5 MV/cm.
    Type: Application
    Filed: January 30, 2007
    Publication date: May 13, 2010
    Applicant: Aviza Technology, Inc.
    Inventors: Robert Jeffrey Bailey, Hood Chatham, Derrick Foster, Olivier Laparra, Martin Mogaard, Cole Porter, Taiquing T. Qiu, Helmuth Treichel
  • Patent number: 7709933
    Abstract: A structural element having a region of porous silicon or porous silicon oxide, which was obtained from a porization, starting from an edge area of the region, in at least largely crystalline silicon. Relative to the edge area, the crystalline silicon has a crystal orientation that has an orientation that differs from a <100> orientation or from an orientation that is equivalent for reasons of symmetry. This structural element is suited for use in a mass-flow sensor, in a component for the thermal decoupling of sensor and/or actuator structures, or a gas sensor. Furthermore, methods for setting the thermal conductivity of a region of porous silicon or porous silicon oxide of a structural element are described.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 4, 2010
    Assignee: Robert Bosch GmbH
    Inventors: Hans Artmann, Thorsten Pannek, Hans-Peter Trah, Franz Laermer
  • Patent number: 7696537
    Abstract: A device, and method for manufacturing the same, including a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a boundary on the side facing toward the channel that is tapered. Such a configuration may allow the PFET channel to be compressively stressed by a large amount without necessarily substantially degrading extension junction characteristics. The tapered SiGe boundary may be configured as a plurality of discrete steps. For example, two, three, or more discrete steps may be formed.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: April 13, 2010
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Yusuke Kohyama
  • Patent number: 7691688
    Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: April 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Meikei Ieong, Alexander Reznicek, Devendra K. Sadana, Leathen Shi, Min Yang
  • Patent number: 7691752
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: April 6, 2010
    Assignee: Intel Corporation
    Inventors: Pushkar Ranade, Keith Zawadzki, Christopher Auth
  • Patent number: 7687829
    Abstract: A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Judson R. Holt, Meikei Ieong, Qiqing C. Ouyang, Siddhartha Panda
  • Publication number: 20100072580
    Abstract: A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms.
    Type: Application
    Filed: November 17, 2009
    Publication date: March 25, 2010
    Applicant: INTEL CORPORATION
    Inventors: Mohamad A. Shaheen, Willy Rachmady, Peter Toichinsky
  • Patent number: 7679165
    Abstract: A light emitting diode includes a substrate tilted toward first and second directions simultaneously, a first cladding layer formed with a semiconductor material of a first conductive type on the substrate, an active layer formed on the first cladding layer, and a second cladding layer formed with a semiconductor material of a second conductive type on the active layer, wherein concavo-convexes are formed on the interfaces of the first cladding layer, the second cladding layer, and the active layer, and the (100) substrate is a III-V or a IV-IV group semiconductor substrate, and has a crystal orientation such that a (100) plane of the (100) substrate is inclined 2 to 20° toward the [0-1-1] direction and 1 to 8° toward the [0-11] direction.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: March 16, 2010
    Assignee: NeosemiTech Corporation
    Inventors: Joon-Suk Song, Soo-Hyung Seo, Myung-Hwan Oh