Abstract: A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at least a surface of the passivation facing away from the wafer; and a mask layer disposed over at least a surface of the protection layer facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation, and wherein the mask layer includes a material that is selectively etchable to the material of the protection layer.

Abstract: A semiconductor device includes a main body having a single crystalline semiconductor body. A layered structure directly adjoins a central portion of a main surface of the main body and includes a hard dielectric layer provided from a first dielectric material with Young's modulus greater than 10 GPa. A stress relief layer directly adjoins the layered structure opposite to the main body and extends beyond an outer edge of the layered structure. Providing the layered structure at a distance to the edge of the main body and covering the outer surface of the layered structures with the stress relief layer enhances device reliability.

Abstract: It is an object of the present invention to provide a light-emitting element with high light emission efficiency and with a long lifetime. A light-emitting device comprises a first electrode, a second electrode, a light-emitting layer, a first layer, and a second layer, wherein the first layer is provided between the light-emitting layer and the first electrode, the second layer is provided between the light-emitting layer and the second electrode, the first layer is a layer for controlling the hole transport, the second layer is a layer for controlling the electron transport, and light emission from the light-emitting layer is obtained when voltage is applied to the first electrode and the second electrode so that potential of the first electrode is higher than potential of the second electrode.

Abstract: The light-emitting apparatus comprising thin film transistors and light emitting elements, comprises; a second inorganic insulation layer on a gate electrode, a first organic insulation layer on the second inorganic insulation layer, a third inorganic insulation layer on the first organic insulation layer, an anode on the third inorganic insulation layer, a second organic insulation layer overlapping with the end of the anode and having an inclination angle of 35 to 45 degrees, a fourth inorganic insulation layer on the upper and side surfaces of the second organic insulation layer and having an opening over the anode, an organic compound layer in contact with the anode and the fourth inorganic insulation layer and containing light-emitting material, and a cathode in contact with the organic compound layer, wherein the third and the fourth inorganic insulation layers comprise silicon nitride or aluminum nitride.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch.

Abstract: A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing.

Abstract: Provided is a method of manufacturing an organic electroluminescence display device including: an organic compound layer-forming step of forming an organic compound layer on a first electrode; a release layer-forming step of forming a release layer on the organic compound layer; a first processing step for the release layer of patterning the release layer; an organic compound layer-processing step of removing the organic compound layer in a region not covered with the release layer processed in the first processing step for the release layer; and a second processing step for the release layer of removing a part of the release layer, in which the release layer is a deposited film formed of a charge-transportable organic compound and is dissolved by a solvent containing an organic solvent miscible with water.

Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 ?m or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.

Abstract: An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

Abstract: A filler for filling a gap includes a compound represented by the following Chemical Formula 1. SiaNbOcHd.??[Chemical Formula 1] In Chemical Formula 1, a, b, c, and d represent relative amounts of Si, N, 0, and H, respectively, in the compound, 1.96<a<2.68, 1.78<b<3.21, 0?c<0.19, and 4<d<10.

Abstract: The light-emitting unit has at least a first light-emitting element, a second light-emitting element, and a separation layer. The separation layer has a leg portion and a stage portion which protrudes outside of a bottom surface of the leg portion over the leg portion. An upper electrode of the first light-emitting element is electrically connected to a lower electrode of the second light-emitting element in a region where the upper electrode and the lower electrode overlap with the stage portion of the separation layer. By providing the separation layer, the light-emitting unit can be formed without using a metal mask. The upper electrode can be a composite material including an organic compound and a metal oxide or a stacked layer of the composite material and a metal material or a light-transmitting conductive material.

Abstract: One or more techniques or systems for forming a pattern during semiconductor fabrication are provided herein. In some embodiments, a photo resist (PR) region is patterned and a spacer region is formed above or surrounding at least a portion of the patterned PR region. Additionally, at least some of the spacer region and the patterned PR region are removed to form one or more spacers. Additionally, a block co-polymer (BCP) is filled between the spacers. In some embodiments, the BCP comprises a first polymer and a second polymer. In some embodiments, the second polymer is removed, thus forming a pattern comprising the first polymer and the spacers. In this manner, a method for forming a pattern during semiconductor fabrication is provided, such that a width of the spacer or the first polymer is controlled.

Abstract: Apparatuses and methods are described that involve the deposition of polymer coatings on substrates. The polymer coatings generally comprise an electrically insulating layer and/or a hydrophobic layer. The hydrophobic layer can comprise fused polymer particles have an average primary particle diameter on the nanometer to micrometer scale. The polymer coatings are deposited on substrates using specifically adapted plasma enhanced chemical vapor deposition approaches. The substrates can include computing devices and fabrics.

Abstract: Methods of forming a semiconductor device are provided. The methods include, for example, forming a low-k dielectric having a continuous planar surface, and, after forming the low-k dielectric, subjecting the continuous planar surface of the low-k dielectric to an ethylene plasma enhanced chemical vapor deposition (PECVD) treatment.

Abstract: A method of modifying a fluorinated polymer surface comprising the steps of depositing a first layer on at least a portion of the fluorinated polymer surface, the first layer comprising a first polymer, the first polymer being a substantially perfluorinated aromatic polymer; and depositing a second layer on at least a portion of the first layer, the second layer comprising a second polymer, the second polymer being an aromatic polymer having a lower degree of fluorination than said first polymer, whereby the second layer provides a surface on to which a substance having a lower degree of fluorination than the first polymer, e.g. a non-fluorinated substance is depositable.

Abstract: A composite article with at least one high integrity protective coating, the high integrity protective coating having at least one planarizing layer and at least one organic-inorganic composition barrier coating layer. A method for depositing a high integrity protective coating.

Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

Abstract: The present invention relates to a biomolecule-based electronic device in which the biomolecule with redox potential is directly immobilized on the substrate. The present invention enables to excellently exhibit the capability of a protein-based bio-memory device in which it is preferable to use the substrate on which cysteine-introduced recombinant proteins are effectively immobilized and a self-assembled layer (SAM) is fabricated. It becomes realized that a redox potential is regulated using intrinsic redox potential of the protein dependent on applied voltage. The present invention provides a novel operating method in which three potentials are applied throughout four steps. The present invention has some advantages of fabricating a protein layer in a convenient manner and inducing electron transfer by fundamental electrochemical or electronic operation.

Abstract: A large size organic light emitting diode (OLED) display and manufacturing method thereof are disclosed. In one embodiment, the method includes i) forming a display unit including a plurality of pixels on a substrate, ii) forming a getter layer, a bonding layer and a conductive contact layer around the display unit and iii) manufacturing a sealing member including a flexible polymer film and a metal layer formed on at least one side of the polymer film. The method may further include laminating the sealing member on the substrate using a roll lamination process such that the metal layer contacts the conductive contact layer and curing the contact layer and the conductive contact layer.

Abstract: A device with an external surface, the device including: a substrate including first mono-crystal transistors; a second layer including second mono-crystal transistors, the second mono-crystal transistors overlaying the first mono-crystal transistors; and a plurality of thermal conduction paths from a plurality of the second layer locations to the external surface, wherein at least one of the thermal conduction paths includes an electrically nonconductive contact.

Abstract: A display device and method for fabricating includes patterning a field shield dielectric layer to expose conductors and form a cavity over the conductors. InkJet printing a semiconductor material fills a portion of the cavity in contact with the conductors. An insulation material is deposited on the semiconductor material. A pixel pad is formed over the insulation material and the field shield dielectric layer. A pixel is formed which includes a thin film transistor with an ink jet printed semiconductor layer.

Abstract: Provided is a high-luminance, long-life laminated organic electroluminescent element. The organic electroluminescent element has a composition in which a plurality of light-emitting units, including at least one organic light-emitting layer, are laminated between a positive electrode and a negative electrode, and in which a linking layer is held between the respective light-emitting units. The linking layer is formed by laminating, in succession from the positive electrode side, an electron generating/transport section, an intermediate layer, and a hole generating/transport section, which contain at least one metal selected from a group consisting of an alkali metal, alkaline earth metal, rare earth metal, alloy of these metals, and compound of these metals. Preferably the intermediate layer contains an electrical insulating non-semiconductive substance having a specific resistance which is between 1.0×102 ?·cm and 1.0×109 ?·cm.

Abstract: A semiconductor device includes a main body having a single crystalline semiconductor body. A layered structure directly adjoins a central portion of a main surface of the main body and includes a hard dielectric layer provided from a first dielectric material with Young's modulus greater than 10 GPa. A stress relief layer directly adjoins the layered structure opposite to the main body and extends beyond an outer edge of the layered structure. Providing the layered structure at a distance to the edge of the main body and covering the outer surface of the layered structures with the stress relief layer enhances device reliability.

Abstract: Organic electronic packages having sealed edges. More specifically, packages having organic electronic devices are provided. A number of sealing mechanisms are provided to hermetically seal the edges of the package to completely protect the organic electronic device from external elements. A sealant may be implemented to completely surround the organic electronic device. Alternatively, edge wraps may be provided to completely surround the organic electronic device.

Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

Abstract: A method of forming an emission layer by using droplets and an emission part on which charges with opposite polarities are induced, a method of manufacturing an organic light emitting display device including the emission layer, and the organic light emitting display device thereof, the method includes inducing charges having a first charge polarity on emission portions by facing a surface of a mask and a surface of a substrate, contacting the charge inducing units of the mask to the emission portions of the substrate, and then separating the mask from the substrate, supplying droplets exhibiting a second and opposite charge polarity to the substrate and forming the emission layer by allowing droplets exhibiting the second charge polarity to be attracted to and move to the emission portions exhibiting the first charge polarity.

Abstract: A coating film (90) is formed by causing vapor deposition particles (91) discharged from a vapor deposition source opening (61) of a vapor deposition source (60) to pass through a space between a plurality of control plates (81) of a control plate unit (80) and a mask opening (71) of a vapor deposition mask in this order and adhere to a substrate, while the substrate (10) is moved relative to the vapor deposition mask (70) in a state in which the substrate (10) and the vapor deposition mask (70) are spaced apart at a fixed interval. A difference in the amount of thermal expansion between the vapor deposition source and the control plate unit is detected and corrected. It is thereby possible to form, at a desired position on a large-sized substrate, the coating film in which edge blur and variations in the edge blur are suppressed.

Abstract: Embodiments of the invention include articles comprising a diamond like carbon coating or doped diamond like carbon coating on one or more surfaces of a plastic substrate or a plastic enclosure. Embodiments of the DLC or doped DLC coatings reduce the gas permeation of the coated plastic or thermoplastic to hydrogen or helium compared to the permeability of the plastic alone. The DLC or doped DLC coatings coating provides a surface resistivity of from about 107 to about 1014 ohm/square and have a transmittance that range from about 0% to about 70% less than the transmittance of the underlying plastic substrate in the range of about 300 nm to about 1100 nm. The DLC coated plastic can be used in environmental enclosures for protecting environmentally sensitive substrates such as semiconductor wafers and reticles.

Abstract: A moisture barrier coating for protecting a substrate from moisture, comprises an inorganic layer disposed over the substrate, the inorganic layer comprising an oxide or nitride of an element selected from the group consisting of silicon, aluminum, titanium, zirconium, hafnium and combinations thereof; and an organic silicon-containing layer disposed over the inorganic layer.

Abstract: An article having a surface treated to provide a protective coating structure in accordance with the following method: vapor depositing a first layer on a substrate, wherein said first layer is a metal oxide adhesion layer selected from the group consisting of an oxide of a Group IIIA metal element, a Group IVB metal element, a Group VB metal element, and combinations thereof; vapor depositing a second layer upon said first layer, wherein said second layer includes a silicon-containing layer selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride; and vapor depositing a third layer upon said second layer, wherein said third layer is a functional organic-comprising layer, wherein said functional organic-comprising layer is a SAM.

Abstract: A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO2 skeleton; a second porous layer that is formed immediately above the first porous layer and includes a SiO2 skeleton; a via wiring that is provided in the first porous layer; and a trench wiring that is buried in the second porous layer. The first porous layer has a pore density x1 of 40% or below and the second porous layer has a pore density x2 of (x1+5) % or above.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a solution processed device are described.

Abstract: An organic light emitting diode (OLED) display that includes a substrate, a thin film transistor, and a pixel electrode. The thin film transistor is formed on the substrate and includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The pixel electrode is electrically connected to the thin film transistor and is formed on the same layer as the source electrode and the drain electrode. The source electrode and the drain electrode include a first conductive layer, and the pixel electrode includes a first conductive layer and a second conductive layer stacked thereon.

Abstract: A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The stabilizing solution comprises a non-volatile component, such as non-volatile particles or polymers, which is applied after the photoresist material has been developed. By treating the photoresist with the solution containing a non-volatile component after developing but before drying, the non-volatile component fills the space between adjacent resist patterns and remains on the substrate during drying. The non-volatile component provides structural and mechanical support for the resist to prevent deformation or collapse by liquid surface tension forces.

Abstract: Disclosed herein are stretchable, foldable and optionally printable, processes for making devices and devices such as semiconductors, electronic circuits and components thereof that are capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Strain isolation layers provide good strain isolation to functional device layers. Multilayer devices are constructed to position a neutral mechanical surface coincident or proximate to a functional layer having a material that is susceptible to strain-induced failure. Neutral mechanical surfaces are positioned by one or more layers having a property that is spatially inhomogeneous, such as by patterning any of the layers of the multilayer device.

Abstract: Disclosed is a method of manufacturing an organic light-emitting display device. An organic light-emitting display device may include, for example, a thin-film transistor (TFT) including a gate electrode, an active layer insulated from the gate electrode, source and drain electrodes insulated from the gate electrode and contacting the active layer and an insulating layer disposed between the source and drain electrodes and the active layer; and an organic light-emitting diode electrically connected to the TFT. The insulating layer may include, for example, a first insulating layer contacting the active layer; and a second insulating layer formed of a metal oxide and disposed on the first insulating layer.

Abstract: The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride.

Abstract: An organic light emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes a substrate, an active layer and a capacitor lower electrode positioned on the substrate, a gate insulating layer positioned on the active layer and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer at a location corresponding to the active layer, a capacitor upper electrode positioned on the gate insulating layer at a location corresponding to the capacitor lower electrode, a first electrode positioned to be separated from the gate electrode and the capacitor upper electrode, an interlayer insulating layer positioned on the gate electrode, the capacitor upper electrode, and the first electrode, a source electrode and a drain electrode positioned on the interlayer insulating layer, and a bank layer positioned on the source and drain electrodes.

Abstract: An organic light emitting display device constructed with an active layer of a thin film transistor formed on a substrate; a gate electrode including a first transparent conductive layer and a first metal layer formed on the active layer and a first insulating layer, source and drain electrodes including a second metal layer connected to the active layer through a contact hole formed in the second insulating layer, a third metal layer formed on the second metal layer, and a second transparent conductive layer formed on the third metal layer, formed on the gate electrode and a second insulating layer, a pixel electrode including the first transparent conductive layer, the third metal layer, and the second transparent conductive layer formed on the first insulating layer; and an intermediate layer disposed on the pixel electrode.

Abstract: An organic EL device 1, for example, excellent in productivity and performance with reduced influence of a voltage drop can be provided at low fabrication cost. The organic EL device 1 includes band-shaped organic EL strips 3 arranged at spacings on a first substrate 2. Each of the organic EL strips 3 includes a second substrate 31, a negative electrode 32b, a positive electrode 32a, and an organic layer 33. The pair of the electrodes 32a and 32b and the organic layer 33 are stacked on the second substrate 2 with the organic layer 33 sandwiched between the electrodes 32a and 32b. The first substrate 2 includes a connection terminal electrode 5 and an auxiliary terminal electrode 6. For example, negative electrode 32b is electrically connected to the connection terminal electrode 5, and the positive electrode 32a is electrically connected to the auxiliary terminal electrode 6.

Abstract: In accordance with at least some embodiments of the present disclosure, a process for fabricating a light pipe (LP) is described. The process may be configured to construct a semiconductor structure having an etch-stop layer above a photodiode region and a first dielectric layer above the etch-stop layer. The process may be configured to etch a LP funnel through the first dielectric layer. And the process may be further configured to stop the etching of the LP funnel upon reaching and removing of the etch-stop layer.

Abstract: Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.

Abstract: The invention relates to an electronic device, particularly photoreceptor or electrophotographic device, comprising an organic function material, which comprises an electron transport component and a hole trap component, to an organic material, which is a mixture or a copolymer comprising an electron transport component and a hole trap component, its use as charge transport material in a photoreceptor or electrophotographic device, especially of the positive charging type, and to electronic devices comprising such a material.

Abstract: To provide a semiconductor device member that is superior in heat resistance, light resistance, film-formation capability and adhesion, and is capable of sealing a semiconductor device and holding a phosphor without causing cracks, peelings and colorings even after used for a long period of time, the weight loss at the time of heating, measured by a predetermined weight-loss at-the-time-of-heating measurement method, is 50 weight % or lower and the ratio of peeling, measured by a predetermined adhesion evaluation method, is 30% or lower, in the semiconductor device member.

Abstract: A semiconductor device has an insulating film, serving as low-porosity regions low in porosity, formed on a substrate and high-porosity regions higher in porosity than the low-porosity regions, and also includes copper interconnects formed to fill interconnect grooves in the insulating film. The insulating film is present under the interconnect grooves, and present in portions neighboring the sidewalls of the interconnect grooves.

Abstract: A method of forming an organic thin film transistor comprising source and drain electrodes with a channel region therebetween, a gate electrode, a dielectric layer disposed between the source and drain electrodes and the gate electrode, and an organic semiconductor disposed in at least the channel region between the source and drain electrodes, said method comprising: seeding a surface in the channel region with crystallization sites prior to deposition of the organic semiconductor; and depositing the organic semiconductor onto the seeded surface whereby the organic semiconductor crystallizes at the crystallization sites forming crystalline domains in the channel region.

Abstract: An organic light emitting device and a method for fabricating the same are discussed. According to an embodiment, the method includes forming a mother substrate structure including organic light emitting devices including TFTs and first electrodes, each first electrode electrically connected to the corresponding TFT and being a part of an OLED to be formed; forming first and second conductive layers to form a power line in each organic light emitting device; forming a dummy layer on the first electrodes and the second conductive layer; performing at least one of scribing and grinding processes on the mother substrate structure to divide the mother substrate structure into sub-substrate structures; removing the dummy layer from the first electrodes and the second conductive layer after the performing step; and forming a light emitting layer and a second electrode on the first electrode in one of the sub-substrate structures to form the OLED.

Abstract: The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride.

Abstract: An organic semiconductor transistor has plural electrodes and an organic semiconductor layer including at least one compound represented by the following Formula (I). In Formula (I), each R is independently a hydrogen atom or an alkyl group; and n and m are each independently an integer of from 1 to 3.

Abstract: A semiconductor composite film includes a semiconductor thin film layer containing an organic semiconductor material, an insulating thin film layer formed from a polymer material phase-separated from the organic semiconductor material in the film thickness direction, and a fine particle material dispersed in at least one of the semiconductor thin film layer and the insulating thin film layer.