Abstract: A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present.

Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility.

Abstract: A semiconductor package with a die pad having a recessed portion is proposed, wherein a lead frame is used, having a die pad formed with at least a through hole, and a plurality of leads. A chip is mounted on the die pad and covers the through hole, with a bottom surface of the chip being partly exposed out the through hole. The through hole is formed at its peripheral edge with a recessed portion that dents from a top surface of the die pad and is associated with the through hole. During a molding process, the recessed portion is entirely filled with an encapsulating compound used for encapsulating the chip and die pad. This prevents forming of voids between the chip and die pad, and assures packaged products to be free of die crack or popcorn effect, thereby significantly improving yield and reliability of the packaged products.

Abstract: A wiring circuit block is produced by forming a release layer on one of planarized principal surfaces of a mother substrate, forming an insulating layer on the release layer, patterning the insulating layer and forming a wiring layer on the patterned insulating layer, and separating the insulating layer and wiring layer from the release layer on the mother substrate. The circuit block has components, and deposited on the wiring layer, and is mounted on a base circuit board to provide a wiring device. Also, semiconductor chips are mounted on the circuit block, and the circuit block is mounted on a base circuit board to provide a semiconductor device.

Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.

Abstract: An insulating sheet which connects a semiconductor chip and a wiring substrate is provided between the semiconductor chip and the wiring substrate. The insulating sheet has windows therethrough at positions corresponding to those of connection pads of the wiring substrate and has leads, one end of each of the leads being fixed on the sheet and the other end of each of the leads protruding from the opposite surface of the sheet through a window. Each of solder balls of the semiconductor chip is connected to the fixed one end of one of the leads, and each of the connection pads is connected to the other end of each of the leads to electrically connect the semiconductor chip and the wiring substrate.

Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.

Abstract: A semiconductor package includes a chip mounting pad having a peripheral edge. The package further includes a semiconductor chip attached to the chip mounting pad. The package further includes a plurality of leads. Each lead includes an inner end and an opposing distal end. Each inner end is disposed adjacent the peripheral edge in spaced relation thereto and vertically downset with respect to each respective distal end. The package further includes at least one isolated ring structure disposed along the peripheral edge between the peripheral edge and the inner ends of the leads in spaced relation thereto. The ring structure is electrically connected to the semiconductor chip and an inner end of at least one of the leads.

Abstract: A stress-balancing layer formed over portions of a spring metal finger that remain attached to an underlying substrate to counter internal stresses inherently formed in the spring metal finger. The (e.g., positive) internal stress of the spring metal causes the claw (tip) of the spring metal finger to bend away from the substrate when an underlying release material is removed. The stress-balancing pad is formed on an anchor portion of the spring metal finger, and includes an opposite (e.g., negative) internal stress that counters the positive stress of the spring metal finger. A stress-balancing layer is either initially formed over the entire spring metal finger and then partially removed (etched) from the claw portion, or selectively deposited only on the anchor portion of the spring metal finger. An interposing etch stop layer is used when the same material composition is used to form both the spring metal and stress-balancing layers.

Abstract: An LOC type semiconductor package has a lead frame with leads divided into general leads and stable leads. The ends of the general leads are at the periphery of the semiconductor chip and separated from the semiconductor chip, such that the general leads do not come into contact with the semiconductor chip. The ends of the stable leads attach to a central portion of the surface of the semiconductor chip. Accordingly, since all the inner leads are not collectively arranged on the surface of the semiconductor chip but only the stable inner leads are located thereon, semiconductor chips in a variety of sizes can be mounted on the lead frame. Thus, there is no need for a new lead frame design whenever the semiconductor chip size is changed and a single lead frame design can be mass produced for use in several different products.

Abstract: A stress shield made of a material having a CTE similar to that of the material used in the fabrication of a microelectronic die, including but not limited silicon, molybdenum, and aluminum nitride, which abuts at least one corner and/or edge of the microelectronic die. When the stress shield is positioned to abut the microelectronic die corners and/or edges, the mechanical stresses on the microelectronic die are greatly reduced or substantially eliminated.

Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

Abstract: A portable data carrier includes a card-shaped body having a recess for receiving a chip module. The chip module includes at least one semiconductor chip on a first main side of a chip carrier connected to the card-shaped body, and a metallization layer disposed on a second main side of the chip carrier and having contact lugs. The chip carrier has desired bending points which, upon the occurrence of bending stresses, reduce forces on the semiconductor chip and wire connections.

Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.

Abstract: An object of the present invention is to provide an adhesive with which voids are less likely to occur and adherends are not curved. Adhesives of the present invention have excellent dispensability from nozzles of dispensers because the overall specific gravity of the adhesives is adjusted to 1.4 or more and 4.0 or less by adding a filler having a specific gravity of 3.0 or more and 9.0 or less. A highly reliable electric device 1 can be obtained because no voids are generated in an adhesive 12 or an adherend or a flexible wiring board 5 is not curved when the flexible wiring board and a semiconductor chip 11 are connected.

Abstract: A two-lead, surface-mounting, high-power micro-leadframe semiconductor package has the same outline, mounting, and electrical functionality as industry standard leadframe packages but provides a lower internal resistance, a higher package power rating, and costs less to produce. The novel package incorporates one of a rectangular array of “micro-leadframes” (“MLFs”), each having parallel and respectively coplanar upper and lower surfaces etched in a plate having a uniform thickness. Each micro-leadframe includes an I-shaped die pad having a head, a foot, and opposite sides. First and second leads are disposed at the foot of the die pad, each having a side aligned with one of the sides of the pad. The second lead has an right-angled wire-bonding pad next to the die pad. A portion of a lower surface of each of the die pad and the leads is exposed through a lower surface of an envelope of plastic molded on the package to define package input/output terminals.

Abstract: A chip carrier with a dam bar structure is proposed. The chip carrier is defined with at least a chip attach area and a wire bonding area surrounding the chip attach area, allowing a chip to be mounted on the chip attach area and electrically connected to the wire bonding area by bonding wires bonded to the wire bonding area. A molding gate and a dam bar are formed on the substrate outside the chip attach area and wire bonding area. An molding compound is injected through the molding gate for encapsulating the chip and bonding wires. The dam bar is provided with a first gate directed toward the molding gate, a second gate and a third gate opposed to the second gate, wherein the second and third gates are each vertically arranged with respect to the molding gate, allowing the molding compound to divert its flow direction by the dam bar.

Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

Abstract: A semiconductor element, such as a pressure sensor, having an upper surface, so that a part of the upper surface is exposed to the outside, while this element is in use. The element is sealed with a sealing resin. The sealing resin has a second, upper surface and a recess, so that said part of the first, upper surface of the semiconductor element is exposed outside at the bottom of said recess which is opened at the second, upper second surface. A releasable protective member has a shape corresponding to the recess and is placed in the recess, so that, when said protective member is in the recess, a bottom surface thereof is in contact with the part of the first, upper face of the protective member and the upper face of the resin coincides with the second surface of the sealing resin.

Abstract: A die pad (81) of a leadframe (8) has a plurality of slots (811-814) that extend through the die pad to define a restrictive region (815). One of the slots extends around a comer of the restrictive region outside where a die (7) is connected to the die pad by solder paste (6). Because of the cohesion of the solder paste, the solder paste does not flow into the slots. The solder paste is thereby restricted to the restrictive region. This prevents the die from drifting or rotating so as to increase the packaging quality.

Abstract: A frame for a semiconductor package includes plural lead frames arranged through grid-leads in a matrix. Semiconductor devices are mounted on individual lead frames of the frame, and are molded with molding compound. Thereafter, the molded semiconductor devices are cut at grid-leads by means of a dicing saw so that individual semiconductor packages are obtained. The frame further has groove portions which are formed by etching the frame from the front or back at areas corresponding to grid-leads, so that the grid-leads are made thin which reduces burrs and the generation of metal powders and dust.

Abstract: A thin GaAs Substrate can be provided with a copper back-metal layer to allow the GaAs Substrate to be packaged using conventional plastic packaging technologies. By providing the GaAs Substrate with a copper back-metal layer, the GaAs Substrate can be made thinner than 2 mils (about 50 microns), thereby reducing heat dissipation problems and allowing the semiconductor die to be compatible with soft-solder technologies. By enabling the semiconductor die to be packaged in a plastic package substantial cost savings can be achieved.

Abstract: A lead frame including a first set of leads in a first plane and a second set of leads in a second plane offset vertically from the second plane. The leads in the first and second planes are offset from each other by a lead width.

Abstract: In a semiconductor device, a lead frame is adhered to a base substrate for heat dissipation via an insulating layer, and an outward guided terminal portion is formed by perpendicularly upwardly bending an end of the lead frame after the mounting of one or more of power semiconductor elements on the lead frame. A recessed portion is formed beforehand in a portion of the lead frame to be bent, and it is ensured that the lead frame does not adhere to the surface of the base substrate in this recessed portion when the lead frame is adhered to the base substrate via the insulating layer before the bending of the lead frame. By virtue of this structure, manufacturing is simplified and manufacturing costs are reduced.

Abstract: In a semiconductor device, and a fabrication method thereof, a semiconductor element having bumps is mounted to a rear side of a base film. A plurality of inner leads are formed at a front side of the base film and located at peripheral portions of the semiconductor element. The inner leads are electrically connected with the bumps of the semiconductor element from the rear side of the base film. Apertures for connection of the bumps of the semiconductor element with the inner leads are provided at the base film. The apertures for connection are provided at locations which exclude locations of distal end portions of the inner leads. The distal end portions of the inner leads are fixed to the base film. The bumps of the semiconductor element and the base film are electrically connected through the apertures for connection from the rear surface.

Abstract: An improved tape carrier package (TCP) structure is proposed, which is characterized in the provision of dummy pads and dummy leads to help reinforce the package construction. The dummy pads are provided on the corners of the semiconductor chip, while the dummy leads are bonded between the dummy pads and corner-situated lead-bonding areas on the tape carrier. During assembly, since dummy leads are bonded between the dummy pads and corner-situated lead-bonding areas, the corners of the semiconductor chip can be firmly supported as well as the four sides of the semiconductor chip which are supported by the I/O leads. As a result the package construction is reinforced. During inner-lead bonding (ILB) process, such reinforcement can help prevent the cracking of the I/O leads.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.

Abstract: A semiconductor device package and method of fabricating same. The package includes a lead frame having a die paddle and a plurality of lead fingers. The active surface of a first semiconductor die is adhered to the underside of the die paddle and is electrically coupled with one or more of the plurality of lead fingers. A second semiconductor die may be adhered to the upper side of the die paddle along a surface which is opposite to its active surface and is electrically coupled with one or more of the plurality of lead fingers. The die paddle may be formed to exhibit a smaller peripheral outline than that of the first semiconductor die such that the die paddle does not interfere with any peripherally located bond pads of the first semiconductor die. The die paddle may further serve as a heat spreader, resulting in a more thermally stable package.

Abstract: By providing an end portion of a radiation plate located on and near an end portion of an insulator sheet, to which a lead frame extends, at a position away from the end portion of the insulator sheet inside of the insulator sheet in a plane direction of the insulator sheet, it is possible to secure a creeping distance between the lead frame and the radiation plate without decreasing a lead frame area on which components can be actually mounted.

Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

Abstract: A package structure having tapering support bars and leads. The package structure has at least a lead frame, a die, a plurality of conductive wires and an encapsulating plastic body. The lead frame has a first surface and has at least a package unit. The package unit has a die pad, a plurality of leads and a plurality of support bars. The die pad is positioned in the middle. The leads and support bars are distributed around the periphery of the package unit. In addition, the width of the leads and support bars decreases gradually from a location close to the die pad towards the peripheral region. The leads and support bars have a rectangular or trapezoidal cross-section. A die is bonded on the surface of the die pad and the die is electrically connected to the leads on the lead frame via a plurality of conductive wires. Plastic material such as epoxy resin encloses the die, the conductive wires and the first surface of the lead frame.

Abstract: In accordance with a press contact type semiconductor device, a metallic body having macroscopic vacancies inside is arranged between a main electrode of the semiconductor device and a main electrode plate, or between an intermediate electrode plate arranged on a respective main plane of the semiconductor element and a main electrode plate.

Abstract: A semiconductor device includes a semiconductor chip with a functional surface, a substrate opposing the functional surface of the semiconductor chip at a space formed between the substrate and the functional surface, a power supplying device electrically connected to a part of the functional surface of the semiconductor chip and separated by a slight gap from the substrate, a fixing member that fixes the semiconductor chip to the substrate, and a sealing member that seals the space formed between the substrate and the functional surface of the semiconductor chip other than a space formed between the substrate and the functional surface of the semiconductor chip that are fixed to each other through the fixing member and other than the gap formed between the power supplying device and the substrate. The sealing member has greater elasticity than the fixing member.

Abstract: A dual-die integrated circuit package is provided, which can be used to pack two semiconductor dies in the same package unit. These two semiconductor dies are of the type having an array of bonding pads formed thereon. The dual-die integrated circuit package has a first leadframe and a second leadframe, each having a die pad and a plurality of leads, with the die pad being arranged at a different elevation with respect to the leads. The two semiconductor dies are mounted on the respective die pads of the two leadframes, with the bottom surface of each semiconductor die facing the bottom surface of the other, allowing the bottom surface of one semiconductor die to be separated from the die pad of the first leadframe and the bottom surface of the other semiconductor die to be separated from the die pad of the second leadframe.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first conductive bump on a substrate, forming a second conductive bump on a semiconductor chip, forming a plurality of spaced apart dielectric supporting pads on one of the substrate and the semiconductor chip, mounting the semiconductor chip on the substrate to confine therebetween a gap, bonding together the first and second conductive bumps, and forming an insulating layer that fills in the gap and that encapsulates the supporting pads and the first and second conductive bumps.

Abstract: A leadless leadframe panel comprising a partially etched top surface of a substrate panel that forms recessed regions that define a portion of a first and a second set of tie bars and a portion of a first and second set of contact pads. A bottom surface of the panel forms lower recessed regions that define the remaining portion of the first and second set of tie bars and the remaining portion of the first and second set of contact pads. The resulting contact pads are connected to a respective one of the tie bars.

Abstract: A lead frame includes a pair of guide rails separated at a predetermined space; at least one dam bar for connecting the pair of guide rails; a die paddle for mounting a semiconductor chip between the dam bar; a tie bar for supporting the die paddle; a plurality of leads each consisting of a first lead having a predetermined length extended from the dam bar between the dam bar and the die paddle, a second lead connected electrically to the first lead and formed bent in a first direction, and a third lead connected electrically to the second lead and formed bent in a second direction.

Abstract: A semiconductor package includes a metallic foil (10) having a front surface and a rear surface, which foil (10) is formed to have a recess portion (12) including a bottom and an extended border region (14) around the recess portion (12). A substrate (30) is attached to the front surface of the foil (10) over the border region (14) to provide a support for electrical connection of a semiconductor element (40). The substrate (30) has an opening exposing the recess portion (12). A stiffener (20) is formed on the rear surface of the foil (10) for enhancing the rigidity of the foil (10). The stiffener (20) extends over the border region (14) and around the recess portion (12), with the rear surface of the bottom of the recess portion (12) exposed for heat dissipation. A semiconductor element (40) is mounted on the bottom of and within the recess portion (12).

Abstract: A structure includes holes formed in a layer of tape. The holes are aligned over active areas on chips formed in a wafer. A custom vacuum chuck with a plurality of suction ports is aligned on the tape such that the suction ports contact only the tape and not the hole portions. Flats of the custom vacuum chuck are formed so that a perimeter of the flats contacts, and rests on, the tape. In addition, the flats of the custom vacuum chuck are formed so that the flats cover the entire active area on the first surface of each of the chips. Consequently, the combination of the custom vacuum chuck and the single layer of tape form a protective cavity over the active areas of the chips during singulation from the wafer.

Abstract: Disclosed is a semiconductor package which has no resinous flash formed on a lead frame and its manufacturing method.

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: The resin-sealed semiconductor device includes a die pad portion, a semiconductor element mounted on the die pad portion and having electrodes, a plurality of lead portions arranged with their respective tips facing the die pad portion, thin metal wires for connecting the electrodes of the semiconductor element to the lead portions, and a sealing resin for sealing the die pad portion, the semiconductor element, the lead portions and connection regions of the thin metal wires except a bottom surface of the die pad portion and respective bottom surfaces and terminal ends of the lead portions. The terminal ends of the lead portions are approximately flush with a side surface of the sealing resin. The die pad portion has a first recess formed in an outer periphery of the bottom surface thereof.

Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.

Abstract: A semiconductor package having a lead frame formed with a die pad and a plurality of conductive leads, wherein the die pad is formed with a plurality of tabs to impede the resin flow below the die pad such that a downward pressure is produced because the resin flow above the die pad moves at a speed faster than that below the die pad. As a result, the tab is urged against a bottom surface of a mold cavity during a transfer molding process so as to prevent the die pad from being exposed to an encapsulant for encapsulating the die pad and a semiconductor die mounted on the die pad.

Abstract: A wire bond comprising an intentionally introduced ends offset wherein the ends offset reduces stress from axial displacement as compared to the same axial displacement on a wire bond without an intentionally introduced ends offset. Further disclosed are a semiconductor device comprising at least one wire bond having an intentionally introduced stress reducing ends offset, and methods for fabricating a wire bond and semiconductor device.

Abstract: An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.

Abstract: The semiconductor elements for the small signal type circuits and the Au wire for connection are integrated as one package to produce the semiconductor devices 30A, 31A, 32, 33A, 34A and 38. In this way, the wire bonding of Au can be omitted, and the wire bonding of the small diameter Al wire and the large diameter Al wire is only required to complete the connection of the fine metal wire. These semiconductor devices have a plurality of circuit elements as one package, so that the mounting operation on the mounting board can be significantly reduced.

Abstract: A novel five-layer tape is provided for applications such as bonding, interconnection and insulation of different parts of a semiconductor package at the same time. The five layer tape includes a metal conductive layer that is sandwiched between two insulative layers, that are themselves in turn sandwiched by two adhesive layers. Windows cut into the insulative and adhesive layers on either the top or bottom of the tape permit electrical connection to the metallic conductive layer. The tape may be made from two insulation sheets that have an adhesive layer and a metallic interconnect. In turn, the tape enables the manufacturer to overcome physical limitations in forming conduction paths, including permitting the connection of multiple die where the terminals of the one die are obscured by the other die.

Abstract: A metallic or an electrical trace having a terminus and a stress relief bend formed in the trace adjacent the terminus. The electrical trace may have a portion carried by a flexible substrate to form a flexible circuit. The stress relief bend may be free floating and extend from the flexible substrate or may be encapsulated by the flexible substrate. The electrical circuit and the flexible circuit each have a generally planar portion extending in the X and Y axis, with the stress relief bend projecting into the Z axis. This allows electrical traces to be spaced with a very narrow pitch because the stress relief bend does not consume any valuable real estate on the flexible circuit or the substrate to which the electrical trace is applied.