Abstract: A semiconductor device includes at least two or more groups of external connection terminals to which a substrate that drives a bare chip by inputting a signal from an external apparatus to the bare chip is electrically connected, the at least two or more groups of external connection terminals being formed outside an image area of the bare chip, wherein at least one group of terminals constitutes a first group of terminals, another group of terminals constitutes a second group of terminals, the first group of terminals doubles as the second group of terminals, and a substrate for inspection doubling as a substrate for mounting is electrically connected to the first group of terminals.

Abstract: An integrated circuit package system includes: connecting a carrier and an integrated circuit mounted thereover; preforming a wire-in-film encapsulation having a cavity; pressing the wire-in-film encapsulation over the carrier and the integrated circuit with the cavity exposing a portion of the integrated circuit; and curing the wire-in-film encapsulation.

Abstract: Electronic device which comprises a substrate provided with at least one passing opening, a MEMS device with function of differential sensor provided with a first and a second surface and of the type comprising at least one portion sensitive to chemical and/or physical variations of fluids present in correspondence with a first and a second opposed active surface thereof, the first surface of the MEMS device leaving the first active surface exposed and the second surface being provided with a further opening which exposes said second opposed active surface, the electronic device being characterized in that the first surface of the MEMS device faces the substrate and is spaced therefrom by a predetermined distance, the sensitive portion being aligned to the passing opening of the substrate, and in that it also comprises a protective package, which incorporates at least partially the MEMS device and the substrate so as to leave the first and second opposed active surfaces exposed respectively through the passin

Abstract: A packaging substrate with an embedded photosensitive semiconductor chip and a method for fabricating the same are provided. The method includes the steps of: disposing the semiconductor chip in an through cavity of a core board with the photosensitive portion of the semiconductor chip being exposed from the through cavity; forming a first circuit layer on the core board at a side opposite to the photosensitive portion so as to electrically connect the electrode pads of the semiconductor chip; and forming a light-permeable layer on the core board at the same side with the photosensitive portion via an adhesion layer so as to allow light to penetrate through the light-permeable layer and reach the photosensitive portion of the semiconductor chip. When fabricated by the method, the packaging substrate dispenses with conductive wires and a surrounding dam and thus is efficiently downsized.

Abstract: A solid-state image capturing apparatus includes: an insulation substrate including an external lead terminal; a solid-state image capturing element fixed on the insulation substrate and including a microlens; and a transparent glass member positioned above the insulation substrate for sealing the solid-state image capturing element fixed on the insulation substrate, and an electrode of the solid-state image capturing element and the external lead terminal of the insulation substrate being connected by a wire, wherein the transparent glass member is positioned in such a manner that a hollow space is formed between a microlens of the solid-state image capturing element and the transparent glass member, and wherein portions of the insulation film, the solid-state image capturing element and the wire, which are exposed in the hollow space, are all covered with a protective film.

Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.

Abstract: A semiconductor device includes an interlayer film formed over a semiconductor substrate. A groove is formed in the interlayer film. A wiring formed in the groove is a copper alloy including copper and a metal element. An oxide layer of the metal element is formed over the surface of the wiring. The oxide layer is formed in a first region along a grain boundary of a copper crystal and a second region surrounded by the grain boundary, over the surface of the wiring. The oxide layer formed in the first region has a thickness greater than that of the oxide layer formed in the second region.

Abstract: An integrated circuit package system includes providing a leadframe that is coplanar with a bottom surface of the integrated circuit package system to which is attached a device with a thermally conductive coating that is coplanar with the bottom surface of the integrated circuit package system to the leadframe, the device having the characteristics of being singulated from a wafer and the thermally conductive coating having the characteristics of being singulated from a wafer level thermally conductive coating and encapsulating the device with an encapsulation material that leaves the thermally conductive coating exposed for thermal dissipation.

Abstract: Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.

Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

Abstract: A device includes: a package having a bottom and a side wall surrounding the bottom; an element adhered to the bottom of the package; an internal contact formed inside the package; a resin encapsulation material with which a space between the package and the element is filled; and a coating formed to cover an end surface of the internal contact near the element, and made of a material whose thermal expansion coefficient is greater than or equal to the thermal expansion coefficient of the package and less than the thermal expansion coefficient of the resin encapsulation material.

Abstract: An optical cell for spectral analysis is disclosed generally comprising a monolithic cell body that transmits light, the cell body having an outer surface and a fluid channel for receiving a sample that defines an inner surface. The inner surface of said cell body includes a planar section, and the outer surface of said cell body likewise includes a planar section, which is adjacent and substantially parallel to the planar section of the inner surface. In certain embodiments, the ends of the channel are frustoconical, and ferrules are employed to secure sample inlet/outlet tubes to the cell.

Abstract: A method for forming an electrical package to reduce warpage. The method includes providing a wafer and coupling a die thereto. A mold compound material is applied to the wafer such that the mold compound material surrounds the die. The method further includes applying a reinforcing material to the mold compound material. The mold compound material is thereby disposed between the wafer and the reinforcing material.

Abstract: A package structure includes first and second substrates, a sealant and a filler. The first substrate has a surface including an active region and a bonding region. The first substrate has a component in the active region and a pad in bonding region. The pad is electrically connected to the component. The sealant is disposed on the surface surrounding the active region. The sealant has a breach at a side of the active region. The second substrate is bonded to the first substrate via the sealant. The second substrate has a first opening corresponding to the pad, and a second opening corresponding to the breach. The filler fills the second opening, covers the breach such that the first substrate, the second substrate, the sealant and the filler together form a sealed space for accommodating the component.

Abstract: A light emitting device can have a layered structure and include a plurality of semiconductor nanocrystals. The layers of the device can be covalently bonded to each other. The device can include continuous chain of covalent bonds extending from the first electrode to the second electrode.

Abstract: An integrated circuit package system includes: connecting a carrier and an integrated circuit mounted thereover; mounting an interposer, having an opening, over the integrated circuit; connecting an interconnect between the interposer and the carrier through the opening; and forming an encapsulation planar with a carrier vertical side of the carrier and an interposer vertical side of the interposer.

Abstract: Two integrated circuits having circuitry on one of their major surfaces are ground on their opposite major surfaces to reduce their thickness. The ground integrated circuits are then adhered together to form a composite body and placed in a chamber formed within a substrate such as a printed circuit board. Electrical connections are formed between contacts of the integrated circuits and contacts of the substrate. Components may be mounted on the outer surfaces of the substrate.

Abstract: This invention is directed to offer a package type semiconductor device that can realize a smaller size device and its manufacturing method as well as a small stacked layer type semiconductor device and its manufacturing method. A device component 1 and a pad electrode 4 electrically connected with the device component 1 are formed on a semiconductor substrate 2. A supporting member 7 is bonded to a surface of the semiconductor substrate 2 through an adhesive layer 6. There is formed a through-hole 15 in the supporting member 7 penetrating from its top surface to a back surface. Electrical connection with another device is made possible through the through-hole 15. A depressed portion 12 is formed in a partial region of the top surface of the supporting member 7. Therefore, all or a portion of another device or a component can be disposed utilizing a space in the depressed portion 12.

Abstract: A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer.

Abstract: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

Abstract: Methods for forming and attaching covers to microelectronic imaging units, packaging microelectronic imagers at the wafer level, and microelectronic imagers having covers that protect the image sensor are disclosed herein. In one embodiment, a method includes providing a first substrate having a plurality of covers, the covers including windows comprising regions of the first substrate and stand-offs projecting from the windows. The method continues by providing a second substrate having a plurality of microelectronic dies with image sensors, integrated circuits electrically coupled to the image sensors, and terminals electrically coupled to the integrated circuits. The method includes assembling the covers with corresponding dies so that the windows are aligned with corresponding image sensors and stand-offs contact corresponding dies inboard of the terminals and outboard of the image sensors.

Abstract: A dual face package includes a semiconductor substrate including a through-electrode connected to a die pad disposed on one side of the semiconductor substrate, and a lower redistribution layer disposed on another side thereof and connected to the through-electrode, an insulating layer including a post electrode connected to the through-electrode, and an upper redistribution layer disposed on one side thereof and connected to the post electrode, and an adhesive layer disposed on the one side of the semiconductor substrate so as to attach the insulating layer to the semiconductor substrate such that the through-electrode is connected to the post electrode.

Abstract: According to the present invention, a protective seal S1 for protecting a transparent member 11 is composed of an organic base 16, adhesive layers 17, and a second adhesive layer 18 having low adhesion. The adhesive layers 17 are provided only on edges corresponding, on the organic base 16, to sides 11b of the transparent member and the second adhesive layer 18 is provided on a portion corresponding, on the organic base 16, to a surface 11a of the transparent member. The organic base 16 is fixed to the sides 11b and the surface 11a of the transparent member 11 with the adhesive layers 17 and 18.

Abstract: A semiconductor wafer bonding product according to the present invention includes: a semiconductor wafer; a transparent substrate provided at a side of a functional surface of the semiconductor wafer; a spacer provided between the semiconductor wafer and the transparent substrate; and a bonded portion continuously provided along a periphery of the semiconductor wafer, the transparent substrate being bonded to the semiconductor wafer through the bonded portion. It is preferred that a minimum width of the bonded portion is 50 ?m or more.

Abstract: A carrier for holding a plurality of chip packages and a carrier assembly are provided, wherein the chip package has a central area without solder balls and a peripheral area with solder balls formed thereon. The carrier includes a tray component and a plurality of supports disposed on the tray component, wherein each support holds the central area of a respective chip package. The carrier assembly is formed by stacking a plurality of the carriers through a plurality of peripheral projections disposed at a periphery of each tray component, wherein each peripheral projection has a pin formed thereon and a hole formed thereunder.

Abstract: The light emitting structure disclosed includes a light emitting device, a metal frame, and a repressing fastener. The light emitting device has a plurality of first coupling terminals, and the metal frame has a plurality of second coupling portions. The light emitting device is disposed in the metal frame, and the first coupling terminals touch the second coupling portions to electrically connect the light emitting device and the metal frame. The repressing fastener is disposed on the light emitting device and fastened to the metal frame to secure the light emitting device in the metal frame. An LED securing device is also disclosed.

Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.

Abstract: An optical device is equipped with a light receiving region 16a and a peripheral circuit region 22 located around the light receiving region 16a on a major surface of an light receiving element 11a; electrodes for external connection 15 electrically connected to the peripheral circuit region 22 formed on a back surface opposite to the major surface of the light receiving element 11a; a transparent member 12 covering the light receiving region 16a adhered on the major surface of the light receiving element 11a with a light-transmitting adhesive 13; and a molding resin 14 for coating side surfaces of the transparent member 12 and the major surface of the light receiving element 11a excluding the region covered with the transparent member 12.

Abstract: A method for manufacturing a hybrid printed circuit board having two kinds of wiring boards. The circuit board has method has a first wiring board having a first terminal and, a second wiring board wherein a dent wherein the first wiring board is fitted and equipped with a second terminal is formed, and forming the same plane as the first wiring board. The board also has an insulating adhesive material disposed around the first terminal, and a conductive adhesive joining the first terminal with the second terminal.

Abstract: A nanophotonic device. The device includes a substrate, at least one light emitting structure and at least one electronic component. The at least one light emitting structure is capable of transmitting light and is monolithically integrated on the substrate. The at least one electronic component is monolithically integrated on the substrate. A method for fabricating nanophotonic devices is also described.

Abstract: Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained.

Abstract: A semiconductor package includes a chip base material; a capacitor formed on the base material; and a cover formed over the base material to cover the capacitor, and having a side portion and an upper portion. The base material is provided with a bonding pattern connecting the base material and the cover to cover the capacitor. The bonding pattern includes a region A having a substantially uniform pattern width A, and at least one region B having a pattern width B which is larger than the width pattern width A.

Abstract: A solid state light emitting device includes a laminated substrate structure (120), an LED chip (30), a transparent capsulation material (50) and an electric component (40). The laminated substrate structure includes a first substrate (10) and a second substrate (20) attached to each other by a sintering process. The first substrate has a mounting surface (100) and a receiving through hole (11) defined in the mounting surface thereof. The LED chip is mounted on the mounting surface of the first substrate. The transparent capsulation material envelops the LED chip therein. The electric component is received in the receiving hole and mounted on the second substrate. The electric component is located below the mounting surface of the first substrate.

Abstract: Provided are a semiconductor device and a touch sensor device. The semiconductor device includes a die including a sense signal generator for sensing a touch signal to generate a sense signal; a conductive die-attach pad attached to the die to generate the touch signal; and a package for packaging the die and the die-attach pad, wherein the die-attach pad generates the touch signal depending on whether a touch object comes into contact with the package. The touch sensor device includes a plurality of semiconductor devices connected in a daisy-chain communication mode, wherein each of the semiconductor devices includes a die including a sense signal generator for sensing a touch signal to generate a sense signal; a conductive die-attach pad attached to the die to generate the touch signal; and a package for packaging the die and the die-attach pad, wherein the die-attach pad generates the touch signal depending on whether a touch object is brought into contact with the package.

Abstract: An environment-resistant module which provides both thermal and vibration isolation for a packaged micromachined or MEMS device is disclosed. A microplatform and a support structure for the microplatform provide the thermal and vibration isolation. The package is both hermetic and vacuum compatible and provides vertical feedthroughs for signal transfer. A micromachined or MEMS device transfer method is also disclosed that can handle a wide variety of individual micromachined or MEMS dies or wafers, in either a hybrid or integrated fashion. The module simultaneously provides both thermal and vibration isolation for the MEMS device using the microplatform and the support structure which may be fabricated from a thin glass wafer that is patterned to create crab-leg shaped suspension tethers or beams.

Abstract: Package (1) having a sensor assembly (2) with at least one sensitive surface (21) and an attachment surface (22), a carrier element (3) with a sensor attachment area (31), and a sensor attach material (4) for attaching the sensor assembly (2) to the sensor attachment area (31) of the carrier element. The package (1) comprises an encapsulation (5) of a first material, in which the encapsulation (5) covers the sensor attachment area (31) of the carrier element (3) and the sensor attach material (4) and leaves the at least one sensitive surface (21) free from the first material.

Abstract: The semiconductor device includes a support substrate 101 on which a semiconductor element 105 to be mounted, a covering member 102 disposed to the support substrate via a bonding member, and a space 107 is defined between the covering member 102 and the support substrate 101. The support substrate 101 has a protruded portion 103 and the covering member 102 is disposed so that a portion thereof is in contact with the protruded portion 103 so as to define an air vent leading from the space 107 to outside.

Abstract: An optoelectronic module having a carrier element, at least one semiconductor component for emitting or detecting electromagnetic radiation, said semiconductor component being applied on the carrier element and being electrically conductively connected and having a radiation coupling area, and also at least one optical device assigned to the semiconductor component. A connecting layer made of a radiation-transmissive, deformable material is arranged between the radiation coupling area and the optical device, the optical device and the semiconductor component being fixed relative to one another in such a way that they are pressed against one another and that the connecting layer is thereby squeezed in such a way that it generates a force that strives to press the optical device and the radiation coupling area apart.

Abstract: Provided are an embedded wiring board and a method of manufacturing the same. The embedded wiring board includes: a printed circuit board (PCB) including a first surface and a second surface, the first surface having a concave portion; through electrodes penetrating the PCB; a semiconductor device group embedded in the concave portion of the PCB, the semiconductor device group including bonding pads exposed in a direction of the first surface of the PCB; bumps disposed on the bonding pads, exposed in the direction of the first surface of the PCB; and a film substrate including a first surface and a second surface, the first surface including connection electrode patterns that are electrically connected to the bumps and the through electrodes, the film substrate having penetrated openings.

Abstract: A stackable integrated circuit package system is provided including forming an external interconnect having an interconnect non-recessed portion and an interconnect recessed portion, mounting an integrated circuit die over a paddle that is coplanar with the interconnect recessed portion, and forming an encapsulation having a recess over the external interconnect and the integrated circuit die with the external interconnect exposed at a side of the encapsulation.

Abstract: Package for an integrated circuit (IC), includes a housing (3) of a first material having two major surfaces (4, 5). The major surfaces are substantially parallel to each other. Furthermore, a lead frame (6) is present for carrying the IC (2), the lead frame (6) including contact terminals (7) for electrical communication with the IC (2). The package (1) has a through-hole (8) in the two major surfaces (4, 5), allowing various special applications of the package (1).

Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. A cover substrate having a plurality of metal traces and a plurality of cover vias is provided. A first die is attached to the first surface of the substrate and positioned over the opening. Side members are coupled to ground planes on the base substrate and cover substrate to form an RF shield around the first die. At least one wirebond having a first end attached to the first die and a second end attached to a metal trace of the base substrate is provided. The at least one wirebond forms a loop wherein a top section of the loop contacts a metal trace of the cover substrate.

Abstract: Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.

Abstract: A thermoelectric structure for cooling an integrated circuit (IC) chip comprises a first type superlattice layer formed on top of the IC chip connected to a first voltage, and a second type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being different from the first voltage, wherein an power supply current flows through the first and second type superlattice layer for cooling the IC chip.

Abstract: A packaging substrate structure with electronic components embedded therein and a method for fabricating the same are disclosed. The packaging substrate structure comprises a core board with a wiring layer on the two opposite surfaces thereof; a first built-up structure disposed on at least one surface of the core board and having a cavity to expose the surface of the core board; an electronic component disposed in the cavity and having an active surface and an inactive surface, where the active surface has pluralities of electrode pads and the inactive surface faces the surface of the core board; and a solder mask disposed on the surfaces of the first built-up structure and the electronic component, where the solder mask has pluralities of first openings to expose the electrode pads of the electronic component. Accordingly, the packaging substrate disclosed by the present invention can efficiently enhance electrical performance and product reliability.

Abstract: A semiconductor device has a substrate. A die is attached to a first surface of the substrate. A heat sink is provided having an approximately planer member and support members extending from the planer member. The support members are attached to the first surface of the substrate to form a cavity over the die with the planer member positioned above the die. An encapsulant is provided for encapsulating the device, wherein an exterior surface of the planer member is exposed. A non-tapered opening is formed in the planer member. The encapsulant is injected through the opening to encapsulate the cavity and the encapsulant will partially fill the non-tapered opening.

Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.

Abstract: On the lower surface of a semiconductor construct having an external connection electrode, there are formed an insulating film having a planar size greater than that of the semiconductor construct, and a metal layer and a mask metal layer having a connection pad portion in which a first opening corresponding to the external connection electrode is formed. A laser beam is applied using the mask metal layer as a mask, and a second opening is thereby formed in a part of the insulating film corresponding to the external connection electrode. Then, a connection conductor is formed to connect a wiring line to the external connection electrode via the second opening of the insulating film.

Abstract: A semiconductor component includes a semiconductor element that has a plurality of signals, a wiring board that is disposed below the semiconductor element and that draws the plurality of signals of the semiconductor element, a heat conduction member that dissipates heat generated by the semiconductor element, a joining member that is disposed between the semiconductor element and the heat conduction member and that joins the heat conduction member to the semiconductor element, a support member formed with an opening so as to surround the semiconductor element that supports the heat conduction member, a first adhesive member that is disposed between the support member and the wiring board to bond the support member with the wiring board and a second adhesive member that is disposed between the support member and the heat conduction member to bond the support member with the heat conduction member.

Abstract: Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.