With Window Means Patents (Class 257/680)
  • Patent number: 7872338
    Abstract: A microelectromechanical device package with integral a heater and a method for packaging the microelectromechanical device are disclosed in this invention. The microelectromechanical device package comprises a first package substrate and second substrate, between which a microelectromechanical device, such as a micromirror array device is located. In order to bonding the first and second package substrates so as to package the microelectromechanical device inside, a sealing medium layer is deposited, and heated by the heater so as to bond the first and second package substrates together.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: January 18, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Terry Tarn
  • Patent number: 7872686
    Abstract: A integrated camera module (10, 10a) for capturing video images in very small digital cameras, cell phones, personal digital assistants, and the like. A lens assembly (24, 24a) is rigidly affixed in relation to a sensor array area (14) of a camera chip (12) by a molding (26). The molding (26) is formed on the camera chip (12), and optionally on a printed circuit board (16, 16a) on which the camera chip (12) is mounted. The lens assembly (24, 24a) is held in place in a recess (29) of the molding (26) by an adhesive (28). The molding (26) is formed such that a precise gap (30) exists between the lens assembly (24) and a sensor array area (14) of the camera chip (12).
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: January 18, 2011
    Assignee: Flextronics International USA, Inc.
    Inventors: Vidyadhar Sitaram Kale, Samuel Waising Tam, Dongkai Shangguan
  • Patent number: 7868336
    Abstract: According to the present invention, protrusions 4 are formed on electrodes 3 of semiconductor elements 6, and an optical member 7 is secured on the semiconductor element 6 with an adhesive 8 so as to be pressed onto the protrusions 4.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: January 11, 2011
    Assignee: Panasonic Corporation
    Inventors: Hiroaki Fujimoto, Yoshihiro Tomita
  • Patent number: 7863093
    Abstract: An integrated circuit (IC) die includes two bonding pads, that share a common logical function, such as signal input or signal output, separated by the width of the die, and preferably on opposite sides of the die. System-in-package devices are produced by steps including directly electrically connecting one or the other bonding pad to bonding pads of other, functionally different IC dies, with the bonding pads of the other IC dies, to which are connected bonding pads of common logical function of the IC dies of the present invention, being functionally identical but geometrically different. Multichip package devices are produced by stacking the IC dies of the present invention with other IC dies and directly electrically connecting one or the other bonding pad to different bonding pads of the other IC dies.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: January 4, 2011
    Assignee: SanDisk IL Ltd
    Inventor: Amir Ronen
  • Patent number: 7855441
    Abstract: A semiconductor card package and a method of manufacturing the semiconductor cared package are provided. The package may include a housing having a cavity. The cavity may have a size corresponding to at least one standard semiconductor package. External terminals may be exposed on the outside of the housing. Internal terminals may be disposed in the cavity. At least one internal semiconductor package may be inserted into the cavity. The internal semiconductor package includes I/O terminals. Each of the I/O terminals is connected to a corresponding one of the internal terminals.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: December 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chang-Hoon Han
  • Patent number: 7847381
    Abstract: According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of alignment features disposed thereon, the monolithic frame having a mounting surface disposed thereon for the integrated circuit, the monolithic frame also having a thermal interface area disposed thereon for the integrated circuit. The device also includes an electrical interface capable of providing an electrical connection for the integrated circuit, the plurality of alignment features being substantially independent of the electrical interface, and an adhesive layer disposed between the monolithic frame and the electrical interface.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: December 7, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Paul L. Rancuret, John T. McKinley
  • Patent number: 7842546
    Abstract: An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Jinbang Tang
  • Patent number: 7842552
    Abstract: A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: November 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: John Peter Karidis, Mark Delorman Schultz
  • Publication number: 20100283139
    Abstract: The present invention relates to a semiconductor device package having a chip with a conductive layer. The semiconductor device package includes a substrate, a chip, at least one first electrical connecting element and at least one second electrical connecting element. The substrate has a first surface and a first circuit layer. The first circuit layer is disposed adjacent to the first surface. The chip is attached to the substrate and has a surface, at least one first pad, a plurality of second pads and a conductive layer. The first pad, the second pads and the conductive layer are disposed adjacent to the surface, and the conductive layer connects the second pads. The first electrical connecting element and the second electrical connecting element electrically connect the substrate to the chip. Therefore, the conductive layer of the chip has the effects of controlling the characteristic impedance and increasing the signal integrity.
    Type: Application
    Filed: February 16, 2010
    Publication date: November 11, 2010
    Inventors: Hung-Hsiang CHENG, Chih-Yi HUANG
  • Patent number: 7825484
    Abstract: A micromachined microphone is formed from a silicon or silicon-on-insulator (SOI) wafer. A fixed sensing electrode for the microphone is formed from a top silicon layer of the wafer. Various polysilicon microphone structures are formed above a front side of the top silicon layer by depositing at least one oxide layer, forming the structures, and then removing a portion of the oxide underlying the structures from a back side of the top silicon layer through trenches formed through the top silicon layer. The trenches allow sound waves to reach the diaphragm from the back side of the top silicon layer. In an SOI wafer, a cavity is formed through a bottom silicon layer and an intermediate oxide layer to expose the trenches for both removing the oxide and allowing the sound waves to reach the diaphragm. An inertial sensor may be formed on the same wafer, with various inertial sensor structures formed at substantially the same time and using substantially the same processes as corresponding microphone structures.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: November 2, 2010
    Assignee: Analog Devices, Inc.
    Inventors: John R. Martin, Timothy J. Brosnihan, Craig Core, Thomas Kieran Nunan, Jason Weigold, Xin Zhang
  • Patent number: 7825500
    Abstract: A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: November 2, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chien-Hao Wang
  • Patent number: 7825519
    Abstract: A multilayered integrated optical and circuit device. The device has a first substrate comprising at least one integrated circuit chip thereon, which has a cell region and a peripheral region. Preferably, the peripheral region has a bonding pad region, which has one or more bonding pads and an antistiction region surrounding each of the one or more bonding pads. The device has a second substrate with at least one or more deflection devices thereon coupled to the first substrate. At least one or more bonding pads are exposed on the first substrate. The device has a transparent member overlying the second substrate while forming a cavity region to allow the one or more deflection devices to move within a portion of the cavity region to form a sandwich structure including at least a portion of the first substrate, a portion of the second substrate, and a portion of the transparent member.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: November 2, 2010
    Assignee: Miradia Inc.
    Inventors: Xiao Yang, Dongmin Chen, Philip Chen
  • Patent number: 7821135
    Abstract: A semiconductor device of improved stress-migration resistance and reliability includes an insulating film having formed therein a lower interconnection consisting of a barrier metal film and a copper-silver alloy film, on which is then formed an interlayer insulating film. In the interlayer insulating film is formed an upper interconnection consisting of a barrier metal film and a copper-silver alloy film. The lower and the upper interconnections are made of a copper-silver alloy which contains silver in an amount more than a solid solution limit of silver to copper.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kazuyoshi Ueno
  • Patent number: 7821117
    Abstract: A semiconductor package (20) includes an organic substrate (24) and a semiconductor die subassembly (22). A method (50) for making the semiconductor package (20) entails providing (52) the organic substrate (24) having an opening (26) and electrical contacts (36). The subassembly (22) is formed by producing (64) a semiconductor die (28) and bonding it to a platform layer (30). An elastomeric adhesive (38) is utilized (92) to secure the subassembly (22) in the opening (26). Electrical interconnects (32) are provided (106) between the semiconductor die (28) and the electrical contacts (36) of the organic substrate (24). The organic substrate (24), semiconductor die (28), elastomeric adhesive (38), and electrical interconnects (32) are encapsulated (114) in a packaging material (46). The elastomeric adhesive (38) provides mechanical anchoring of the subassembly (22) to the substrate (24) and provides mechanical stress isolation of the semiconductor die (28) within the semiconductor package (20).
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: October 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Clem H. Brown, Vasile R. Thompson
  • Publication number: 20100264532
    Abstract: Various embodiments for molding tools for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding an image sensor chip, and a transparent cover. The housing structure may cover substantially all of the interposer chip surface. In another embodiment, the housing structure also covers substantially all of the interposer edge surfaces. The housing structure may also cover substantially all of the interposer attachment surface. An image sensor chip is electrically connected to the interposer with sealed wire bond connections or with sealed flip-chip connections. The housing structure may include runners that enable simultaneous sealing of the interior of the image sensor package and of the transparent cover.
    Type: Application
    Filed: October 14, 2009
    Publication date: October 21, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Todd O. Bolken, Cary J. Baerlocher, Steven W. Heppler, Chad A. Cobbley
  • Patent number: 7812264
    Abstract: A functional element-mounted module can be decreased in size and requires no costly and special members for a light transition member. A substrate is used, on which an optical functional element having an optical function part and bonding pads therearound is mounted by wire bonding, with an upper face of the element upward. A bank to dam a liquid sealing resin is provided around the optical functional element on the substrate, and the liquid sealing resin is dropped and filled between the optical functional element and the bank such that the bonding pads and partial gold wires for the wire bonding are exposed. A package-component member having a hole corresponding to the optical functional element is abutted to the bank such that the hole is opposed to the function part of the functional element. Thereby, the package-component member is contacted to the liquid sealing resin. The package-component member is fixed to the substrate by curing the liquid sealing resin, and the bank is cut away.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: October 12, 2010
    Assignees: Sony Corporation, Sony Chemical & Information Device Corporation
    Inventors: Yoshihiro Yoneda, Takahiro Asada, Kazuaki Suzuki
  • Patent number: 7812433
    Abstract: A package structure and an electronic device using the same are provided. The package structure includes a chip module and a cover. The chip module covered by the cover is used for receiving a first signal. The chip module includes a substrate, a heat sink and a first chip. The substrate has a first surface, a second surface and an opening. The first surface is opposite to the second surface. The opening penetrates the first surface and the second surface. The heat sink is disposed on the first surface of the substrate and covers the opening. The first chip is disposed on the heat sink and is positioned inside the opening. A bottom surface of the first chip flatly contacts the heat sink. The cover has a window element. The first signal passes through the window element to contact with the chip module.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: October 12, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Mi-Cheng Cheng, Kuo-Hua Chen
  • Patent number: 7812447
    Abstract: A pre-packaged flip chip package that includes one or more dice on a semiconductor wafer is disclosed. In the various embodiments, an adhesive layer may be applied to a first side of a finished wafer, having connector pads formed thereon. The adhesive layer may include openings through which the connector pads may be accessed. Conductive elements may be positioned within the adhesive, and configured to electrically couple to the conductive elements.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: October 12, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Suan Jeung Boon
  • Patent number: 7800119
    Abstract: A semiconductor lamp having a light-emitting semiconductor device, the semiconductor device comprising a carrier and at least one light-emitting semiconductor component on the carrier, and a heatsink. The heatsink has a first main face, the semiconductor device is located adjacent to the first main face, and the carrier faces the first main face. The semiconductor device is thermally coupled to the heatsink, and the heatsink has at least one feedthrough for electrical connection of the semiconductor device.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: September 21, 2010
    Assignee: OSRAM Gesellschaft mit beschrankänkter Haftung
    Inventors: Xiyuan He, Rui Ma, Wolfgang Georg Pabst, Giovanni Scilla
  • Patent number: 7791193
    Abstract: An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer is meshed.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: September 7, 2010
    Assignee: NVIDIA Corporation
    Inventors: Inderjit Singh, Howard Lee Marks, Joseph David Greco
  • Patent number: 7791184
    Abstract: A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: September 7, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Kyle K. Kirby, Warren M. Farnworth, Salman Akram
  • Publication number: 20100219521
    Abstract: A window-type semiconductor package is revealed, primarily comprising a substrate with an interconnection channel, a chip on the substrate, a die-attach adhesive between the chip and the substrate, and an encapsulant filling the interconnection channel. A first solder mask formed on the top surface of the substrate has a specific pattern. The die-attach adhesive bonds the active surface of the chip to the first solder mask with the bonding pads of the chip aligned inside the interconnection channel. The first solder mask has an opening to expose the interconnection channel and further to form an indentation from the interconnection channel to expose the top surface to prevent damaging of the active surface of the chip adjacent to the edges of the interconnection channel to ensure the integrity and yield of the final products.
    Type: Application
    Filed: May 8, 2009
    Publication date: September 2, 2010
    Inventors: Kuo-Yuan LEE, Yung-Hsiang Chen, Wen-Chun Chiu
  • Patent number: 7786500
    Abstract: The present invention is an LED lamp lens, on which orderly arranged surface plural protuberances. And with the differences of light perviousness, a particular luminous pattern of the LED lamp is displayed when the LED lamp is turned on.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: August 31, 2010
    Assignee: Everlight Electronics Co., Ltd.
    Inventors: Jing-Yi Tsai, Chun-Chih Liang
  • Patent number: 7786560
    Abstract: A package structure including a chip, a lid, a substrate, a plurality of wires, an encapsulant, and a moisture resistive layer is provided. The chip has an active area where at least one MEMS device is disposed. The lid is covered on the chip, and the substrate is used to carry the chip and the lid. The plurality of wires is electrically connected between the substrate and the chip. The encapsulant is sealed around the lid and exposes an upper surface of the lid. The moisture resistive layer is covered on the encapsulant to enhance the airtightness and the moisture resistance of the encapsulant.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: August 31, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Li-Ching Hong
  • Patent number: 7781855
    Abstract: An optical device includes a metal film that has a first plane and a second plane electrically connected to the first plane. For example, the second plane is integrally formed with the first plane. The second plane is arranged at an obtuse angle ? (90°<?<180°) with respect to the first plane. An optical semiconductor chip is mounted on the second plane of the metal film, and a light-transmitting sealing material seals the optical semiconductor chip. The light-transmitting sealing material has the metal film provided on a surface thereof.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: August 24, 2010
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Iwao Shoji
  • Patent number: 7781852
    Abstract: A circuit element package has a substrate having a plurality of electrically conductive patterns, a die pad, and an access hole formed through the die pad and substrate. A plurality of leads is coupled to the substrate. A circuit element die is attached to the die pad wherein a first sensor port is positioned over the access hole. A die attach membrane is provided for attaching the circuit element die to the die pad. The die attach membrane allows the circuit element die to sense ambient while protecting the circuit element die from environmental damage. An encapsulant is used for covering portions of the circuit element die.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: August 24, 2010
    Assignee: Amkor Technology, Inc.
    Inventors: Faheem F. Faheem, Christopher M. Scanlan, Christopher J. Berry
  • Patent number: 7781236
    Abstract: An optical element mounting method includes: illuminating ultraviolet light onto a polymer optical waveguide device; under the ultraviolet light illumination, capturing, by an image pickup device, the polymer optical waveguide device including a light incident/exiting position of a waveguide core; and judging, from a difference between bright and dark in a captured image, that a portion brighter than other portions or a portion darker than other portions is the light incident/exiting position of the waveguide core.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: August 24, 2010
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Toshihiko Suzuki, Shigemi Ohtsu, Keishi Shimizu, Kazutoshi Yatsuda, Akira Fujii, Eiichi Akutsu
  • Patent number: 7777314
    Abstract: A package of the present invention has a laminate structure formed by laminating a plurality of ceramic layers, and has a mount surface to be a joint surface when mounted on a mother board, defined parallel with the laminating direction. A first ceramic layer has a recess with an L-shaped cross section across the mount surface and a side surface, defined at each end thereof in a direction perpendicular to the laminating direction, and an external electrode formed on each recess, the external electrode having a surface thereof exposed to the mount surface.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: August 17, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masanori Hongo, Masami Fukuyama
  • Patent number: 7777247
    Abstract: A mounting substrate for a semiconductor light emitting device includes a thermally conductive mounting block. The mounting block has, in a first face thereof, a cavity that is configured to mount a semiconductor light emitting device therein and to reflect light that is emitted by the semiconductor light emitting device that is mounted therein away from the cavity. A conductive lead inserted into the mounting block extends into the cavity. The conductive lead is electrically isolated from the mounting block and has an exposed contact portion in the cavity. The conductive lead may be a plurality of conductive leads each having an exposed contact portion at different locations in the cavity. Related packaging methods also may be provided.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: August 17, 2010
    Assignee: Cree, Inc.
    Inventors: Ban P. Loh, Gerald H. Negley, Yankun Fu
  • Patent number: 7776640
    Abstract: An image sensing device and a packaging method thereof is disclosed. The packaging method includes the steps of providing an adhesive layer; placing a substrate, having an opening, on the adhesive layer; disposing an image sensor within the opening on the adhesive layer; adding a filler between the image sensor and the substrate; connecting the image sensor and the substrate via a plurality of bonding wires; and removing the adhesive layer.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: August 17, 2010
    Assignee: Tong Hsing Electronic Industries Ltd.
    Inventors: Cheng-Lung Chuang, Chi-Cheng Lin
  • Patent number: 7772694
    Abstract: An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: August 10, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Jinbang Tang
  • Patent number: 7768111
    Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: August 3, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Iwasaki
  • Patent number: 7768112
    Abstract: A method for cutting and molding in small windows of a window-type semiconductor package and the semiconductor package fabricated from the same are revealed. According to the method, a substrate strip has a plurality of small windows disposed at the sides or at the corners of the substrate strip. The external surface of the substrate strip includes a plurality of window molding areas surrounding the small windows and extending to the scribe lines. A plurality of chips are disposed on the substrate strip. Then, an encapsulant is formed in the small windows to encapsulate the electrical connecting components and formed on the window molding areas so that the encapsulant extends to the scribe lines. Therefore, the mold flashes at the small windows can be effectively reduced.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: August 3, 2010
    Assignee: Walton Advanced Engineering Inc.
    Inventors: Kuo-Yuan Lee, Yung-Hsiang Chen
  • Patent number: 7763959
    Abstract: A heat slug is provided for a package structure, including a main body and a plurality of protrusions. The main body has a surface in which at least one ditch is defined. Each protrusion is connected to and extends from the main body and has a surface in which a plurality of dimples is defined.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: July 27, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-cheng Liu, Jun-cheng Liu, Hsin-hao Chen, Chi-ming Chen
  • Publication number: 20100164081
    Abstract: According to one embodiment, a micro-optical device includes an electro-optical circuit and an annular frame disposed on a surface of a substrate. The electro-optical circuit has an active region that is encapsulated by a window and an interconnect region adjacent at least one edge of the electro-optical circuit. The annular frame extends around an outer periphery of the window and is separated from the window by a gap, the annular frame and the electro-optical circuit form a cavity for placement of a plurality of bonding wires the interconnect that electro-optical circuit to the substrate.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Bradley Morgan Haskett, John Patrick O'Connor, Mark Myron Miller, Sean Timothy Crowley, Jeffery Alan Miks, Mark Phillip Popovich
  • Publication number: 20100164082
    Abstract: The reliability of a photosensor-type semiconductor device is enhanced. The sealing step in a manufacturing process for the semiconductor device is carried out as described below. A molding die having an upper die and a lower die is prepared and a film is arranged between the upper die and the lower die. A lead frame in which first adhesive, a semiconductor chip, second adhesive 11, and a base material are mounted over the upper surface of each tab is arranged between the film and the lower die. The base material has an opening formed therein and the opening is covered with a protective sheet. The semiconductor chip has a light receiving area formed in its main surface. The upper die and the lower die are clamped to cause part of the base material to bite into the film. Thereafter, sealing resin is supplied to between the film and the lower die to form a blanket sealing body. Thus the photosensor-type semiconductor device without resin flash over the light receiving area is obtained.
    Type: Application
    Filed: December 26, 2009
    Publication date: July 1, 2010
    Inventor: Atshushi Fujisawa
  • Patent number: 7745897
    Abstract: An image sensor is packaged by attaching the image sensor to a substrate, forming metallic bumps on either the image sensor or a transparent cover, where the metallic bumps are formed in a pattern around the perimeter of the active area of the image sensor. The transparent cover is then glued to the image sensor at the metallic bumps. Electrical connections are formed between the image sensor and the substrate using, for example, conventional wire bonding techniques. The electrical connections are encapsulated within an epoxy for protection. In an embodiment, multiple image sensors are packaged together on the same substrate and separated into individually packaged image sensors by, for example, sawing.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: June 29, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Cheng Why Tan, Piang Joon Seow
  • Patent number: 7745944
    Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: June 29, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Setho Sing Fee
  • Publication number: 20100155917
    Abstract: A semiconductor device includes: a semiconductor element having a light receiving region or a light emitting region on which a transparent member is attached, and a plurality of electrode pads; a substrate on which the semiconductor element is provided; and a resin covering the semiconductor element and side surfaces of the transparent member. The first area corresponding to part of an upper surface of the semiconductor element, which part is covered with the resin is smaller than the second area corresponding to parts of a lower surface of the semiconductor element and a lower surface of the substrate, which parts are covered with the resin.
    Type: Application
    Filed: November 4, 2009
    Publication date: June 24, 2010
    Inventor: Tetsumasa MARUO
  • Publication number: 20100148293
    Abstract: An implantable, miniaturized platform and a method for fabricating the platform is provided, where the e platform includes a top cover plate and a bottom substrate, top cover plate including an epitaxial, Si-encased substrate and is configured to include monolithically grown devices and device contact pads, the Si-encased substrate cover plate including a gold perimeter fence deposited on its Si covered outer rim and wherein the bottom substrate is constructed of Si and includes a plurality of partial-Si-vias (PSVs), electronic integrated circuits, device pads, pad interconnects and a gold perimeter fence, wherein the device pads are aligned with a respective device contact pad on the top cover plate and includes gold bumps having a predetermined height, the top cover plate and the bottom substrate being flip-chip bonded to provide a perimeter seal and to ensure electrical connectivity between the plurality of internal devices and at least one external component.
    Type: Application
    Filed: November 16, 2009
    Publication date: June 17, 2010
    Inventors: Faquir Chand Jain, Fotios Papadimitrakopulos
  • Patent number: 7723811
    Abstract: A packaged micro-electromechanical systems (MEMS) device assembly includes a MEMS device, a substrate within which the MEMS device is disposed, and a lid disposed over the substrate. The assembly may include one or more first cavities within the lid having a predetermined volume satisfying packaging specifications for the packaged MEMS device assembly. The assembly may include one or more second cavities within the lid and one or more corresponding overflow areas within the lid, where each second cavity contains a material and each corresponding overflow area is adapted to catch overflow of the material. The assembly may include one or more third cavities within the lid and one or more channels within one of the substrate and the lid to fluidically connect the MEMS device to the third cavities.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: May 25, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Charles C Haluzak, Jeffrey R Pollard, Kirby Sand, John R Sterner, Henry Kang, Chien-Hua Chen, James Denning Smith
  • Patent number: 7719085
    Abstract: A semiconductor device 1 includes an interconnect 12, a conductive layer 14 (first conductive layer), an insulating layer 20 (first insulating layer), another conductive layer 30 (second conductive layer), another insulating layer 40 (second insulating layer), a via plug 52 (first via plug), and another via plug 54 (second via plug). In the semiconductor device 1, the conductive layer 14, the insulating layer 20 and the conductive layer 30 constitute a MIM capacitor (capacitor element). To be more detailed, the conductive layer 14, the insulating layer 20 and the conductive layer 30 serve as a lower electrode, an insulating capacitor film and an upper electrode, respectively. The insulating layer 40 covers both the conductive layer 30 and the interconnect 12. The insulating layer 40 works as the etching stopper for the via plugs 52, 54.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: May 18, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takuji Onuma, Yasutaka Nakashiba
  • Patent number: 7719097
    Abstract: A semiconductor device includes a semiconductor element, a transparent member separated from the semiconductor element by a designated length and facing the semiconductor element, a sealing member sealing an edge surface of the transparent member and an edge part of the semiconductor element, and a shock-absorbing member provided between the edge surface of the transparent member and the sealing member and easing a stress which the transparent member receives from the sealing member or the semiconductor element.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: May 18, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Naoyuki Watanabe
  • Patent number: 7709912
    Abstract: An electronic device, including a substrate, a functional structure constituting a functional element formed on the substrate, and a cover structure forming a cavity portion in which the functional structure is disposed, is disclosed. In the electronic device, the cover structure includes a laminated structure of an interlayer insulating film and a wiring layer, the laminated structure being formed on the substrate in such a way that it surrounds the cavity portion, and the cover structure has an upside cover portion covering the cavity portion from above, the upside cover portion being formed with part of the wiring layer that is disposed above the functional structure.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: May 4, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Akira Sato, Toru Watanabe, Shogo Inaba, Takeshi Mori
  • Publication number: 20100103389
    Abstract: A system and method for packaging multiple MEMS devices is disclosed. A preferred embodiment comprises two or more MEMS devices, such as DMD devices, packaged together into a single package. The MEMS devices can be either on a single substrate or else on multiple substrates, and may be aligned together or not aligned together depending upon the desired orientation of the MEMS devices.
    Type: Application
    Filed: October 28, 2008
    Publication date: April 29, 2010
    Inventors: Kenneth Brian McVea, Bryce Daniel Sawyers
  • Patent number: 7701044
    Abstract: A chip package for an image sensor includes a first semiconductor chip having a first surface where a photographing device and a first circuit pattern are formed and a second surface that is opposite to the first surface where a second circuit pattern is formed. The first and second circuit patterns are electrically connected. The chip package further includes a second semiconductor chip attached to a second circuit pattern on the second surface of the first semiconductor chip. A printed circuit board faces the second surface of the first semiconductor chip and transfers an electric signal between the first and second semiconductor chips and externally. A housing accommodates the first and second semiconductor chips. The housing allows light to pass through to the photographing device.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: April 20, 2010
    Assignee: Samsung Techwin Co., Ltd.
    Inventors: Byoung-young Kang, San-deok Hwang
  • Publication number: 20100091633
    Abstract: A flat pre-board plate including connection electrodes, internal interconnections, and external-connection portions is prepared. This pre-board plate is cut at portions each located between adjacent ones of the connection electrodes, thereby forming trenches. A plurality of semiconductor elements are placed in each of the trenches. Electrode pads and the connection electrodes are connected to each other by metal wires. Transparent lids are placed on, and bonded to, spacers to cover the semiconductor elements. Thereafter, two lines of the connection electrodes arranged between adjacent ones of the trenches are separated from each other. Subsequently, adjacent ones of the semiconductor elements are also separated from each other.
    Type: Application
    Filed: March 10, 2008
    Publication date: April 15, 2010
    Inventors: Junya FuruyashikiI, Syouzou Moribe, Hiroki Utatsu, Noriyuki Yoshikawa, Toshiyuki Fukuda, Masanori Minamio, Hiroyuki Ishida
  • Patent number: 7696614
    Abstract: A driver module structure includes a flexible circuit board (2) provided with a wiring pattern (7), a semiconductor device mounted on the flexible circuit board (2), and an electrically conductive heat-radiating member (4) joined to the semiconductor device. The wiring pattern (7) includes a ground wiring pattern (8). The flexible circuit board (2) has a cavity (9) that exposes a portion of the ground wiring pattern (8). The exposed portion of the ground wiring pattern (8) and the heat-radiating member (4) are connected to establish electrical continuity via a member (11) that is fitted into the cavity (9).
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: April 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Hiroyuki Fukusako, Kazunori Seno
  • Patent number: 7696590
    Abstract: A housing accommodating a semiconductor chip is set out. The housing and chip may be used for sending and/or receiving radiation. Popular applications of the housing may be in light emitting diodes. The housing includes a conductor strip that is punched into two electrically isolated portions. The housing further includes a cavity extending inwards from the top of the housing. The conductor portions include respective areas that are exposed at the bottom of the cavity. The semiconductor chip is bonded to one of the exposed areas and a wire bonds the chip to the second exposed area. The conductor portions also terminate in exposed electrodes, which allow for electrical connection of the chip with external devices. A window is formed in the cavity and the walls of the housing that form the cavity may be made of a reflective material. The electrodes remain unexposed to the window but for any residual areas about the chip and bonding wire within the first and second exposed areas.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: April 13, 2010
    Assignee: OSRAM GmbH
    Inventors: Gunter Waitl, Herbert Brunner
  • Patent number: RE41722
    Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: September 21, 2010
    Assignee: Renesas Electronics Corp.
    Inventors: Atsushi Nakamura, Kunihiko Nishi