Abstract: Methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity.

Abstract: A semiconductor package having a structure in which a decoupling capacitor is disposed to be adjacent with a semiconductor chip using a vertical chip interconnection (VCI) to improve power integrity. The semiconductor package includes a semiconductor substrate including a first finger pad and a second finger pad, a semiconductor chip mounted on the semiconductor substrate and including a first chip pad and a second chip pad, a bonding tape electrically connecting the first finger pad and the first chip pad, and a bonding wire electrically connecting the second finger pad and the second chip pad. Here, the bonding tape is formed to make contact with a sidewall of the semiconductor chip in a vertical direction of the semiconductor chip.

Abstract: Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor, an impedance matching circuit, and a video bandwidth circuit. The impedance matching circuit is coupled between the transistor and an RF I/O (e.g., an input or output lead). The video bandwidth circuit is coupled between a connection node of the impedance matching circuit and a ground reference node. The video bandwidth circuit includes a plurality of components, which includes an envelope inductor and an envelope capacitor coupled in series between the connection node and the ground reference node. The video bandwidth circuit further includes a first bypass capacitor coupled in parallel across one or more of the plurality of components of the video bandwidth circuit.

Abstract: A high-frequency package has: a resin substrate; a high-frequency device mounted on a side of a first surface of the resin substrate; a ground surface conductor of a ground potential formed on a second surface of the resin substrate on an opposite side to the first surface; a transmission line for a high-frequency signal formed in an inner layer of the resin substrate; and a ground via of a ground potential formed within the resin substrate. A through hole is formed in the ground surface conductor. The ground via is placed between the transmission line and the through hole.

Abstract: A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.

Abstract: The semiconductor device 1 includes an insulating substrate 2, a conductive part 3 that extends in a first direction, a conductive part 4 that is separated in a second direction and extends in the first direction, conductive parts 5 that are lined along the first direction between the part 3 and the part 4, high-side switches 11, 12 and 13, low-side switches 14, 15 and, signal terminals that are arrayed along the first direction, a power supply terminal 21 that is electrically connected to the part 3, a ground terminal 22 that is electrically connected to the part 4, and output terminals 23, 24 and 25 that are electrically connected respectively to the corresponding parts 5, arrayed along the first direction on the other end side of the substrate 2, and provided over a straight line L that passes through the part 4 and extends in the first direction.

Abstract: A die package having a plurality of connection pads, a die substrate supporting a plurality of connection elements, a first lead having a first metal core with a first core diameter, and a dielectric layer surrounding the first metal core, the dielectric layer having a first dielectric thickness that varies along its length and/or the dielectric layer having an outer metal layer at least partially surrounding the dielectric layer, for selectively modifying the electrical characteristics of the lead.

Abstract: Some of the embodiments of the present disclosure provide a Quad Flat No-Lead package comprising: an outer row of outer peripheral leads disposed on an outer periphery of a bottom surface of the Quad Flat No-Lead package; and an inner row of inner peripheral leads disposed on an inner periphery of the bottom surface of the Quad Flat No-Lead package, wherein each of the inner peripheral leads has a substantially rectangular shape, and wherein the substantially rectangular shape has two rounded corners adjacent to the outer row of outer peripheral leads.

Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: An integrated power module is provided, which may include a gate driver circuit, a plurality of first metal plates, a plurality of chips, a plurality of second metal plates, and an annular frame. The first metal plates may be parallel to each other/one another, and electrically coupled to the gate driver circuit; at least one of the first metal plates may include a plurality of chip slots. The chips may be disposed at the chip slots; each of the chips may be electrically coupled to one of the adjacent first metal plates. The second metal plates may be parallel to each other/one another, and electrically coupled to the gate driver circuit; each of the second metal plates may be disposed between any two adjacent first metal plates. The first metal plates, the second metal plates, the gate driver circuit, and the chips may be disposed inside the annular frame.

Abstract: A power semiconductor module comprising internal load and auxiliary connection devices embodied as wire bonding connections. A substrate has a plurality of load and auxiliary potential areas, wherein a power switch is arranged on a first load potential area, said power switch being embodied as a plurality of controllable power subswitches arranged in series. The power subswitches have a load bonding connection consisting of a plurality of load bonding wires to a second load potential area, wherein a first bonding base is arranged on the second load potential area and an adjacent second bonding base of the respective load bonding wire is arranged on a contact area of the power subswitch.

Abstract: A microchip including an outer chamber, compartment, or bladder; an inner chamber, compartment, or bladder inside said outer chamber, compartment, or bladder; an internal sipe separating at least a part of said inner and outer chambers, compartments, or bladders, and a Faraday cage. The microchip is configured to connect to a network of computers and includes an internal hardware firewall configured to deny access a protected portion of the microchip from the network. The sipe is formed by at least a portion of both an inner surface of the outer chamber, compartment, or bladder and an outer surface of the inner chamber, compartment, or bladder. The surface portions forming the sipe oppose each other and can move relative to each other in a sliding motion. At least a portion of an outer surface of the outer chamber, compartment, or bladder is proximate to an outer surface of the microchip.

Abstract: Aspects of the disclosure provide a printed circuit board (PCB) structure. The PCB structure includes a plurality of dielectric layers including an outer layer, a second layer disposed immediately below the outer layer, at least one first power plane disposed on at least one first internal layer of the PCB structure, and at least one first ground plane disposed on at least one second internal layer of the PCB structure. The PCB structure further includes an array of buried vias passing through at least the second layer configured to respectively connect power pads disposed on the second layer to the at least one first power plane and to connect ground pads disposed on the second layer to the at least one first ground plane.

Abstract: A layout of a switching power converter, wherein the switching power converter includes: a capacitor unit receiving or outputting DC voltage; six power transistor units transforming the DC voltage to the AC voltage or the AC voltage to the DC voltage; and a carrier board with the capacitor unit and the six power transistor units on. The layout of the switching power converter includes a first commutation loop and a second commutation loop, in which the six power transistor units are arranged on the same surface of the carrier board. In order to ensure the first commutation loop and the second commutation loop as short as possible, the fifth power transistor unit is located at a middle position of the carrier board, surrounded by the other five power transistor units as closely as possible.

Abstract: A package includes a bottom substrate and a bottom die over and bonded to the bottom substrate. A metal-particle-containing compound material is overlying a top surface of the bottom die, wherein the metal-particle-containing compound material comprises metal particles. A molding material molds at least a lower part of the bottom die therein, wherein the molding material is overlying the bottom substrate.

Abstract: An electronic assembly for use in space missions that includes a PCB and one or more multi-pin CGA devices coupled to the PCB. The PCB has one or more via-in-pad features and each via-in-pad feature comprises a land pad configured to couple a pin of the one or more multi-pin CGA devices to the via. The PCB also includes a plurality of layers arranged symmetrically in a two-halves configuration above and below a central plane of the PCB.

Abstract: An apparatus having a plurality of insulating layers, a plurality of conductive layers and a plating is disclosed. The conductive layers may be separated by the insulating layers. A first pattern in a first of the conductive layers generally extends to an edge castellation. A second pattern in a second of the conductive layers may also extends to the edge castellation. The plating may be disposed in the edge castellation and connect the first pattern to the second pattern. The plating in the castellation may extend at most between a subset of the conductive layers.

Abstract: A battery voltage monitor circuit for monitoring a voltage of plural secondary batteries includes first and second logic circuit parts that select first and second secondary batteries from the plural secondary batteries according to first and second command signals supplied from an external device, first and second reference voltage generation parts that generate first and second reference voltages, first and second AD conversion parts that digitalize a voltage of both ends of the first and second secondary batteries into first and second digital signals by using the first and second reference voltages, first and second communication parts that transmit the first and second digital signals to the external device.

Abstract: A hybrid circuit assembly includes an integrated metal substrate (IMS) having high-voltage, high-power components mounted thereon. The IMS includes a metal base plate an insulating adhesive on the metal base plate, and one or more wiring layers on the insulating adhesive. The hybrid circuit assembly includes a multi-layer printed wiring board (PWB) having low-voltage, low-power components mounted thereon. The multi-layer PWB is connected to the IMS and has an upper surface that is co-planar with an upper surface of the IMS. The PWB is mounted on the metal base plate via the insulating adhesive.

Abstract: An electronic package is disclosed, which includes: a substrate; at least an electronic element disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic element; and an antenna body embedded in the encapsulant without contacting with the substrate and exposed from a surface of the encapsulant. Since the antenna body is not disposed on the substrate, the surface area of the substrate can be reduced to meet the miniaturization requirement of the electronic package.

Abstract: A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit.

Abstract: An inter-stage test structure for a wireless communication apparatus is provided. The wireless communication apparatus has a unit under test (UUT) and a next-stage component connected to the UUT through a signal wire. The inter-stage test structure is disposed on the signal wire and electrically connects the UUT to the next-stage unit component. The inter-stage test structure includes an upper board, a lower board, and an intermediate layer. The intermediate layer is disposed between the upper board and the lower board. The intermediate layer includes a first region and a second region defined thereon. The first region has an air cavity for generating an air impedance. The second region has an impedance adjusting cavity for generating an adjustable impedance. Accordingly, the inter-stage test structure can detect the condition of the UUT of the wireless communication apparatus based on the air impedance and the adjustable impedance.

Abstract: A power converter for converting DC power to AC power by switching operation of a switching element includes: a bridge circuit configured by at least two series circuits using, as power input terminals, terminals on both sides of two switching elements connected to each other in series and using, as a power output terminal, a connection point of the two switching elements are connected in parallel via the power output terminal; a gate drive circuit for outputting a driving signal which controls to turn on/off the switching elements; and signal lines using a driving signal output terminal in the gate drive circuit as a starting point of wiring, individually hard-wired to each of the switching elements in each of series circuits to which the same driving signal is supplied from the driving signal output terminal, and having inductances which are configured equal to each other.

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.

Abstract: A power module substrate including an insulating substrate, a circuit layer formed on one surface of the insulating substrate, and a metal layer formed on the other surface of the insulating substrate, wherein the circuit layer is composed of copper or a copper alloy, one surface of this circuit layer functions as an installation surface on which an electronic component is installed, the metal layer is formed by bonding an aluminum sheet composed of aluminum or an aluminum alloy, a thickness t1 of the circuit layer is within a range of 0.1 mm?t1?0.6 mm, a thickness t2 of the metal layer is within a range of 0.5 mm?t2?6 mm, and the relationship between the thickness t1 of the circuit layer and the thickness t2 of the metal layer satisfies t1<t2.

Abstract: An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.

Abstract: A connecting device to connect an electronic component of an electronic device such as a portable terminal to another connection point such as a connection point of a main circuit board. The connection device includes at least a pair of conducting wires extending from the electronic component; a board connected to an end of the conducting wires; and at least two connecting members provided on one surface of the board, which are electrically coupled to the respective conducting wires. The connecting device so configured does not require a process of soldering or of coupling a connector to a socket to make a connection to the connection point, and makes it easy to standardize/commonly use an electronic component, thereby allowing the unit price of an electronic component, and the manufacturing costs of the electronic device to be reduced.

Abstract: Exemplary embodiments provide a substrate for mounting multiple power transistors. The substrate has a first metallization on which the power transistors are mountable with an associated collector or emitter, and which extends in at least one line on the substrate. A second metallization extends in an area next to the at least one line of the first metallization, for connection to the remaining ones of the emitters or collectors of the power transistors. A third metallization allows connection to gate contact pads of the power transistors. The third metallization includes a gate contact and at least two gate metallization areas, which are interconnectable. The gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line. At least one gate metallization area is provided as a gate island surrounded on the substrate by the second metallization.

Abstract: A heat-dissipation structure for a motor controller. The heat-dissipation structure includes a control box, a circuit board, a plurality of radiators, and IGBT modules. The circuit board is installed in the control box. Each radiator includes a side plate and a heat dissipation block protruding from the side plate. The side plate is attached to an inner wall surface of the control box. The IGBT modules are installed on the heat dissipation block, and the pin terminals protruding from the IGBT modules are in electric or electronic connection with the circuit board.

Abstract: A semiconductor module has a first electrode terminal, a second electrode terminal, a third electrode terminal, a fourth electrode terminal, a fifth electrode terminal, and a sixth electrode terminal. The first electrode terminal and the second electrode terminal are arranged along a first direction. The third electrode terminal, the fourth electrode terminal, the fifth electrode terminal, and the sixth electrode terminal are arranged along a second direction perpendicular to the first direction. The first electrode terminal is arranged at a position where the first direction intersects with the second direction. The fourth electrode terminal, the fifth electrode terminal, and the sixth electrode terminal are AC output terminals or AC input terminals. The first electrode terminal is one of an anode terminal and a cathode terminal. At least one of the second electrode terminal and the third electrode terminal is the other of the anode terminal and the cathode terminal.

Abstract: The invention provides an electrical power module, including power transistors, and control components for controlling said power transistors, said module being cooled, in particular, by heat conduction. The module of the invention further includes a main substrate of the AMB/Si3N4 type carrying the power transistors, this main substrate itself constituting a heat-dissipating baseplate for dissipating the heat generated by the power transistors by being arranged in the module to be directly in contact with the carrier structure that provides cooling by conduction when said module is in place, and a ceramic substrate carrying the control components, this ceramic substrate itself being carried by the main substrate.

Abstract: A semiconductor module includes a first semiconductor element, a second semiconductor element, a first heat spreader electrically and thermally connected to the first semiconductor element, a second heat spreader electrically and thermally connected to the second semiconductor element, a DCB substrate including a first metal foil on a top surface of a ceramic insulating substrate and including a second metal foil on a bottom surface, the first metal foil being electrically and thermally joined to the first heat spreader and the second heat spreader, and a cooler thermally connected to the second metal foil of the DCB substrate. The first semiconductor element is disposed on an upstream side, and the second semiconductor element is disposed on a downstream side with respect to a flowing direction of a refrigerant of the cooler. An area of the second heat spreader is greater than an area of the first heat spreader.

Abstract: A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the first carrier side via one or more contact pads on the chip bottom side, disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, and disposing a second encapsulation material over a second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side.

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate; a plain trace on the substrate; an insulated trace on the substrate; an insulation layer on the insulated trace, the insulation layer at least partially covers the insulated trace; and a semiconductor device over the substrate, the semiconductor device has a plain bump attached on the plain trace and an inner bump attached on the insulated trace, and the plain bump is mounted adjacent to the insulation layer.

Abstract: In one embodiment, a semiconductor integrated circuit includes power supply strap wires extending in a first direction in a first layer, auxiliary power supply strap wires extending in the first direction in a second layer below the first layer, and intermediate power supply wires each electrically connecting one of the power supply strap wires to one of the auxiliary power supply strap wires in a third layer between the first and second layers. The circuit further includes power supply rails extending in a second direction in a fourth layer below the second layer, and upper power supply strap wires extending in the second direction in a fifth layer above the first layer. An interval between the intermediate power supply wires is larger than an interval between the power supply rails, and is smaller than an interval between the upper power supply strap wires.

Abstract: A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber.

Abstract: A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.

Abstract: Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads.

Abstract: A printed circuit board includes a first semiconductor package on a first surface layer of a printed wiring board and a second semiconductor package on a second surface layer where a bus signal is transmitted from the first to the second semiconductor package. A first bus wiring path from a signal terminal on an inner circumference side of the first semiconductor package via a via hole and the second surface layer to a signal terminal on an outer circumference side of the second semiconductor package and a second bus wiring path from a signal terminal on an outer circumference side of the first semiconductor package via the second surface layer and a via hole to a signal terminal on an inner circumference side of the second semiconductor package are provided, thus securing a return current path for a signal current and realizing a high density wiring while suppressing radiation noise.

Abstract: An apparatus relates generally to a microelectronic assembly. In such an apparatus, a contact arrangements are disposed on a first surface of a first substrate, including first contacts disposed as a first ring array; second contacts disposed interior to the first contacts as a second ring array; third contacts disposed interior to the second contacts as a third ring array; and fourth contacts disposed interior to the third contacts on the first surface as an innermost array. The first ring array, the second ring array, and the third ring array are concentric rings with the innermost array in a central region of the concentric rings. The first contacts and the fourth contacts are for interconnection with first microelectronic dies. The second contacts and the third contacts are for interconnection with second microelectronic dies.

Abstract: A surface mount package includes at least one semiconductor device and a POL packaging and interconnect system formed about the at least one semiconductor device that is configured enable mounting of the surface mount package to an external circuit. The POL system includes a dielectric layer overlying a first surface of the semiconductor device(s) and a metal interconnect structure extending through vias formed through the dielectric layer so as to be electrically coupled to connection pads on the semiconductor device(s). A metallization layer is formed over the metal interconnect structure that comprises a flat planar structure, and a double-sided ceramic substrate is positioned on a second surface of the semiconductor device(s), with the double-sided ceramic substrate being configured to electrically isolate a drain of the semiconductor device(s) from an external circuit when the surface mount package is joined thereto and to conduct heat away from the semiconductor device(s).

Abstract: Certain embodiments provide a semiconductor device including a semiconductor substrate, a side wall portion, a cap substrate, a plurality of external connection terminals, and a ground conductor. The semiconductor substrate includes a semiconductor element on its front surface. The side wall portion has conductivity and is provided on the front surface of the semiconductor substrate so as to surround the semiconductor element. The cap substrate is provided on the side wall portion so as to be electrically connected to the side wall portion. Each of the plurality of external connection terminals is provided on a back surface of the semiconductor substrate so as to be electrically connected to the semiconductor element. The ground conductor is provided to be electrically connected to the side wall portion on the entire back surface of the semiconductor substrate except an area in which the plurality of external connection terminals is provided.

Abstract: A power module includes a semiconductor device having at least one electrode surface on each side thereof, a first conductive member connected to the electrode surface provided on one side of the semiconductor device with solder, and a second conductive member connected to the electrode surface provided on the other side of the semiconductor device with solder, with at least one of the electrode surfaces provided on the one side of the semiconductor device being double comb-shaped.

Abstract: A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.

Abstract: A method of improving the appearance of aging skin that includes applying an effective amount of artichoke leaf extract and olive oil extract in combination to a target area of skin that exhibits a sign of aging skin, and compositions that include an effective amount of artichoke leaf extract and olive oil extract in combination. The composition is applied for a period of time sufficient to improve the appearance of the aging skin.

Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

Abstract: The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.