Abstract: According to one embodiment, a semiconductor device includes a first electrical conductor, a second electrical conductor, first and second semiconductors between the first and second electrical conductors, a first power terminal, a second power terminal, a signal terminal, and an insulator which covers the components. The insulator includes a flat bottom surface in which the first and second electrical conductors are exposed, a ceiling surface, a first end surface, and a second end surface. The power terminals and the signal terminal extend outwardly from the first and second end surfaces, and the ceiling surface, respectively. The first end surface, the ceiling surface, and the second end surface are formed with a parting line.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Abstract: A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die.

Abstract: A slew rate of a signal transmitted between a semiconductor device having a small load capacitance and a semiconductor device having a large load capacitance is improved. When a signal is transmitted to the semiconductor device (for example, a memory device) having the large load capacitance, pre-emphasis is performed, and when a signal is transmitted to the semiconductor device (for example, a memory controller) having the small load capacitance, pre-emphasis is not performed or is slightly performed. By this, when the signal is transmitted to the memory device, blunting in signal rising due to the load capacitance is suppressed, and when the signal is transmitted to the memory controller, ringing due to the reflection of the signal is suppressed, and the slew rate of the data transmission is improved.

Abstract: There is provided a semiconductor device including: plural bit cells each including the same circuit; plural electrodes supplied with power from outside, wherein each of the respective plural electrodes is mounted above the same circuit within the plural bit cells. Further, there is provided a semiconductor package including: the semiconductor device; a substrate mounted with the semiconductor device; an external input terminal formed on the substrate; an external output terminal formed on the substrate; an input wiring pattern connecting the semiconductor device mounted above the substrate and the external input terminal; an output wiring pattern connecting the semiconductor device mounted above the substrate and the external output terminal; and plural power supply lines, arranged without contact with each other on the same face of the substrate, and connecting the plural electrodes mounted to the semiconductor device to the corresponding electrode from the plural external power input electrodes.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

Abstract: In one embodiment of the present invention, a method of forming a semiconductor device includes forming a device region in a first region of a semiconductor substrate, and forming an opening in a second region of the semiconductor substrate. The method further includes placing a semiconductor die within the opening, and forming a first metallization level over the semiconductor die and the device region.

Abstract: A chip arrangement is provided, the chip arrangement including: a first chip carrier; a second chip carrier; a first chip electrically connected to the first chip carrier; a second chip disposed over the first chip carrier and electrically insulated from the first chip carrier; and a third chip electrically connected to the second chip carrier; wherein at least one of the first chip and the second chip is electrically connected to the third chip.

Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.

Abstract: A semiconductor unit includes an insulation layer, a conductive layer bonded to one side of the insulation layer, a semiconductor device mounted on the conductive layer, a cooler thermally coupled to the other side of the insulation layer, a first bus bar having a bonding surface bonded to the semiconductor device or the conductive layer and a non-bonding surface that is the part of the first bus bar other than the bonding surface, and a second bus bar having a bonding surface bonded to the semiconductor device or the conductive layer and a non-bonding surface that is the part of the second bus bar other than the bonding surface. The second bus bar has a greater ratio of the area of the bonding surface to the area of the non-bonding surface than the first bus bar. The second bus bar has a lower electric resistance than the first bus bar.

Abstract: The present invention relates to an electronic device for switching currents and a method for producing such a device that is reliable and durable. Such an electronic device comprises a power semiconductor that can be actuated for switching between at least two states; a substrate having thermomechanical properties compatible with the power semiconductor on which the power semiconductor is disposed on one side; a bus bar disposed on the other side of the substrate for conducting the current, wherein the substrate and the bus bar are coupled to each other such that a heat-conductive connection is provided so that heat can be dissipated from the power semiconductor to the bus bar.

Abstract: A semiconductor module is disclosed, including a substrate and at least one semiconductor component in bottom contact with the substrate. The semiconductor component including a main current branch sandwiched between the bottom and top of the semiconductor component. The side edges of a barrier layer zone coincide with the side edge portions of the semiconductor component between the top and the bottom. The space above the substrate and to the side of the semiconductor component is packed with an insulating compound at least up to the level of the top of the semiconductor component. Topping the semiconductor component and parallel thereto is a patterned or unpatterned metallization connected to a contact pad on the top of the semiconductor component.

Abstract: A semiconductor device that improves noise performance includes a circuit substrate, an enclosing case, and a metal part. A control circuit is mounted on the front surface of the circuit substrate. The enclosing case is a resin case in which semiconductor elements are installed. The metal part, included inside the enclosing case, includes a first mounting portion, a second mounting portion, and a bus bar. The first mounting portion mounts the circuit substrate on the enclosing case, and is connected to a ground pattern of the circuit substrate when mounting. The second mounting portion mounts an external instrument on the enclosing case, and is grounded when mounting. The bus bar connects the first mounting portion and second mounting portion.

Abstract: A semiconductor device package with an interposer, which serves as an intermediate or bridge circuit of various electrical pathways in the package to electrically connect any two or more electrical contacts, such as any two or more electrical contacts of a substrate and a chip. In particular, the interposer provides electrical pathways for simplifying a circuit layout of the substrate, reducing the number of layers of the substrate, thereby reducing package height and manufacturing cost. Furthermore, the tolerance of the circuit layout can be increased or maintained, while controlling signal interference between adjacent traces and accommodating high density circuit designs. Moreover, the package is suitable for a PoP process, where a profile of top solder balls on the substrate and a package body can be varied according to particular applications, so as to expose at least a portion of each of the top solder balls and electrically connect the package to another device through the exposed, top solder balls.

Abstract: A semiconductor device, includes a substrate with a first surface, a semiconductor chip disposed over the first surface of the substrate, the semiconductor chip including a first region and a second region, and an encapsulant resin formed over the first surface of the substrate and encapsulating the semiconductor chip. The encapsulant resin has a thickness that is less at the first region of the semiconductor chip than that at the second region.

Abstract: A packaging substrate and a semiconductor package each include: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer.

Abstract: A semiconductor package includes a plurality of electrical connectors, a semiconductor die having core logic, at least two pairs of core logic input-power and output-power pads, and a plurality of input/output signal pads that carry signals to and from the core logic. Each pad of the semiconductor die has an electrical connector of the plurality of electrical connectors extending therefrom. The semiconductor package also includes a package substrate having at least two pairs of input-power and output-power contact pads, a plurality of input/output signal contact pads, a first metal redistribution layer, and a second metal redistribution layer. The first metal redistribution layer provides a first electrical potential to each of the input-power contact pads, and the second metal redistribution layer provides a second electrical potential to each of the output-power contact pads. Each contact pad has an electrical connector of the plurality of electrical connectors extending therefrom.

Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.

Abstract: Some implementations provide an integrated device that includes a first substrate, a first die coupled to the first substrate, a second die coupled to the first die, and a second substrate coupled to the second die. The second substrate is configured to provide an electrical path for a signal to the second die. The integrated device further includes a molding surrounding the first die and the second die, and several through mold vias (TMVs) coupled to the second substrate. The TMVs are configured to provide an electrical path for the signal to the second die through the second substrate. In some implementations, the second substrate includes a signal distribution structure configured to provide the electrical path for the signal to the second die. In some implementations, the first substrate and the second substrate are part of a signal distribution network that provides signal to the second die.

Abstract: A preamplifier integrated circuit (IC) for a magnetic storage device comprises a plurality of channels, each including at least one preamplifier and a plurality of groups. Each of the groups includes at least one of the channels. A passivation layer is arranged adjacent to at least one interconnecting layer. A plurality of first external connections external to the IC are arranged in openings in the passivation layer, are in contact with at least one of the interconnecting layers, that distribute a first potential to the at least one preamplifier of the plurality of channels, and communicate with the plurality of groups. Each of the plurality of first external connections distributes the first potential to first respective ones of the plurality of groups independently of others of the plurality of groups.

Abstract: A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die.

Abstract: Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.

Abstract: A Peltier element is provided so that an electrically conductive plate forming a heat absorbing portion is in close proximity to an insulating layer and an electrically conductive plate forming a heat radiating portion is provided in close proximity to an insulating layer. The Peltier element has one end connected to a branch line branched from a power line, and has the other end electrically connected to an electrode plate. Further, the Peltier element receives from the branch line a portion of electric power supplied to a power transistor, and outputs it to the electrode plate. In other words, the Peltier element uses the portion of the electric power supplied to the power transistor, to absorb heat generated by the power transistor and radiate it toward a heat radiating plate.

Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Abstract: A pad for a line which supplies an electric power potential is disposed on a semiconductor integrated circuit and a pad which is not electrically connected to any other electric circuit is disposed on a semiconductor integrated circuit board, and the two pads are connected through a bonding wire. An LC resonant circuit is configured with ease using a floating capacitance C of the pad which is in an electrically open state and which is disposed in a vacant region and an inductance value L of the bonding wire which is disposed in a three-dimensional manner. High-frequency noise is filtered and high-density implementation is realized.

Abstract: A semiconductor die that includes a plurality of non-metallic slots that extend through a current routing line is disclosed. The semiconductor die comprises a semiconductor circuit that includes a plurality of semiconductor components and a current trace line that is coupled to a first semiconductor component. Further, the semiconductor die comprises a current routing line that is coupled with the current trace line. The current routing line includes a plurality of non-metallic slots that extend through the current routing line.

Abstract: A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer.

Abstract: A semiconductor chip includes a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.

Abstract: A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged.

Abstract: A chip packaging structure includes a flexible plate, a chip, and a plurality of leads. The chip is disposed on the flexible plate. A first boundary and a second boundary are defined on the flexible plate. The first boundary is located between the chip and the second boundary. A first area is formed between the first boundary and the chip. A second area is formed between the first boundary and the second boundary. The chip includes a plurality of signal conducting points and a plurality of non-signal conducting points. The plurality of leads are disposed on the flexible plate and include a plurality of signal leads and a plurality of non-signal leads. The width of the non-signal lead is smaller than the width of the signal lead extending out of the second boundary.

Abstract: An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.

Abstract: An organic light emitting display apparatus and method of manufacturing the organic light emitting display apparatus including a lower substrate having power lines in a non-display region that is outside a display region whereon an image is realized; and a functional layer formed between the power lines and an encapsulation substrate.

Abstract: An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different function and include at least one dielectric layer disposed on the substrate and/or on the unit cells and at least two contact surfaces which are disposed parallel to the plane above the contact points and/or the substrate. The contact points with the same function are connected electrically to at least one common contact surface for at least a part of the contact points of the same function via at least one through-contacting through the dielectric layer and able to be contacted in common from outside via the corresponding contact surfaces.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages.

Abstract: Embodiments of the present disclosure provide an apparatus comprising a substrate layer, a metal ring structure disposed on the substrate layer, the metal ring structure having an opening defined therein, and a solder mask layer coupled to (i) the metal ring structure and (ii) the substrate layer through the opening defined in the metal ring structure, the solder mask layer having a solder mask opening defined therein, wherein an edge of solder mask material defining the solder mask opening overlaps a portion of the opening defined in the metal ring structure. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device includes a metal substrate including a metal base plate, an insulating sheet located on the metal base plate, and a wiring pattern located on the insulating sheet, and a semiconductor element located on the metal substrate. The semiconductor element is sealed with a molding resin. The molding resin extends to side surfaces of the metal substrate. On the side surfaces of the metal substrate, the insulating sheet and the wiring pattern are not exposed from the molding resin, whereas the metal base plate includes a projecting portion exposed from the molding resin.

Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

Abstract: A power converter includes a plurality of semiconductor modules that have main body sections, each of the main body sections has a semiconductor element therein, and power terminals projected from the main body sections, and a plurality of bus bars that connect the power terminals of the semiconductor modules. At least one of the plurality of the bus bars are connecting bus bars which have a plurality of terminal connecting sections that connect the power terminals of the plurality of different semiconductor modules, and connecting sections that connect the terminal connecting sections. The entirety of each of the connecting bus bars is formed integrally. The terminal connecting sections and the connecting section of every connecting bus bar are provided alternately in the connecting bus bar, and disposed in substantially the same position in a projecting direction of the power terminals.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

Abstract: A grounding system for a semiconductor module of a variable speed drive includes a first conductive layer, a second conductive layer; a substrate disposed between the first conductive layer and the second conductive layer; and a base attached to the second conductive layer, the base being connected to earth ground via a grounding harness. The first conductive layer is in electrical contact with the semiconductor module and the substrate, and electrically insulated from the second conductive layer by the substrate. The second conductive layer is in electrical contact with the substrate and disposed between the substrate and the base in electrical communication with an earth ground. The first conductive layer, the substrate and the second conductive layer form a capacitance path between the semiconductor module and the base as well as electrical conductors and the base for reduction circulating currents within the semiconductor module.

Abstract: A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device. In this manner, the design benefits from the power capabilities and improved grounding of a lead-frame conductor, whilst also achieving the routeing capabilities and small scale advantages provided by a multi-layer printed circuit substrate.

Abstract: According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Abstract: An interposer chip may include a substrate, a plurality of upper terminals, a plurality of lower terminals, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals and a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.

Abstract: In-package fly-by signaling can be provided in a multi-chip microelectronic package having address lines on a package substrate configured to carry address information to a first connection region on the substrate having a first delay from terminals of the package, and the address lines being configured to carry the address information beyond the first connection region to at least to a second connection region having a second delay from the terminals that is greater than the first delay. Address inputs of a first microelectronic element, e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region, and address inputs of a second microelectronic element can be coupled with each of the address lines at the second connection region.

Abstract: A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through silicon via (TSV) contacts.

Abstract: An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The integrated circuit having circuit blocks, that operate at different operating voltages and voltage regulator modules die bonded to the second bond pads of the integrated circuit. The voltage regulator modules converting a power supply voltage to the operating voltage of a respective circuit block and supply the respective operating voltage to the circuit block via the second bond pads.

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

Abstract: A light emitting die package is provided which includes a metal substrate having a first surface and a first conductive lead on the first surface. The first conductive lead is insulated from the substrate by an insulating film. The first conductive lead forms a mounting pad for mounting a light emitting device. The package includes a metal lead electrically connected to the first conductive lead and extending away from the first surface.

Abstract: A storage element is provided in a semiconductor chip, and an inductor and a driver circuit are provided in another semiconductor chip. An external terminal is a contact type terminal, and at least some external terminals are a power supply terminal and a ground terminal. A sealing resin layer is formed over a first surface of an interconnect substrate and seals the semiconductor chips but does not cover the external terminal. The inductor is formed at a surface of the semiconductor chip not facing the interconnect substrate.