Fanned/radial Leads Patents (Class 257/695)
  • Patent number: 9918667
    Abstract: A universal electrochemical micro-sensor can be used either as a biosensor or an environmental sensor. Because of its small size and flexibility, the micro-sensor is suitable for continuous use to monitor fluids within a live subject, or as an environmental monitor. The micro-sensor can be formed on a reusable glass carrier substrate. A flexible polymer backing, together with a set of electrodes, forms a reservoir that contains an electrolytic fluid chemical reagent. During fabrication, the glass carrier substrate protects the fluid chemical reagent from degradation. A conductive micromesh further contains the reagent while allowing partial exposure to the ambient biological or atmospheric environment. The micromesh density can be altered to accommodate fluid reagents having different viscosities. Flexibility is achieved by attaching a thick polymer tape and peeling away the micro-sensor from the glass carrier substrate.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 20, 2018
    Assignee: STMICROELECTRONICS PTE. LTD.
    Inventors: Olivier Le Neel, Suman Cherian, Calvin Leung
  • Patent number: 9129942
    Abstract: A method for shaping a laminate substrate includes characterizing the laminate substrate for warpage characteristics over a range of temperatures. The laminate substrate is placed into a shaping fixture with any necessary correction to obtain a flat laminate substrate chip site area at a chip join temperature. The laminate substrate is shaped at a temperature greater than or equal to a maximum laminate substrate fabrication temperature. The shape of the laminate substrate is retained when it is removed from the shaping fixture.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: September 8, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Edmund D. Blackshear
  • Patent number: 8941241
    Abstract: A semiconductor device includes at least 4 conductive line groups arranged in parallel over one memory cell block and each configured to include conductive lines. First contact pads may be coupled to the respective ends of the conductive lines of two of the 4 conductive line groups in a first direction, and second contact pads may be coupled to the respective ends of the conductive lines of the remaining 2 of the 4 conductive line groups in a second direction opposite to the first direction.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: January 27, 2015
    Assignee: SK Hynix Inc.
    Inventor: Dae Sung Eom
  • Patent number: 8836106
    Abstract: In a QFN that includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads arranged around the semiconductor chip, a plurality of wires that electrically connect the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively, and a sealing member sealing the semiconductor chip and the plurality of wires, first and second step portions are formed at shifted positions on the left and right sides of each of the leads to make the positions of the first and second step portions shifted between the adjacent leads. As a result, the gap between the leads is narrowed, thereby achieving the miniaturization or the increase in the number of pins of the QFN.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: September 16, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Masato Numazaki
  • Patent number: 8829685
    Abstract: Provided are: a circuit device demonstrating an improved connection reliability while being mounted; and a method for manufacturing the same. The circuit device of the present invention includes: an island; leads arranged around the island, each lead having a lower surface and a side surface exposed to the outside; and a semiconductor element mounted on the island and electrically connected to the leads through thin metal wires. Furthermore, the exposed end portion of the lead is formed to spread toward the outside. By forming the lead in this manner, the area where the lead comes into contact with a brazing filler material is increased, thus improving the connection strength therebetween.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Tetsuya Fukushima, Takashi Kitazawa
  • Patent number: 8698218
    Abstract: A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer. The free, barrier and pinned layers together form a layer stack that has a read current path that extends through the layer stack and that is not aligned with the write current path in the free layer.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: April 15, 2014
    Assignee: Seagate Technology LLC
    Inventor: Mark William Covington
  • Patent number: 8659143
    Abstract: A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. The microelectronic element can include stacked electrically interconnected semiconductor chips. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location. The central region may have a width not more than 3.5 times a minimum pitch between adjacent terminal columns. The axial plane can intersect the central region.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: February 25, 2014
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8659140
    Abstract: A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: February 25, 2014
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8659142
    Abstract: A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: February 25, 2014
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8659141
    Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: February 25, 2014
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8659139
    Abstract: A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: February 25, 2014
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8653646
    Abstract: A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: February 18, 2014
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8648458
    Abstract: An integrated circuit leadframe device supports various chip arrangements. As consistent with various embodiments, a leadframe includes a plurality of banks of conductive integrated circuit chip connectors. Each bank has a plurality of conductive strips respectively having an end portion, the end portions of each of the strips in the bank being substantially parallel to one another and arranged at an oblique angle to end portions of strips in at least one of the other banks. Each of the end portions has a tip extending to an interior portion of the leadframe device and separated from the other tips by a gap.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: February 11, 2014
    Assignee: NXP B.V.
    Inventor: Barry Lin
  • Patent number: 8633407
    Abstract: A semiconductor device includes a substrate, a first pad that is formed above the substrate, a second pad that is formed above the substrate, an external terminal that is connected with the second pad, and a circuit that judges whether or not the first pad is connected with the external terminal, wherein a distance between the first pad and a side of the substrate opposed to the external terminal is different from a distance between the second pad and the side.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: January 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyoshi Fukuda
  • Patent number: 8502377
    Abstract: A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 ?m and 40 ?m and a length substantially between 70 ?m and 130 ?m, for example.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: August 6, 2013
    Assignee: Mediatek Inc.
    Inventors: Tzu-Hung Lin, Ching-Liou Huang, Thomas Matthew Gregorich
  • Patent number: 8450841
    Abstract: A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: May 28, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Li Ting Celina Ong, Yin Kheng Au, Zi-Song Poh
  • Patent number: 8395246
    Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: March 12, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Cheemen Yu, Vani Verma, Hem Takiar
  • Patent number: 8344269
    Abstract: A semiconductor device includes a substrate, a first pad, a second pad, and a third pad that are placed along one side of a perimeter of the substrate, a circuit that is formed above the substrate, and that is coupled to the first pad, a first external terminal that is coupled to the second pad, and a second external terminal that is coupled to the third pad, wherein the circuit generates a signal indicative of a connection configuration between the first pad and the first external terminal, wherein the third pad is placed adjacent to one of the first pad and the second pad, wherein, in a direction parallel to the one side of the perimeter of the substrate, the first pad, the second pad and the third pad have a first width, a second width and a third width, respectively, and wherein each of the first width of the first pad and the second width of the second pad is smaller than the third width of the third pad.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: January 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyoshi Fukuda
  • Patent number: 8304886
    Abstract: Provided are a semiconductor device and a method of forming a semiconductor device in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using a double patterning.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: November 6, 2012
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Dong-hyun Kim
  • Patent number: 8283663
    Abstract: A multichip device, which achieves a normal operation and a testing operation without the needs for terminals dedicated for the testing and/or an interposer substrate, is provided. The peripheral chip also includes a switching unit for providing a switching between a normal mode that provides a first connection condition and a testing mode that provides a second coupling connection condition. The switching unit, in turn, provides connections of at least some of a plurality of outside terminals to the functional circuits, respectively, in the normal mode, and connects at least some of a plurality of outside terminals to the inside terminals in the testing mode. Thus, the normal operation and the testing operation can be carried out without the needs for the external terminals and/or the interposer substrate, which are employed for the purpose of only the testing.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: October 9, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuyuki Kobayashi
  • Patent number: 8233127
    Abstract: An object of the present invention is to reduce a lateral width of an FPC also with evenly aligned and arranged plurality of ICs. The liquid crystal display device according to the present invention includes a glass substrate, a plurality of ICs of COG (Chip On Glass) configuration aligned on a glass substrate along a side thereof, and an FPC (Flexible Printed Circuit) that is arranged to extend along the side of the glass substrate and that is connected to the plurality of ICs. Specified ICs from among the plurality of ICs are arranged in that extending directions of their longer sides are inclined with respect to an extending direction of the side of the glass substrate such that the longer sides face towards a central side of the FPC.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: July 31, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tomohiro Tashiro
  • Patent number: 8188582
    Abstract: Provided are a lead frame, semiconductor device, and methods of manufacturing the same. The lead frame may include a die pad having at least three pair of sides parallel with each other, and a plurality of inner leads spaced apart from a circumference of the die pad, arranged in a radial shape with respect to a center of the die pad, and having the ends form inner lead connection surfaces parallel with at least one pair of sides of the die pad. In addition, there may be provided a semiconductor device having the lead frame. Accordingly, a semiconductor chip may be positioned on a die pad. The plurality of inner leads may be electrically connected to the semiconductor chip through wires. The semiconductor device may further include a molding resin for surrounding top and bottom surfaces of the lead frame and filling in an interior thereof.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: May 29, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jang-Mee Seo
  • Patent number: 8159063
    Abstract: A substrate of a micro-BGA package is revealed, primarily comprising a substrate core, a first trace, and a second trace where the substrate core has a slot formed between a first board part and a second board part. The first trace is disposed on the first board part and has a suspended inner lead extended into the slot where the inner lead has an assumed broken point. The second trace is disposed on the second board part and is integrally connected to the inner lead at the assumed broken point. More particularly, a non-circular through hole is formed at the assumed broken point and has two symmetric V-notches away from each other and facing toward two opposing external sides of the inner lead so that the inner lead at two opposing external sides does not have the conventional V-notches cutting into the inner lead from outside. Moreover, the inner lead will not unexpectedly be broken and the inner lead can easily and accurately be broken at the assumed broken point during thermal compression processes.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: April 17, 2012
    Assignee: Powertech Technology Inc.
    Inventor: Ching-Wei Hung
  • Patent number: 8110913
    Abstract: An integrated circuit package system includes: fabricating a lead frame including: providing inner leads having an inner lead pitch of progressive length, forming a lead shoulder, on the inner leads, having a shoulder height of a progressive height, and forming outer leads coupled to the lead shoulder and the inner leads; mounting an integrated circuit die on the lead frame; and molding a package body on the lead frame and the integrated circuit die.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: February 7, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Linda Pei Ee Chua, Zheng Zheng, Lee Sun Lim
  • Patent number: 8106418
    Abstract: A light emitting device includes a first lead and a second lead. The first lead has a top surface which a light emitting element is mounted thereon and a bottom surface opposed to the top surface. The second lead has a lead peripheral region where a wire connected to an electrode of the light emitting element is bonded therewith. The first lead includes a lead middle region where the semiconductor light emitting element is mounted thereon to thermally conduct therewith. A bottom surface of the lead middle region is exposed from a package. The second lead has an outer lead region that is projected outwardly from the both side surfaces of the package. The bottom surface of the first lead middle region is substantially coplanar with a bottom surface of the outer lead region.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: January 31, 2012
    Assignee: Nichia Corporation
    Inventor: Yoshitaka Bando
  • Patent number: 8067831
    Abstract: An integrated circuit package system is provided including forming a first substrate, mounting a first integrated circuit to the first substrate, and forming first planar interconnects in contact with the first integrated circuit and electrically connecting the first integrated circuit to the first substrate.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Hyeog Chan Kwon, Tae Sung Jeong, Jae Han Chung, Taeg Ki Lim, Jong Wook Ju
  • Patent number: 7825445
    Abstract: A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer. The free, barrier and pinned layers together form a layer stack that has a read current path that extends through the layer stack and that is not aligned with the write current path in the free layer.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: November 2, 2010
    Assignee: Seagate Technology LLC
    Inventor: Mark William Covington
  • Patent number: 7781873
    Abstract: A thin, small outline IC leadframe plastic package to be used to assemble high performance, high speed semiconductor memory IC devices such as dynamic random access memories (DRAM) having a high data transfer rate in the range of 1 GigaHertz. The package leadframe is electrically interconnected to the IC device input-output pads by either electrically conductive (e.g. solder) bumps that are flip-chip bonded to the IC device or by of an interposer. The interposer contains integral curled micro-spring contacts at opposite ends of conductive fan out traces. The interposer is attached to the leadframe bonding pads by way of tape automated bonding, soldering, or adhesive bonding. The leadframe that is interconnected to the IC device by the aforementioned flip-chip bumps or the interposer is encapsulated and trimmed to form either gull-wing style perimeter leads as a standard thin small outline package (TSOP) or wrap around leads as a micro-leadframe (MLF) package.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: August 24, 2010
    Assignee: Kingston Technology Corporation
    Inventors: Wei H. Koh, Fred Kong, David Chen
  • Patent number: 7763812
    Abstract: A semiconductor device according to the present invention includes first through fourth internal terminals placed along the perimeter of a substrate, a circuit coupled to the first internal terminal, a first external terminal coupled to the second internal terminal, a second external terminal coupled to the third internal terminal, and a third external terminal coupled to the fourth internal terminal. The circuit outputs a signal indicative of a connection state the first internal terminal and the first external terminal. A distance between centers of the first and second internal terminals is L1 in a direction parallel to one side of the substrate beside which the first external terminal is placed. A distance between centers of the third and fourth internal terminals is L2 in a direction parallel to one side of the substrate beside which the second and third external terminals are placed. The distance L1 is set smaller than the distance L2.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hiroyoshi Fukuda
  • Publication number: 20100140788
    Abstract: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 10, 2010
    Applicant: STMICROELECTRONICS ASIA PACIFIC PTE, LTD.
    Inventor: Yonggang Jin
  • Patent number: 7618845
    Abstract: A QFN integrated circuit is mounted on a leadframe having multiple lead lands and resin material encapsulates the integrated circuit leaving the lead lands exposed. Subsequently a sawing operation divides the lead lands into multiple leads, and the leadframe and resin material are partitioned to form packages. The pitch of the resultant leads is not limited by the pitch of the lead lands of the leadframe, so the leadframe can be of the relatively cheap generic leadframe variety, in which the pitch of the lead lands is higher than the desired pitch of the leads of the completed package. The sawing operation may further include reshaping the diepad area of the leadframe to produce heat sink fins, for improved heat dissipation. The proposed process is suitable both to produce packages including only a single integrated circuit, and also to produce multi-chip modules.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: November 17, 2009
    Assignee: Infineon Technologies AG
    Inventor: Chee Chian Lim
  • Patent number: 7579680
    Abstract: A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: August 25, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: David Chong, Hun Kwang Lee
  • Patent number: 7554136
    Abstract: A micro device that is manufactured by semiconductor process and is electrically connected to outside for its operation. The micro device includes a circuit board, an electrode pad being provided on the circuit board, a lead substrate being provided substantially parallel to the circuit board, and a lead of conductive member being electrically connected to the electrode pad by being bent in a direction away from a surface of the lead substrate, one end of the lead being adhered to the lead substrate and the other end being a free end.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: June 30, 2009
    Assignee: Advantest Corporation
    Inventors: Fumikazu Takayanagi, Yoshiaki Moro, Hirokazu Sanpei
  • Patent number: 7511368
    Abstract: A surface mount electronic chip (10) is mounted on a holder (70) and electrically connected to holder terminals (74,76, 80) by the use of a carrier device (30). The carrier device has clips (36) mounted on walls of the carrier frame. The chip is merely pressed into a cavity (48) between inner tabs (44) of the chips. The carrier with the chip in place is merely pressed into a cradle (78) formed in the holder by the holder terminals, so outer tabs (46) of the clips press against the holder terminals.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: March 31, 2009
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventor: Peter Jordan
  • Patent number: 7504670
    Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 17, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Satoshi Shiraishi, Yoichi Kazama
  • Patent number: 7459770
    Abstract: A lead frame structure is provided, which includes a die pad having a first mounting portion and a second mounting portion separated from the first mounting portion by a gap. The first and second mounting portions are formed with corresponding blocking surfaces bordering the gap, so as to allow a flow rate of an encapsulating resin flowing through the gap during a molding process to be reduced by the blocking surfaces, such that different portions of the encapsulating resin respectively flowing above, in and below the die pad can have substantially the same flow rate, thereby preventing bonding wires from being deformed to cause short circuit and avoiding formation of voids. A semiconductor package with the lead frame structure is also provided.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: December 2, 2008
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wen-Shan Tsai, Chien-Feng Wei, Hung-Wen Liu, Ming Cheng Lin, Lien-Chen Chiang
  • Patent number: 7459780
    Abstract: This invention discloses a fan-out wire structure for use in a display panel of a display device. The fan-out wire structure comprises a first metal layer, a first insulation layer, and a second metal layer. The first insulation layer is formed on the first metal layer and the second metal layer is formed on the first insulation layer, and the first metal layer and the second metal layer are electrically connected by a conductive material, so as to modulate the resistance of the fan-out wire structure by modulating the length of the second metal layer and the conductive material.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: December 2, 2008
    Assignee: AU Optronics Corporation
    Inventor: Wan-Jung Chen
  • Patent number: 7420271
    Abstract: A heat conductivity and brightness enhancing structure for light-emitting diode, including a bracket having a cathode leg support. A bowl structure is formed on upper end of the cathode leg support for resting a light-emitting chip therein. At least one depression is formed on a bottommost section of the bowl for receiving an adhesive therein. The depression has a diameter or area smaller than the bottom face of the chip. The adhesive is filled into the depression for adhering one or more chip. The other portions of the bottom face of the bowl, which contact with the chip is free from the adhesive and can achieve good heat conduction and radiation effect. At least one column hole is formed in the cathode leg support from a hollow section of the bottom of the bracket to the depression of the bowl. During manufacturing procedure, the adhesive can be heated, molten and exhausted from the column hole. The column hole serves as a passage for air convection, whereby the heat generated by the chip can be dissipated.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: September 2, 2008
    Inventor: Hsin Fen Hsu
  • Patent number: 7378727
    Abstract: A memory device includes a semiconductor substrate having a surface, a plurality of first and second conductive lines, a plurality of memory cells, and a plurality of landing pads. Each of the first conductive lines has a line width wb and two neighboring ones of the first conductive lines having a distance bs from each other. Each of the second conductive lines has a line width wl and two neighboring ones of the second conductive lines having a distance ws from each other. Each memory cell is accessible by addressing corresponding ones of said first and second conductive lines. Each of the landing pads are made of a conductive material and are connected with a corresponding one of said second conductive lines.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: May 27, 2008
    Inventors: Dirk Caspary, Stefano Parascandola
  • Patent number: 7348494
    Abstract: Inner layer traces on a multilayer printed wiring board are exposed to enable direct interconnection with another device such as a printed wiring board. The traces may be exposed by removing at least some of the dielectric substrate material around the traces, or by extending the traces beyond the other layers of the printed wiring board. Corresponding conductors associated with the other device are placed in direct physical contact with the exposed inner layer traces, and may be aligned and secured with guide plates, alignment pins and spring members. Such direct connection mitigates the need for vias, and has more favorable electrical characteristics for high frequency signal transmission.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: March 25, 2008
    Assignee: Nortel Networks Limited
    Inventors: Martin R. Handforth, Herman Kwong, Richard R. Goulette
  • Patent number: 7329946
    Abstract: A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones of the first conductive elements. A lower surface of the package may include third conductive elements, the third conductive elements to receive a second plurality of the input/output signals from respective other ones of the first conductive elements.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: February 12, 2008
    Assignee: Intel Corporation
    Inventors: Jianqi He, Yuan-Liang Li, Michael Walk
  • Patent number: 7323776
    Abstract: The elevated heat dissipating device of the present invention comprises a thermal substrate connecting onto a heat source and at least one heat conductive pipe connecting to the thermal substrate. The heat conductive pipe further comprises a connecting part connected to a top portion of the thermal substrate, and a bending part which is bended and extended upward away from the thermal substrate. A plurality of sets of heat fins connecting to end portions of the bending part of the heat conductive pipe are supported and elevated by the heat conductive pipe so that an air space is formed between the thermal substrate and the sets of heat fins. A fan locating on a top part of the heat fins, wherein a plurality of air passages are formed in between those heat fins so that cool air ventilates from the fan through the air passages of the heat fins to the thermal substrate.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: January 29, 2008
    Assignee: Thermaltake Technology Co., Ltd.
    Inventor: Pei-His Lin
  • Patent number: 7239008
    Abstract: A semiconductor apparatus includes a semiconductor pellet having electrodes thereon; a plurality of lead terminals, which electrically connect the electrodes of the semiconductor pellet to terminals formed on a substrate; and a molding member, which is filled around the semiconductor pellet and upper parts of the lead terminals. The plurality of lead terminals are shaped to be elongated strips and are arranged to extend out of the molding member toward the substrate.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: July 3, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Nakamura
  • Patent number: 7115977
    Abstract: A multi-chip package type semiconductor device includes an insulating substrate having first and second conductive patterns thereon, a first semiconductor chip on the insulating substrate and having a first terminal pad and a relay pad isolated from the first terminal pad. The device further includes a second semiconductor chip on the first semiconductor chip having a second terminal pad. The first semiconductor chip is connected to the first pattern by a first bonding wire. The second semiconductor chip is connected to the second pattern by a second bonding wire, which connects the second pattern to the relay pad, and a third bonding wire, which connects the relay pad to the second terminal pad. The lengths of the first, second and third bonding wire are approximately the same.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: October 3, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Mitsuru Komiyama, Shinsuke Suzuki
  • Patent number: 7109573
    Abstract: An IC package dissipates thermal energy using thermally and electrically conductive projections. The IC package includes a substrate material with a die pad area, which is suitable to support an integrated circuit. A plurality of solder ball pads is disposed on a first surface of the substrate material and a plurality of conductive projections radiate outwardly from the die pad area and extend to cover a corresponding selected solder ball pad to facilitate the dissemination of thermal energy from the die pad area to the substrate and/or printed wiring board.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: September 19, 2006
    Assignee: Nokia Corporation
    Inventor: Janne T Nurminen
  • Patent number: 7102211
    Abstract: The related arts have difficulty in efficiently dissipating the heat generated by a resin-molded semiconductor element, and thus have the problem of thermal stress causing damage to the semiconductor element. To solve the problem, a semiconductor device of the preferred embodiments includes common leads coupled to an island, and a part of the common leads projects out from a resin seal body. The projecting common leads have a coupling portion. When mounting the semiconductor device, the common leads are bridged with brazing material. Thus, the heat generated by an integrated circuit chip mounted on the island is dissipated through the common leads to the outside of the resin seal body. In the preferred embodiments of the invention, a further improvement in heat dissipation characteristics can be accomplished by increasing the surface areas of the common leads.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: September 5, 2006
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Isao Ochiai, Masato Take
  • Patent number: 7012325
    Abstract: An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30–50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: March 14, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Ho Ahn, Se-Yong Oh
  • Patent number: 6992372
    Abstract: The present invention provides a flat film carrier tape for mounting electronic devices thereon which tape can enhance reliability of a semiconductor chip mounting line. The film carrier tape includes a continuous insulating layer, a wiring pattern formed of a conductor layer provided on a surface of the insulating layer, a row of sprocket holes provided along respective longitudinal edges of the insulating layer, which said row of sprocket holes are at the outer sides of the wiring pattern, and a metallic layer formed around said row of sprocket holes, wherein the metallic layer is provided in a discontinuous manner in the longitudinal direction of the insulating layer by provision of slits on the insulating layer at intervals of three to eight said sprocket holes.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: January 31, 2006
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventor: Shinichi Sumi
  • Patent number: RE43818
    Abstract: A QFN integrated circuit is mounted on a leadframe having multiple lead lands and resin material encapsulates the integrated circuit leaving the lead lands exposed. Subsequently a sawing operation divides the lead lands into multiple leads, and the leadframe and resin material are partitioned to form packages. The pitch of the resultant leads is not limited by the pitch of the lead lands of the leadframe, so the leadframe can be of the relatively cheap generic leadframe variety, in which the pitch of the lead lands is higher than the desired pitch of the leads of the completed package. The sawing operation may further include reshaping the diepad area of the leadframe to produce heat sink fins, for improved heat dissipation. The proposed process is suitable both to produce packages including only a single integrated circuit, and also to produce multi-chip modules.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: November 20, 2012
    Assignee: Infineon Technologies AG
    Inventor: Chee Chian Lim
  • Patent number: RE44699
    Abstract: A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: January 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-Cheol Lee