Abstract: A printed circuit board is connected to a single-layer wiring tape so as to surround an integrated circuit element which is connected to the single-layer wiring tape. Wiring patterns of the wiring tape are formed from either a power electrode or a ground electrode on the integrated circuit element to a planar metal pattern on the printed circuit board, from the planar metal pattern on the printed circuit board to either an external power terminal or an external ground terminal on the wiring tape, and from a signal electrode on the integrated circuit element to an external signal terminal on the wiring tape.

Abstract: A semiconductor device packaged in a plastic package, the semiconductor device being provided with a semiconductor device chip further provided with plural leads arranged along the top surface of the semiconductor device chip and a plastic mold covering the semiconductor device chip, wherein the plastic mold is limited to the top surface of the semiconductor device chip and the shape of the leads is J-shape or U-shape, whereby the connection between the leads and a printed board is made strong, resulting enhanced reliability of the semiconductor device from the electrical and mechanical viewpoints.

Abstract: A semiconductor device package is formed with a lead frame including a plurality of lead members positioned in an array, and a semiconductor die is secured to the lead frame. At least one pair of bus bars is connected to the lead frame and positioned over the semiconductor die, with the bus bars including a plurality of inner-digitized bond fingers. The inner-digitized bond fingers are formed from a series of alternating projections and recesses on each bus bar. A plurality of bond wires electrically couples the lead members to the semiconductor die. Other bond wires electrically couples the inner-digitized bond fingers of the bus bars to the semiconductor die. The bond wires attached to the inner-digitized bond fingers have a substantially uniform loop height and length, providing for easier manufacture and inspection of the semiconductor device package.

Abstract: A semiconductor package includes a base plate, a semiconductor die having top and bottom surfaces, the bottom surface being mounted to the base plate, and a conductor tab having first and second ends, the first end being adapted to communicate with and couple to external circuitry, the second end including a relatively wide foot having a plurality of finger portions separated by gaps, the finger portions being mounted to an covering a substantial portion of the top surface of the semiconductor die.

Abstract: A lead frame comprises an island supported by island supports at its four corners and leads extending from its frame section to the island. The leads are composed of inner leads and outer leads which are connected to each other with dam bars. Plating layers are formed on the surfaces of the tip sections of the inner leads, and lead-fixing tape is bonded to the distal portions of the inner leads with an adhesive which acquires elastic properties when set. The lead-fixing tape is bonded with its inner side located 0.1 mm-2 mm inward from the tips of the inner leads.

Abstract: A semiconductor die assembly of this invention includes a lead system in which the leads are arranged in a radial pattern. That is, in a group of leads associated with a single side of a semiconductor die, leads which are furthest from the middle are most angled from the perpendicular. The semiconductor die includes an outer row of bond pads which are located proximate to the edge of the semiconductor die and an inner row of bond pads, parallel to the first row and located toward the interior of the semiconductor die surface. In one embodiment, one of the rows of bond pads is regularly spaced, while the other row of bond pads is variably spaced.

Abstract: Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.

Abstract: A lead frame having a plurality of metallic conductors with each conductor having a coined or stamped region near its proximal end but spaced therefrom to provide pressure points to assure substantial even joining of the conductor to semiconductor chip via an insulative adhesive medium. The lead frame, when mounted on the active face of a semiconductor chip, has wires connecting terminals on the major active surface of the semiconductor chip to the bands on selected lead frame conductors. The lead frame on the semiconductor chip and the wires which connect the semiconductor chip terminals to the bands of selected lead frame conductors are then encapsulated with a suitable insulative material to form a semiconductor module or package.

Abstract: Two or more bonding option pads are aligned in a predetermined direction on a semiconductor chip. Leads on higher and lower potential sides are provided on both sides of the bonding option pads such that the leads are extended in the direction passing across the predetermined direction. At least one of the bonding option pads is connected to at least one of the leads by means of a bonding wire.

Abstract: An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.

Abstract: A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip converts a receive signal to a baseband signal using a tuning frequency signal generated from a tank circuit. The design of a package for the tuner chip maximally spaces the pins associated with high frequency signals by placing them on opposite sides of the chip (in the case of two high frequency signal sources) or (in the case of three high frequency signal sources) in a triangle formation with widely spaced vertices wherein at least two of the pins are adjacent to corners of the package. For two or more high frequency signal sources, a good determination of pin locations can be determined according to the formula P.sub.i =C+i.multidot..left brkt-bot.N/M.right brkt-bot., i=1, . . . , M, where P.sub.i are the pin numbers, N is a total number of pins around the perimeter of the package, M is a total number of the high frequency signal sources, and C is an offset number.

Abstract: A semiconductor IC device requiring dense arrangements of I/O connections in which a plurality of electrode pads are arranged in a rectangular form for a quad surface mounting type package, corner electrode pads are arranged to be shifted toward inside of a semiconductor chip for reducing the distance of corner bonding wires, or corner inner leads are bent and further extended toward the chip for making shorter the span length of the corner bonding wires, so that wire sweeping and electrical shorting of the corner bonding wires during a wire bonding and a molding processes can be prevented and the reliability of the bonding wires can be improved.

Abstract: Disclosed is a pair of conductive rings and method for making the conductive rings for introducing an integral network of capacitive structures around a semiconductor die of a semiconductor package. The pair of conductive rings include a ground rail ring that is defined around a semiconductor die pad that is configured to receive a semiconductor die. The ground rail ring has a first plurality of extension spokes that extend away from the ground rail ring. The pair of conductive rings further includes a power rail ring that is defined around the semiconductor die pad. The power rail ring has a second plurality of extension spokes that extend away from the power rail ring and toward the ground rail ring.

Abstract: A semiconductor device of the present invention in which a plurality of lead terminals are provided for only one side, comprising a plurality of leads connected to the lead terminals, a semiconductor chip provided on an island and having a plurality of pads electrically connected to the leads on one side, a first extension lead which is connected to one lead terminal among the leads and at least a part of which is provided along a side of the semiconductor chip perpendicular to the side of it having the pads, a second extension lead at least a part of which is provided for a side of the semiconductor chip opposite to the side of it having the pads, and a suspension pin provided between one end of the first extension lead and one end of the second extension lead and connected to the island.

Abstract: A semiconductor device including an insulating package outer frame member, outer leads, positioning dummy leads, a heat radiating plate, and a semiconductor chip mounted to the heat radiating plate. The heat radiating plate is made from a different material from that of the outer leads, and the positioning dummy leads act to regulate the position of the heat radiating plate during the soldering process. The positioning dummy leads and the outer leads are made in a common lead frame, and are separated from each other after the soldering process, preferably after the subsequent plating process.

Abstract: The present invention provides an improved method of wire-bonding on a semiconductor chip, especially a small acceleration sensor chip which is mounted on a substrate with an adhesive having low stress characteristics such as a silicon resin. Further, the present invention provides a semiconductor device having a structure in which the improved method of wire bonding is easily applicable. The wire-bonding is performed by giving ultrasonic vibrations to the wires and the pads on which the wires are bonded while imposing pressure thereon. The vibration is given in a direction along a radial line extending from the center of the semiconductor chip.

Abstract: An integrated circuit package of this invention includes a series of nonconductive rigid substrates, each substrate having a pattern of generally coplanar bond fingers embedded thereupon. An integrated circuit die is connected to individual bond fingers of varying bond finger patterns. Individual bond fingers are connected to package terminals by medial leads, which are generally perpendicular to the bond finger patterns. Semiconductor die packages having both top and bottom package terminals are thus produced. Methods and devices are shown.

Abstract: A plastic covered semiconductor device that enables to simplify the structure and fabrication to reduce the assembly cost of the device and to reduce the thickness or height of the device. This device contains a substrate having a first surface and a second surface opposite to the first surface, a semiconductor chip mounted on or over the first surface, lead fingers joined to the first surface, interconnecting conductors electrically interconnecting the semiconductor chip with the corresponding lead fingers, respectively, and a plastic covering material formed to cover the first surface. Each lead finger is made of an inner part bonded to the first surface of the substrate and an outer part protruding the covering material. The covering material confines the semiconductor chip, the interconnecting conductors and the inner parts of the lead fingers. The second surface of the substrate is exposed from the covering material.

Abstract: In a printed circuit board on which a plurality of electronic components are mounted, a first electronic component having the largest number of input and output pins among the electronic components is arranged at or near the center of the printed circuit board. Wiring patterns including a signal line pattern, a first power supply pattern, and a first ground pattern almost radially arranged from the first electronic component, thereby mounting the electronic components at a high density with a high wiring efficiency.

Abstract: In accordance with the invention, integrated circuit dies may be packaged in a plastic package employing an area area array technology such as a conductive ball grid array, column grid array or pin grid array. One aspect of the invention is an integrated circuit package(10) which includes an electronic circuit enclosed by a plastic body (12, 14). The molded plastic body has a first major surface opposing a second major surface. The first major surface of integrated circuit (10) has a plurality of openings therein. One of a plurality of conductive pads (18) is adjacent to each one of the openings and is electrically connected to the electronic circuit. Each of a plurality of conductors (20) is electrically connected to one of the pads (18) and protrudes from one of the openings (22).

Abstract: A greater lead count for a given die area can be achieved with "certain non-square" geometries formed by the inner ends of conductive lines. These include various triangular configurations, as well as "greatly elongated" rectangular, parallelogram and trapezoidal configurations. The conductive lines may be leads of a lead frame, leads on a tape-based package, or traces on ceramic or PCB-substrate packages. The package body may be formed to have a shape similar to that of the die receiving area, and may also be provided with external pins, ball bumps or leads. A number of these "certain non-square" packages may be assembled in an electronic system on a mother board. Unpackaged "certain non-square" dies may be connected to the ends of traces on a substrate, and encapsulated to form a multi-chip module.

Abstract: A method of making a semiconductor device and the device wherein a chip is provided having plural bond pads thereon. A plurality of adjacent wires is provided, each wire having one end thereof coupled to and extending from one of the bond pads. The other end of each wire is coupled to one of a plurality of lead fingers. A mass of hardenable, flowable adhesive having a viscosity in its flowable state sufficient to enable the adhesive to rest on a the wire until hardened, preferably an epoxy, is disposed on adjacent wires and the adhesive is then hardened. Optionally, some of the adhesive is permitted to be disposed on a surface of the chip and beneath a wire and then hardened.

Abstract: A surface mounting type electronic component is provided which includes an electronic element enclosed in a resin package, and a plurality of leads electrically connected to the electronic element. Each of the leads has an inner lead portion inserted in the package and an outer lead portion extending out of the package. The outer lead portion has an end face includes a rounded bottom corner portion continuous with the flat bottom surface, a vertically scored lower portion following the rounded bottom corner portion, and a tear portion above the vertically scored portion.

Abstract: A surface mount component which can be mounted to a surface of a printed circuit board having a plurality of bonding pads connected to circuitry provided on the printed circuit board, which includes a puck having first and second wiring patterns, and a plurality of electrical connectors, a first set of electrical connectors being connected to the first wiring pattern, and a second set of the electrical connectors connected to the second wiring pattern. During the process of manufacturing a product which incorporates the printed circuit board, a production line worker can mount the puck to the surface of the printed circuit board in a selected one of a plurality of different possible positions, with at least selected ones of the first and second sets of electrical connectors being connected to respective ones of said bonding pads, to thereby achieve a selected one of a plurality of different selectable circuit configurations.

Abstract: A package for a semiconductor die having a plurality of bonding pads about its periphery is provided. The package has a plastic molding encapsulating the semiconductor die. The package also has a plurality of conductive leads with leads having inner and outer portions, the inner portions encapsulated in the molding and arranged substantially in a plane and radially about the semiconductor die with ends displaced from and forming a rectangle with four corners about the die. A bonding wire extends from each of the bonding pads to one of the inner portions of the leads. Bonding wire loop heights of approximately 8 mils are made with a specially designed tip of a capillary tool. The package also has a pair of leads with inner portions at opposite corners of the rectangle, each of the inner portions connected to a pair of bonding wires from a pair of contiguous bonding pads on the die. This double wiring arrangement prevents wire sweep during the injection molding step.

Abstract: A leadframe for use in mounting and interconnecting an integrated circuit. A first or base metal layer of the leadframe comprises at least one of brass or other copper alloy. A second, conducting layer atop the base layer comprises at least one of aluminum or an aluminum alloy. A third, upper layer on the second layer comprises at least one of copper or a copper alloy. The first, second and third layers are formed into a multilayer clad strip, a portion of at least the third layer being selectively removed to expose a selected pattern of the second layer.

Abstract: A semiconductor device for converting DC input power to AC output power includes a package having a rectangular shape with four side edges and containing a plurality of semiconductor chips therein. Two pairs of positive and negative terminals of DC input terminals are situated on the side edges to face to each other such that the same polar terminals in the positive and negative terminals face to each other. AC output terminals and control terminals are arranged on the side edges where the DC input terminals are not formed.

Abstract: A leadframe is provided for making semiconductor devices. The leadframe comprises at least one island arranged centrally widthwise of the leadframe and having four corner portions, four bridging legs radially extending from the respective corner portions of the island, the bridging legs being integral with the leadframe and island; and a multiplicity of leads radially extending toward but spaced from the island, the leads being integral with the leadframe. The leads have respective tips which are progessively closer to the island toward the respective bridging legs.

Abstract: A highly integrated electronic component comprised of a semiconductor body cast into a plastics enclosure. A multiplicity of metallic terminals protrude from the plastic enclosure, and a heat-conducting plate is cast into the plastic enclosure and is in surface contact with an underside of the semiconductor body. Good heat removal and an increase in the mechanical stability for the terminals are achieved by the heat-conducting plate being substantially planar and bearing both against the underside of the semiconductor body and against the underside of the terminals and by the upper side of the heat-conducting plate having a thin, electrically insulating layer.

Abstract: A semiconductor device comprises a semiconductor chip carrier and a semiconductor chip packaged therein with a resin. The semiconductor chip carrier comprises a printed wiring substrate with conductor patterns, a first adhesive layer formed on at least an outer peripheral portion of the substrate, a second adhesive layer formed on the conductor pattern of the substrate, a lead frame joined to the substrate through the adhesive layers and comprised of plural leads for external connection. The conductor pattern is electrically connected to a part of inner leads of the lead frame.

Abstract: The invention relates to a method of making electronic modules for electronic memory cards and to electronic modules thus obtained. Starting with a metal strip, in which patterns have been cut out and to which semiconductor chips have been attached, this assembly is placed in the cavity of a transfer mold. The cavity has two portions located on the two sides of the strip in order to ensure a good mechanical bond between the conductive parts of the pattern before it is cut from the remainder of the strip.

Abstract: A semiconductor device is provided having a semiconductor pellet that is arranged on a substantially central part of a film base in which a metal plate is overlaid with an insulating member, while inner leads are arranged on a peripheral part of the film base in a state in which they are electrically isolated from the metal plate of the film base. External terminals for a power source among external terminals of the semiconductor pellet and middle parts of the metal plate of the film base, as well as inner leads for the power source among the inner leads and peripheral parts of the metal plate are electrically connected by pieces of bonding wire, respectively.

Abstract: A TAB lead frame having concentric power/ground planes provides for even distribution of power and ground potentials about the periphery of an integrated circuit. An electrically conductive plane is divided into multiple concentric power/ground planes, each of which are electrically isolated from each other and from the leads of the TAB lead frame. A dielectric layer electrically isolates the concentric power/ground planes from the leads. Electrical connection between the power/ground planes and the leads is made as appropriate via holes through the dielectric layer. The concentric planes provide structural strength to the TAB lead frame, while the even power distribution provides consistent shielding for each lead of the lead frame, and provides flexibility as to the placement of connector pads on the integrated circuit.