Abstract: A semiconductor apparatus includes a semiconductor pellet having electrodes thereon; a plurality of lead terminals, which electrically connect the electrodes of the semiconductor pellet to terminals formed on a substrate; and a molding member, which is filled around the semiconductor pellet and upper parts of the lead terminals. The plurality of lead terminals are shaped to be elongated strips and are arranged to extend out of the molding member toward the substrate.

Abstract: A multi-chip package type semiconductor device includes an insulating substrate having first and second conductive patterns thereon, a first semiconductor chip on the insulating substrate and having a first terminal pad and a relay pad isolated from the first terminal pad. The device further includes a second semiconductor chip on the first semiconductor chip having a second terminal pad. The first semiconductor chip is connected to the first pattern by a first bonding wire. The second semiconductor chip is connected to the second pattern by a second bonding wire, which connects the second pattern to the relay pad, and a third bonding wire, which connects the relay pad to the second terminal pad. The lengths of the first, second and third bonding wire are approximately the same.

Abstract: An IC package dissipates thermal energy using thermally and electrically conductive projections. The IC package includes a substrate material with a die pad area, which is suitable to support an integrated circuit. A plurality of solder ball pads is disposed on a first surface of the substrate material and a plurality of conductive projections radiate outwardly from the die pad area and extend to cover a corresponding selected solder ball pad to facilitate the dissemination of thermal energy from the die pad area to the substrate and/or printed wiring board.

Abstract: The related arts have difficulty in efficiently dissipating the heat generated by a resin-molded semiconductor element, and thus have the problem of thermal stress causing damage to the semiconductor element. To solve the problem, a semiconductor device of the preferred embodiments includes common leads coupled to an island, and a part of the common leads projects out from a resin seal body. The projecting common leads have a coupling portion. When mounting the semiconductor device, the common leads are bridged with brazing material. Thus, the heat generated by an integrated circuit chip mounted on the island is dissipated through the common leads to the outside of the resin seal body. In the preferred embodiments of the invention, a further improvement in heat dissipation characteristics can be accomplished by increasing the surface areas of the common leads.

Abstract: An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30–50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.

Abstract: The present invention provides a flat film carrier tape for mounting electronic devices thereon which tape can enhance reliability of a semiconductor chip mounting line. The film carrier tape includes a continuous insulating layer, a wiring pattern formed of a conductor layer provided on a surface of the insulating layer, a row of sprocket holes provided along respective longitudinal edges of the insulating layer, which said row of sprocket holes are at the outer sides of the wiring pattern, and a metallic layer formed around said row of sprocket holes, wherein the metallic layer is provided in a discontinuous manner in the longitudinal direction of the insulating layer by provision of slits on the insulating layer at intervals of three to eight said sprocket holes.

Abstract: A main lead (2) is a single body comprised of an inner lead (2a) and an outer lead (2b) which are integrally formed, the bonding wires are arranged in parallel and fixed onto the inner lead (2a) by the wire bonding portions (3b), and the outer lead are exposed from the mold resin to the outside for electrical connection, and a plurality of through holes (8) penetrating the main terminal lead are formed in the outer vicinity of the wire bonding portions (3b) within the inner lead (2a), and the through holes are arranged substantially in parallel to the arrangement direction of the wire bonding portions (3b) so as to correspond to the entire wire bonding portions (3b).

Abstract: A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.

Abstract: A semiconductor device and a manufacturing method thereof are provided with downsizing and densification achieved by reducing the thickness of the semiconductor device without increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed to overlap in the range of height with the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, a wire connects the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wire. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.

Abstract: A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier, and electrically conductive external bond terminals are disposed on an edge of the substrate. Electrically conductive paths are formed in the substrate and electrically coupled between the electrically conductive tabs, the electrically conductive contacts, and the electrically conductive external bond terminals.

Abstract: A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones of the first conductive elements. A lower surface of the package may include third conductive elements, the third conductive elements to receive a second plurality of the input/output signals from respective other ones of the first conductive elements.

Abstract: A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a second stiffener to cover an opening through the second stiffener that is open at the first surface and a second surface of the second stiffener. The second surface of the second stiffener is attached to a first surface of a substantially planar substrate that has a plurality of contact pads on the first surface of the substrate. The plurality of contact pads are electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate.

Abstract: The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an image sensor chip is bonded to the conductive traces. Discrete conductive elements are attached to the conductive traces and extend below a back surface of the image sensor chip. In a second embodiment, a secondary substrate having conductive traces formed thereon is secured to the transparent substrate. In a third embodiment, a backing cap having a full array of attachment pads is attached to the transparent substrate of the first embodiment or the secondary substrate of the second embodiment. In a fourth embodiment, the secondary substrate is a flex circuit having a mounting portion secured to the second surface of the transparent substrate and a backing portion bent over adjacent to the back surface of the image sensor chip.

Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, the pillars are disposed outside the peripheries of the chips and aligned with one another, and the first pillar extends into a cavity in the second pillar. The conductive bond is within the cavity and contacts and electrically connects the pillars.

Abstract: The invention relates to an electronic device having a semiconductor chip and a leadframe. The leadframe has a flat conductor frame. A semiconductor chip connection plate is configured in the center of the flat conductor frame. The semiconductor chip connection plate is structured by elongate openings all around the position of the semiconductor chip to form an island that carries the semiconductor chip and a ring that surrounds the island. Furthermore, the invention relates to a method for producing such an electronic device and to a corresponding leadframe.

Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

Abstract: There is a need to provide a semiconductor device in which strain in a bonding member resulting from the difference in thermal deformation between a lead electrode and a semiconductor chip, which are electrically bonded to each other by the bonding member, is reduced for an improved thermal fatigue lifetime and the semiconductor chip has an improved current carrying capacity and enhanced heat dissipation.

Abstract: A semiconductor die assembly employing a voltage reference plane structure electrically isolated from, but in immediate proximity to, leads of a lead frame to which the die is electrically connected. A non-conductive adhesive or an adhesively-coated dielectric film is used to position the voltage reference plane on the leads. The voltage reference plane is electrically connected to a ground or other reference potential pin of the die through a connection to one of the leads. The assembly is encapsulated, preferably by transfer-molding of a filled polymer. More than one discrete voltage reference plane structure may be employed, for example, when the package is of an LOC configuration with two rows of leads, each having a voltage reference plane secured thereto, or a single voltage reference plane including major portions adhered to leads and interposed connection portions may be applied to all of the leads of an assembly.

Abstract: The invention provides a film carrier tape for mounting electronic devices thereon, which film carrier tape enables reliable formation of a predetermined wiring pattern in a pattern-forming region and lower production cost. The film carrier tape of the present invention for mounting electronic devices thereon, including an insulating film serving as a tape substrate, and a wiring pattern formed of a conductor layer provided on a surface of the insulating film, the insulating film having a plurality of sprocket holes provided along respective side of longitudinal edges of the wiring pattern, wherein the shortest distance between said sprocket holes and corresponding edges of said wiring pattern is less than 0.7 mm. Thus, production cost of the film carrier tape can be reduced. The invention also provides a method of manufacturing the film carrier tape.

Abstract: A semiconductor device and a manufacturing method for downsizing and densification achieved by reducing the thickness of the semiconductor device without an increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed overlapping in height the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, wires connect the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wires. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.

Abstract: The electronic component has semiconductor chips that are stacked on one another. On their active top sides, the chips having interconnects for rewiring to contact areas through contacts formed on the sawn edges of the semiconductor chip. The electronic components of overlying and underlying semiconductor chips are thus connected to one another via the through contacts.

Abstract: Leads are connected between first and second elements so that a first end of each lead is connected to the first element and a second end of each lead is connected to the second element. and the elements are moved away from one another so as to bend the leads towards a vertically-extensive disposition. The direction of each lead, prior to the movement step, is represented by a lead direction vector from the first end of the lead to the second end of the same lead. At least some of these lead direction vectors are non-parallel with at least some other lead direction vectors, but the various lead direction vectors have components in a common direction. During the vertical movement step, the first element is moved in a horizontal direction of motion in this common direction, thereby moving the first end of each lead horizontally toward the second end of that lead, so as to provide or maintain slack in the leads.

Abstract: A molded electronic component has numerous connection pins protruding on a single plane from a side surface area of an essentially cuboid housing, and a circumferential ridge of molded housing material protrudes from the other side area surfaces on the plane of the connection pins. The thickness of this ridge essentially corresponds to the thickness of the connection pins. On the side surface area located opposite the side surface area from which the connection pins protrude, in the plane of the connection pins, the ridge passes or transitions into a groove such that there is no ridge protruding outwardly beyond the side surface in this area. Thus, the component can be better placed by a tool such as a suction needle onto a printed circuit board without interference from such a ridge. The invention is particularly suitable for the production of molded electronic components whose separation plane runs through that housing surface which serves as a docking surface for a suction needle.

Abstract: A flip chip assembly is disclosed that includes a coplanar waveguide launch with a transmission line, and a bump interconnection that includes multiple ground bumps. The transmission line may be a radial transmission line. Similarly, the ground bumps may be arranged in a pseudo-coaxial configuration so as to effect a vertical transition in the flip chip assembly. A method is also disclosed that includes the steps of: providing a coplanar waveguide transmission line launch; providing a chip for attachment to the coplanar waveguide launch; arranging one or more ground bumps on the coplanar waveguide launch; and forming a bump interconnection between the coplanar waveguide launch and the chip. The coplanar waveguide launch provided in this method may include a radial transmission line. The step of arranging the multiple ground bumps may include the step of arranging multiple ground bumps in a pseudo-coaxial configuration.

Abstract: A semiconductor chip provided, at a lateral face thereof, with an electrode for external electric connection. Where a semiconductor chip has a plurality of electrodes, all the electrodes are preferably formed at one or more lateral faces of the semiconductor chip. Each electrode is preferably embedded in a groove which is formed in a lateral face of the semiconductor chip and which is opened laterally of the semiconductor chip. The semiconductor chip may be a discrete bipolar transistor element. In this case, each of the base electrode, the emitter electrode and the collector electrode is preferably formed at a lateral face of the semiconductor chip.

Abstract: A single tier cavity down integrated circuit package having a die with outer bond pads and staggered inner bond pads is described. The bond pads of the die are assigned to associated supply rings and bond fingers of the package according to a design methodology where in one embodiment at least all bond pads connected to the supply rings are outer bond pads, and staggered inner bond pads are connected to bond fingers. There is further described a method for assigning bond pads of the die to associated supply rings and bond fingers of the package, as well as, a die having staggered bond pads formed in accordance with the method of the present invention.

Abstract: Patterns for a routable interface of the signal lines of a integrated circuit device include several groups of terminals distributed about the pattern center, each group clustered along a corresponding curvilinear reference segment extending outward from the pattern center to its perimeter. Routability zones are created between each successive pair of groups. For higher terminal density, in at least one of the terminal groups of the pattern, either the offset of the terminals from the reference line segment is not uniform, or the distance of the terminals from the pattern center does not increase uniformly. A portion, preferably at least about 50% of the terminals in a group of the pattern are not collinear with, but offset from, the reference segment. A portion, preferably at least about 90% of the terminals in a given terminal group are each closer to the reference line segment of that terminal group than they are to the reference segment of another terminal group.

Abstract: In a semiconductor device, at the time of resin sealing by using a package member, a conductor is disposed in a loop so that its apex is at almost the same level as that of a surface (mounting face on which a cooling device is to be mounted) of the package member, thereby forming a contact terminal as contacting means. With the configuration, a semiconductor device capable of knowing deterioration in cooling efficiency of the cooling device by a method other than a method of detecting a temperature rise in the semiconductor device can be provided.

Abstract: A first interconnection pattern having a comb shape is formed around a semiconductor chip on a package body. A second interconnection pattern having a comb shape is formed around the first interconnection pattern. The projections of the first interconnection pattern are engaged with the projections of the second interconnection pattern. The distances between those two groups of projections and the bonding pads of the semiconductor chip are set nearly equal to each other.

Abstract: In a stacked-type semiconductor unit having a plurality of semiconductor devices stacked on a base board including a base electrode, each semiconductor device has a wiring board including an external electrode provided in an end portion thereof. The semiconductor devices are stacked on the base board such that the external electrodes are aligned with one another. Then, the external electrodes are electrically connected to the base board by solder.

Abstract: A TAB tape with a stiffener is prepared by bonding a one-metal TAB tape 20 having a structure wherein a circuit pattern 21 is formed on either surface of a first tape base material, a part thereof is covered with an insulating film 2, and a via hole 12 is defined on a connecting regional section 25 for via, to a tape 30 for second metal prepared by providing a metallic foil layer 14 on either surface of a second tape base material 15 through an adhesive layer 15; the connecting regional section 25 for via on the upper edge of a via hole is electrically connected with a part of the metallic foil layer 14 on the bottom of the hole by means of conducting means (4, 16, and 18), and at the same time, an exposed portion 32 of the metallic foil layer 14, which has not been covered with the one-metal TAB tape 20, is connected to an electrode 71 of a ground line in the semiconductor 7 by means of a bonding wire 83 to lead a ground potential.

Abstract: A semiconductor package with an embedded heat-dissipating device is proposed. The heat-dissipating device including a heat sink and a plurality of connecting bumps attached to connecting pads formed on the heat sink is mounted on a substrate by reflowing the connecting bumps to ball pads of the substrate. The connecting bumps and the ball pads help buffer a clamping force generated during the molding process, so as to prevent a packaged semiconductor chip from being cracked. Moreover, the reflowing process allows the connecting bumps to be self-aligned on the substrate, so as to assure the toning and planarity of the heat sink mounted thereon. Accordingly, during molding, the precisely-positioned beat sink can have its upper side closely abutting an upper mold, allowing a molding resin to be prevented from flashing on the upper side thereof i.e.

Abstract: A packaged semiconductor having increased solder joint strength. The packaged semiconductor includes a semiconductor chip and a plurality of bond pads on the semiconductor chip. A leadframe includes a chip paddle, a plurality of tie bars connected to corners of the chip paddle and a plurality of dam bars. A plurality of leads connect to the leadframe, and are radially formed at regular intervals along and spaced apart from the chip paddle, and extend towards the chip paddle. A plurality of conductive wires electrically connect the leads and the semiconductor chip. Encapsulation material encapsulates the semiconductor chip, wires, chip paddle, and leads to form a package body, wherein dam bars formed on the leadframe limit flow of the encapsulation material. The chip paddle, plurality of leads and plurality of tie bars are externally exposed at peripheral side and bottom surfaces to allow depressions to be formed thereon.

Abstract: A first semiconductor chip (2) is bonded and secured to a second semiconductor chip (3) with a back surface of the first semiconductor chip (2) and a circuit forming surface (3X) of the second semiconductor chip (3) facing each other, and an inner portion of a support lead (6) is bonded and secured to the circuit forming surface (3X) of the second semiconductor chip (3). Such a configuration makes it possible to provide a semiconductor with a reduced thickness.

Abstract: A substrate for a semiconductor apparatus, a semiconductor apparatus and a method of manufacturing thereof and an electronic apparatus are provided that achieve excellent productivity and cost reduction. A semiconductor apparatus is formed from a substrate and a semiconductor device wire-bonded thereto. The substrate includes a substrate main body and pluralities of leads formed on a mounting surface of the substrate on which the semiconductor device is mounted. Conduction sections electrically connected to each of the leads define at least a part of external terminals. The leads have portions located under the semiconductor device, with the remaining portions located outside the semiconductor device depending upon the size of the semiconductor device.

Abstract: A wiring board according to the present invention has a substrate, a plurality of lines provided on the substrate, an interference-preventive conductor layer provided between the lines to have open ends and prevent signal interference between the lines, and a via electrically connected to the interference-preventive conductor layer. The via is provided at a point at which a distance from each of the open ends of the interference-preventive conductor layer is less than one quarter of a wavelength corresponding to a maximum frequency component of harmonic components contained in the signal.

Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, and the pillars are disposed outside the peripheries of the chips and aligned with one another. The conductive bond contacts and electrically connects the pillars.

Abstract: In a dual-sided chip package without a die pad according to the invention, a first die can be fixed directly on the lead fingers of a leadframe, a support bar, or bus bars, while a second die is attached to the first die. Without a die pad, the distance between the surfaces of the dies and the plastic surface of the package therefore gets longer. Thus, the invention enables a large decrease in the probability of generating voids in the plastic and there is no need to grind the dies. Besides, it improves the vibration and floating characteristics of the dies in the manufacturing process and thus prevents the exposure of the bonding wires and the shelling off or breaking of the dies. The invention can raise the yield of chip packages.

Abstract: Provided is an interposer tape which provides electrical communication between a die and a packaging substrate. The dimensions of the interposer tape may vary to accommodate a variety of die sizes for the same packaging substrate. The interposer tape includes an array of traces. A first set of wire bonds is formed between the array of traces and the die. A second set of wire bonds is formed between the array of traces and the packaging substrate.

Abstract: An aspect of the present invention provides a semiconductor chip package that can accommodate many outer leads in a relatively small package outline. The package includes a package body and outer leads along the outline of the package body. The package body outline has concave portions to increase the number of outer leads without increasing the package footprint. For example, the package can have a QFP outline with concave portions on the sides of the QFP outline. The package can have an SOP outline with concave portions on two opposite sides of the SOP outline.

Abstract: The side of one of the source electrodes 7a and 7b of two semiconductor modules Q1 and Q2 corresponding to a pair of upper and lower arms are installed parallel with the outer side of the other source electrode inside packages 8a and 8b. Both the modules are arranged parallel to one another in such a way that both the sides are opposed, an inter-module electrode terminal 15 for connecting the source electrode 7a of the module Q1 and the drain electrode (base substrate) 6b of the module Q2 is formed in a block shape, and one end of the inter-module electrode terminal 15 is vertically installed parallel and close to the side of the source electrode 7b on the base substrate of the module Q2.

Abstract: A semiconductor package includes a semiconductor chip which is mounted on a die pad which is smaller than the semiconductor chip, a die pad supporter which supports the die pad, the die pad supporter having a stress absorbing portion and the stress absorbing portion which is disposed under the semiconductor chip.

Abstract: A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

Abstract: A semiconductor device is provided with a semiconductor chip and a connection lead connected to a pad of the semiconductor chip. The connection lead has a tip part which is bent up to a surface of the semiconductor chip on the opposite side of the pad. The semiconductor device is further provided a resin sealed part covering the semiconductor chip and a solder ball provided on the tip part of the connection lead.

Abstract: A chip module has a contact area disposed on its outer side formed of a plurality of essentially flat contact elements of electrically conductive material insulated from one another. At least one semiconductor chip having one or more integrated semiconductor circuits that are electrically connected to the contact elements of the contact area via bonding wires. The contact elements of the chip module are formed by a prefabricated lead frame for supporting the at least one semiconductor chip and have on two opposing sides of the chip module outwardly offset terminals arranged in rows next to one another. The outwardly offset terminals are provided for surface mounting the chip module on the mounting surface of an external printed circuit board or an external circuit board substrate.

Abstract: An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. An underfill material is introduced between each lead finger and semiconductor die, extending from the bonding location of the die and the edge of the die, in order to prevent filler particles from lodging between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The seal created by P the underfill material reduces point stresses on the active surface of the die usually caused by the filler particles. The decreased flexure in the leads further enhances the locking of the leads in position with respect to the die.

Abstract: A micromodule is used as a surface-mounted package on a substrate of interconnections. In one embodiment of the invention, barriers to the expansion of solder are formed between contact zones of the micromodule and corresponding contact pads of the substrate. A mechanical stopping device is planned to keep the thickness of the interface of solder. In another embodiment of the invention, contact zones are extended by tongues. A cambering operation enables the formation of the surface-mounting pins.

Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a support layer and conductive structures extending across a surface of the support layer. The conductive structures have anchors connecting them to the support layer, and releasable or unanchored portions.

Abstract: There is provided a technique of connecting easily the lead terminal to the board of the module. A plurality of clip lead terminals each has at one end thereof clip portions which are connected electrically to connecting terminals by sandwiching an end portion of a board of a module and the connecting terminals formed thereon between clip members of said clip portions and has a lead portion at the other end thereof. The clip lead terminals are arranged so as to be spaced from one another in parallel with one another with the leading edges of the respective clip portions aligned on a straight line. The clip lead terminals are connected to one another through a tie bar and a guide as a connecting portion, respectively, whereby the connecting clip lead terminal 18 is formed as one-body. The lead portions are bent on every other one, leading end portions of the bent lead portions and leading end portions of the non-bent lead portions are in parallel with each other viewing from a side of the board.