Composite Ceramic, Or Single Ceramic With Metal Patents (Class 257/703)
  • Patent number: 10916687
    Abstract: The present invention relates to a silica glass member including: a main body including a silica glass and having a bonding part for bonding to another member; and a bonding film which is provided on the bonding part, has a thickness of 0.2 ?m to 10 ?m, and includes Au and a glass formed through melting of glass frit, in which the bonding film is produced from Au powder having an average particle diameter of 3 ?m or less and glass frit having a softening point of 850° C. or lower, a process for producing a silica glass member, and a process for bonding a ceramic and a silica glass.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 9, 2021
    Assignee: COORSTEK KK
    Inventors: Hiroaki Kobayashi, Yu Yokoyama, Ramesh Vallepu, Hirotaka Hagihara
  • Patent number: 10770367
    Abstract: A semiconductor apparatus includes: a substrate including a circuit pattern on an upper surface side and a metal plate on a lower surface side; a semiconductor device joined to the circuit pattern via a conductive component; a case located to surround the substrate; a sealing material sealing the semiconductor device and the substrate in a section surrounded by the case; and a bonding agent bonding the case and the metal plate on a side face of the substrate.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 8, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Kitabayashi, Hiroshi Yoshida, Hidetoshi Ishibashi, Daisuke Murata
  • Patent number: 10763244
    Abstract: The present disclosure relates to power modules. The teachings thereof may be embodied in a power unit and/or a drive unit for driving the power unit, along with methods for producing a power module. For example, a power module may include: a power unit including a heat sink; a power device disposed on the heat sink; an insulating layer covering the heat sink and the power device; and a drive unit for driving the power unit, the drive unit comprising a contact element corresponding to the contact area of the power unit. An underside of the power unit is defined by an underside of the heat sink. A top side of the power unit is defined by a contact area thermally and/or electrically coupled to the power device and a surface of the insulating layer surrounding the contact area. The contact element may be disposed abutting the contact area of the power unit for making electrical and/or thermal contact with the power device.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: September 1, 2020
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Karl Weidner, Kai Kriegel
  • Patent number: 10707146
    Abstract: Provided is a semiconductor device having high heat conductivity and high productivity. A semiconductor device includes an insulating substrate, a semiconductor element, a die-bond material, a joining material, and a cooler. The insulating substrate has an insulating ceramic, a first conductive plates disposed on one surface of the insulating ceramic, and a second conductive plate disposed on another surface of the insulating ceramic. The semiconductor element is disposed on the first conductive plate through the die-bond material. The die-bond material contains sintered metal. The semiconductor element has a bending strength degree of 700 MPa or more, and has a thickness of 0.05 mm or more and 0.1 mm or less. The cooler is joined to the second conductive plate through the joining material.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 7, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Motoru Yoshida, Yoshiyuki Suehiro, Kazuyuki Sugahara, Yosuke Nakanishi, Yoshinori Yokoyama, Shinnosuke Soda, Komei Hayashi
  • Patent number: 10504749
    Abstract: A semiconductor device of the present invention includes a circuit layer formed of a conductive material, a semiconductor element mounted on a first surface of the circuit layer, and a ceramic substrate disposed on a second surface of the circuit layer, in which a Ag underlayer having a glass layer and a Ag layer laminated on the glass layer is formed on the first surface of the circuit layer, and the Ag layer of the Ag underlayer and the semiconductor element are directly joined together.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: December 10, 2019
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Shuji Nishimoto, Yoshiyuki Nagatomo
  • Patent number: 10504855
    Abstract: A semiconductor package includes a support member having a first surface and a second surface, and having a through-hole, a first metal layer for shielding disposed on an internal sidewall of the through-hole and the first surface and the second surface of the support member, a connection member disposed on the first surface of the support member, and having a redistribution layer, a semiconductor chip disposed in the through-hole, an encapsulant sealing the semiconductor chip located in the through-hole, and covering the second surface of the support member, a second metal layer for shielding disposed on the encapsulant, and connected to the first metal layer for shielding by a connecting trench via passing through the encapsulant, and a reinforcing via disposed in a region, overlapping the trench via for connection, of the support member, and connected to the first metal layer for shielding.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Moon Jung, Chul Kyu Kim, Seok Hwan Kim, Kyung Ho Lee, Seong Hwan Park
  • Patent number: 10453772
    Abstract: Provided is a heat-sink-attached power-module substrate, in which a metal layer and first layers are formed from aluminum sheets having a purity of 99.99 mass % or greater and a heat sink and second layers are formed from aluminum sheets having a purity lower than that of the metal layer and the first layers: when a thickness is t1 (mm), a joined-surface area is A1 (mm2), yield strength at 25° C. is ?11 (N/mm2), yield strength at 200° C. is ?12 (N/mm2) in the second layers; a thickness is t2 (mm), a joined-surface area is A2 (mm2), yield strength at 25° C. is ?21 (N/mm2), and yield strength at 200° C. is ?22 (N/mm2) in the heat sink.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: October 22, 2019
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Tomoya Oohiraki, Sotaro Oi
  • Patent number: 10453742
    Abstract: A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 10453783
    Abstract: A power module substrate of the present invention includes a ceramic substrate and a circuit layer having a circuit pattern. In an interface between the circuit layer and the ceramic substrate, a Cu—Sn layer and a Ti-containing layer are laminated in this order from the ceramic substrate side. In a cross-sectional shape of an end portion of the circuit pattern of the circuit layer, an angle ? formed between a surface of the ceramic substrate and an end face of the Cu—Sn layer is set in a range equal to or greater than 80° and equal to or smaller than 100°, and a maximum protrusion length L of the Cu—Sn layer or the Ti-containing layer from an end face of the circuit layer is set in a range equal to or greater than 2?m and equal to or smaller than 15 ?m.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: October 22, 2019
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Toyo Ohashi, Yoshiyuki Nagatomo
  • Patent number: 10410952
    Abstract: Power semiconductor packages described herein each include a substrate having two or more metal layers and one or more insulating layers for separating the metal layers. The substrate insulating layers are formed from a polymer material to reduce the CTE mismatch between the substrate metal layers and the substrate insulating layers.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: September 10, 2019
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 10411498
    Abstract: A sensor integrated circuit includes an energy storage device having a first terminal coupled to a functional circuit and a blocking circuit coupled between a power supply pin and the first terminal of the energy storage device. The blocking circuit permits the energy storage device to store energy from an external power supply coupled to the power pin. The first terminal of the energy storage device is inaccessible from outside of the sensor IC. Additional features of the sensor IC can include a high regulator, a low regulator, and a low power circuit.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: September 10, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventors: Eric G. Shoemaker, P. Karl Scheller, Devon Fernandez
  • Patent number: 10403512
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
  • Patent number: 10393013
    Abstract: Disclosed are a coating layer including pores for thermal insulation and a method of preparing the same. As such, the coating layer may secure low thermal conductivity, low volume heat capacity and improved durability, such that the coating layer can be applied to an internal combustion engine.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: August 27, 2019
    Assignee: Hyundai Motor Company
    Inventors: Woong Pyo Hong, In Woong Lyo, Hong Kil Baek, Su Jung Noh, Seung Jeong Oh, Seung Woo Lee, Bokyung Kim
  • Patent number: 10283447
    Abstract: A power semiconductor module includes one or more power semiconductor dies attached to a first main face of a substrate, a plastic housing attached to the substrate, which together with the substrate encloses the one or more power semiconductor dies, a plurality of power terminals attached to the first main face of the substrate at a first end, and extending through the plastic housing at a second end to provide a point of external electrical connection for the one or more power semiconductor dies, a potting compound embedding the one or more power semiconductor dies, the first main face of the substrate and at least part of the first end of the plurality of power terminals, and an insulative coating applied only to parts of the plurality of power terminals disposed inside the plastic housing and in contact with just air. A corresponding method of manufacture also is provided.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: May 7, 2019
    Assignee: Infineon Technologies AG
    Inventors: Torsten Groening, Thomas Nuebel, Reinhold Spanke
  • Patent number: 10249516
    Abstract: Arrays of objects on a substrate having void-free underfill as well as methods and systems of forming the same include forming a void-free layer of underfill material between a substrate and an array of multiple objects positioned on the substrate. The void-free layer of underfill material is cured to form a protective cured underfill layer that provides structural support to connections between the objects and the substrate.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Evan George Colgan, Michael Anthony Gaynes, Katsuyuki Sakuma, Donald Alan Merte
  • Patent number: 10224264
    Abstract: Aspects of the disclosure are directed to a package including a substrate, die coupled to the substrate, wick deposited on the die, and an evaporation-condensation chamber having a hollowed bottom and two bottom lips, wherein the wick mates into the hollowed enclosure and substantially merges with the two bottom lips forming a sealed chamber. Other aspects are directed to a method of forming a package including coupling a die to a substrate, depositing a wick on the die, and mating the wick with an evaporation-condensation chamber having a hollowed enclosure and two bottom lips, wherein the mating attaches the wick into the hollowed enclosure and substantially merges the wick with the two bottom lips forming a sealed chamber. By directly depositing the wick over the die and integrating the wick with the encapsulation-condensation chamber, this integrated solution provides significant improvement in package thermal resistance especially for high-power and high-performance applications.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: March 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ali Akbar Merrikh, Mehdi Saeidi, Guoping Xu, Damion Gastelum, Luis Eduardo De Los Heros Beunza, Ajay Vadakkepatt, Rama Rao Goruganthu
  • Patent number: 10173282
    Abstract: The bonded body of the present invention includes: a ceramic member made of ceramics; and a Cu member which is made of Cu or a Cu alloy and bonded to the ceramic member through a Cu—P—Sn-based brazing filler material and a Ti material, wherein a Cu—Sn layer, which is positioned close to the ceramic member and in which Sn forms a solid solution with Cu, and a Ti layer which is positioned between the Cu member and the Cu—Sn layer, are formed at a bonded interface between the ceramic member and the Cu member, a first intermetallic compound layer made of Cu and Ti is formed between the Cu member and the Ti layer, and a second intermetallic compound layer containing P is formed between the Cu—Sn layer and the Ti layer.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: January 8, 2019
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Nobuyuki Terasaki, Yoshiyuki Nagatomo
  • Patent number: 10026665
    Abstract: For a purpose of raising the breakdown voltage of a semiconductor device, the creepage distance and clearance between an electrode terminal and another metallic portion are preferably increased. A semiconductor device is provided, the semiconductor device including: a semiconductor element; a case portion that houses the semiconductor element; and an external terminal provided to a front surface of the case portion, wherein the front surface of the case portion has, formed thereon: a wall portion that protrudes from the front surface; and a hollow portion that is provided to a region surrounded by the wall portion and is depressed relative to the front surface, and the external terminal is arranged on a floor surface of the hollow portion.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: July 17, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshinari Ikeda
  • Patent number: 10004143
    Abstract: A printed wiring board includes a first circuit substrate having a first surface and a second surface on the opposite side, and a second circuit substrate having a third surface and a fourth surface on the opposite side such that the first circuit substrate is laminated on the third surface and that the first surface and the third surface are opposing each other. The second circuit substrate has a mounting area on the third surface and includes pads positioned to mount an electronic component in the mounting area and a connection wire structure connected to the pads, and the first circuit substrate includes through-hole conductors extending from the first surface to the second surface and connected to the pads through the connection wire structure and has an opening portion formed through the first circuit substrate such that the opening portion is exposing the pads formed in the mounting area.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: June 19, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Haiying Mei, Hiroyuki Ban
  • Patent number: 9935044
    Abstract: The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiu-Jen Lin, Wen-Hsiung Lu, Cheng-Ting Chen, Hsuan-Ting Kuo, Wei-Yu Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9935144
    Abstract: An image sensor package includes a ceramic substrate with a cavity disposed in the ceramic substrate. A glass layer is adhered to the ceramic substrate and encloses the cavity in the ceramic substrate. An image sensor is disposed in the cavity between the glass layer and the ceramic substrate to electrically isolate the image sensor. An image sensor processor is disposed in the cavity and electrically coupled to the image sensor to receive image data from the image sensor.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: April 3, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Wei-Feng Lin, Chi-Chih Huang, En-Chi Li
  • Patent number: 9898911
    Abstract: The inventive concept provides MIT devices molded by clear compound epoxy and fire detecting devices including the MIT device. The fire detecting device is supplied with a power source from a power control device. The fire detecting device includes a MIT device including a MIT chip molded by a clear compound epoxy, a diode bridge circuit supplied with the power source from the power control device for providing a non-polar power source, a notice circuit supplied with the non-polar power source from the diode bridge circuit for warning of a fire alarm in response to a detecting signal from the MIT device, and a stabilization circuit for maintaining the detecting signal for a certain period.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: February 20, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyun-Tak Kim, Bongjun Kim, Jong Chan Park
  • Patent number: 9711937
    Abstract: A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: July 18, 2017
    Assignee: SpectraSensors, Inc.
    Inventors: Alfred Feitisch, Gabi Neubauer, Mathias Schrempel
  • Patent number: 9711707
    Abstract: A method for manufacturing an electronic device includes a through electrode forming step of forming a through electrode on an insulating base substrate; an electronic element mounting step of mounting an electronic element on one surface of the base substrate; a cover body placing step of bonding a cover body accommodating the electronic element; a conductive film forming step of forming a conductive film on the other surface of the base substrate and on an end face of the through electrode exposing on the other surface; an electrode pattern forming step of forming an electrode pattern on the end face of the through electrode and on the surface of the periphery of the end face while leaving the conductive film; and an external electrode forming step of forming an external electrode by accumulating an electroless plated film on the surface of the electrode pattern by an electroless plating method.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: July 18, 2017
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Atsushi Kozuki
  • Patent number: 9673128
    Abstract: A power module includes: an insulating layer; a leadframe (metal layer) disposed on the insulating layer; a semiconductor chip disposed on the leadframe; and a mold resin formed so as to cover the semiconductor chip, at least a part of the metal layer, and at least a part of the insulating layer, wherein the insulating layer includes a relatively-soft insulating layer disposed at a side of the leadframe and a relatively-hard insulating layer disposed at an opposite side of the leadframes. Accordingly, there can be provided the power module with improved cooling capability and improved reliability, and the fabrication method for such a power module.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: June 6, 2017
    Assignee: ROHM CO., LTD
    Inventors: Katsuhiko Yoshihara, Masao Saito
  • Patent number: 9673140
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: June 6, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chia-Cheng Chen, Ming-Chen Sun, Tzu-Chieh Shen, Shih-Chao Chiu, Wei-Chung Hsiao, Yu-Cheng Pai, Don-Son Jiang
  • Patent number: 9648732
    Abstract: A semiconductor device includes: a conductive-patterned insulating substrate; conductive blocks fixed to conductive patterns of the conductive-patterned insulating substrate; a semiconductor chip fixed to each conductive block; a printed circuit board that has a conductive post fixed to the semiconductor chip; and a resin. The semiconductor device is configured such that the average volume of a conductive film per unit area of each conductive pattern around a section thereof, to which the corresponding conductive block is fixed, is reduced from the conductive block toward the outside.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: May 9, 2017
    Assignee: FUJI ELECTRIC CO, LTD.
    Inventors: Youko Nakamura, Norihiro Nashida
  • Patent number: 9620969
    Abstract: A storage battery equalization device is provided with: a battery pack including a plurality of storage battery modules; a plurality of equalization circuits corresponding to the respective storage battery modules, each including a DC/AC mutual converter circuit, a variable capacitor, and a transformer; external wirings interconnecting secondary windings of the transformers; voltage monitors each being connected across both electrodes of a corresponding storage battery module; and an equalization control unit.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: April 11, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shoichi Kobayashi, Takashi Shindoi, Hiroshi Araki, Kenji Inomata, Toshihiro Wada, Shoji Yoshioka
  • Patent number: 9573840
    Abstract: An antimony-free glass suitable for use in a frit for producing a hermetically sealed glass package is described. The hermetically sealed glass package, such as an OLED display device, is manufactured by providing a first glass substrate plate and a second glass substrate plate and depositing the antimony-free frit onto the first substrate plate. OLEDs may be deposited on the second glass substrate plate. An irradiation source (e.g., laser, infrared light) is then used to heat the frit which melts and forms a hermetic seal that connects the first glass substrate plate to the second glass substrate plate and also protects the OLEDs. The antimony-free glass has excellent aqueous durability, good flow, low glass transition temperature and low coefficient of thermal expansion.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: February 21, 2017
    Assignee: CORNING INCORPORATED
    Inventors: Melinda Ann Drake, Robert Michael Morena
  • Patent number: 9564937
    Abstract: Devices and methods related to packaging of radio-frequency (RF) devices on ceramic substrates. In some embodiments, a packaged electronic device can include a ceramic substrate configured to receive one or more components. The ceramic substrate can include a conductive layer in electrical contact with a ground plane. The packaged electronic device can further include a die having an integrated circuit and mounted on a surface of the ceramic substrate. The packaged electronic device can further include a conformal conductive coating implemented over the die to provide shielding functionality. The packaged electronic device can further include an electrical connection between the conformal conductive coating and the conductive layer.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: February 7, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Anthony James Lobianco, Howard E. Chen, David Scott Whitefield
  • Patent number: 9545015
    Abstract: A method for connecting two objects electrically by an electroconductive liquid is described. The method includes providing a substrate having a first surface and a second surface opposite to the first surface. Thereafter, the method includes forming a channel of the liquid on the first surface of the substrate to extend along the first surface of the substrate. Further, the method includes forming a through hole in the substrate. Moreover, the method includes arranging the two objects to interpose the substrate, wherein the two objects overlap with the openings of the through hole. Next, the method further includes filling the liquid to the through hole via the channel, bringing the liquid in contact with the two objects, and hardening the liquid. Further still, the method further includes wherein a surface of the liquid hole bulges to form a projection which makes contact with one of the two objects.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: January 10, 2017
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Hiroto Sugahara
  • Patent number: 9524917
    Abstract: A semiconductor device that includes a semiconductor chip having a first silicon substrate with opposing first and second surfaces, a semiconductor device formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the semiconductor device, a layer of thermal conductive material on the second surface, and a plurality of first vias formed partially through the layer of thermal conductive material.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: December 20, 2016
    Assignee: OPTIZ, INC.
    Inventor: Vage Oganesian
  • Patent number: 9461190
    Abstract: A sensor device and method of making same that includes a silicon substrate with opposing first and second surfaces, a sensor formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the sensor, and a plurality of cooling channels formed as first trenches extending into the second surface but not reaching the first surface. The cooling channels instead can be formed on one or more separate substrates that are attached to the silicon substrate for cooling the silicon substrate.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: October 4, 2016
    Assignee: OPTIZ, INC.
    Inventors: Vage Oganesian, Zhenhua Lu
  • Patent number: 9446588
    Abstract: A liquid ejecting head includes a piezoelectric element including a first electrode, a second electrode, and a piezoelectric layer between the first and the second electrodes. The piezoelectric layer includes a buffer layer disposed on the first electrode and containing Bi and an element selected from Al, Si, Cr, and Mn and a complex oxide layer disposed on the buffer layer and having a perovskite structure containing Bi, Fe, Ba, and Ti.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: September 20, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Tomohiro Sakai
  • Patent number: 9390853
    Abstract: There is provided a multilayer ceramic capacitor including a ceramic body having first and second main surfaces, third and fourth end surfaces, and fifth and sixth side surfaces; a plurality of first and second internal electrodes having a dielectric layer to be alternately exposed to the third and fourth end surfaces; and first and second external electrodes formed on the end surfaces and the main surfaces and electrically connected to the first and second internal electrodes, wherein when a width of the first or second external electrode is A and a length of a margin part of the ceramic body in the length direction is B, a ratio (A/B) of the width of the first or second external electrode to the length of the margin part of the ceramic body in the length direction is 3.3 or less (A/B?3.3).
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: July 12, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Soo Park, Heung Kil Park
  • Patent number: 9331011
    Abstract: An electronic component built-in substrate, includes, a substrate having an opening portion, a first wiring layer formed in the substrate, an electronic component arranged in the opening portion, a first insulating layer formed on one face of the substrate and sealing the electronic component, a second insulating layer formed on other face of the substrate, a second wiring layer formed on the first insulating layer, and a third wiring layer formed on the second insulating layer. The first insulating layer is formed of an inner insulating layer covering the one face of the substrate and filling an inside of the opening portion, and an outer insulating layer formed on the inner insulating layer.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 3, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takayuki Kiwanami, Junji Sato
  • Patent number: 9240526
    Abstract: Solid state light emitting diode packages can be provided including a ceramic material and a leadframe structure, on the ceramic material, the leadframe structure including a portion thereof that integrates the leadframe structure with the ceramic material.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: January 19, 2016
    Assignee: Cree, Inc.
    Inventor: Peter S. Andrews
  • Patent number: 9220164
    Abstract: A high frequency module includes a ground mounting electrode connected to a ground terminal of a component, a first ground in-plane conductor in a multilayer substrate on a portion under the component and connected to the ground mounting electrode with a first ground interlayer connecting conductor, a signal mounting electrode connected to a signal terminal of the component, and a signal in-plane conductor provided in the multilayer substrate on a portion under the first ground in-plane conductor and connected to the specific signal mounting electrode with a signal interlayer connecting conductor. The first ground in-plane conductor is between the component and the signal in-plane conductor, and the signal interlayer connecting conductor is on an outer side portion of the first ground in-plane conductor when seen from above.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: December 22, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hiromichi Kitajima
  • Patent number: 9166364
    Abstract: A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: October 20, 2015
    Assignee: SpectraSensors, Inc.
    Inventors: Alfred Feitisch, Gabi Neubauer, Mathias Schrempel
  • Patent number: 9087701
    Abstract: A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.
    Type: Grant
    Filed: April 30, 2011
    Date of Patent: July 21, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: DongSam Park, YongDuk Lee
  • Patent number: 9041190
    Abstract: A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing 98 wt % or more of one metallic element such as silver having a melting point of 400° C. or higher, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazutaka Takagi
  • Patent number: 9035448
    Abstract: Semiconductor packages are provided that have a base plate with a matrix of pure silver or a silver alloy and reinforcement particles. The reinforcement particles can include high thermal conductivity, low CTE particles selected from the group consisting of diamond, cubic boron nitride (c-BN), silicon carbide (SiC), and any combinations thereof. In some embodiments, the base plate is entirely comprised of the composite. In other embodiments, the base plate has a core made of the composite. The core can include at least one outer layer on the core. The semiconductor package can include one or more dice or transistors on the base plate, an insulated frame on the base plate, and one or more leads on the insulated frame.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 19, 2015
    Assignee: Materion Corporation
    Inventors: George Michael Wityak, Richard Koba
  • Patent number: 9013034
    Abstract: A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing copper and a low-melting-point metal such as tin, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 8994168
    Abstract: A semiconductor package includes a wiring board; a semiconductor chip mounted on the wiring board; and a radiation plate mounted on the semiconductor chip, including an insulating member including a resin that is the same as a resin included in the wiring board, as a main constituent, a first metal foil formed on a first surface of the insulating member, a second metal foil formed on a second surface of the insulating member, the second surface being an opposite to the first surface, the radiation plate being provided with a through hole that penetrates the first metal foil, the insulating member and the second metal foil, and a metal layer formed to cover the inner surface of the through hole to thermally connect the first metal foil and the second metal foil by penetrating the insulating member in a thickness direction.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Yukio Sato
  • Patent number: 8946885
    Abstract: A semiconductor arrangement includes a ceramic mount and at least one semiconductor component fixed-to the ceramic mount. The ceramic mount includes a first section, and the first section is electrically conductive.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: February 3, 2015
    Assignee: Robert Bosch GmbH
    Inventor: Andreas Krauss
  • Patent number: 8921996
    Abstract: A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: December 30, 2014
    Assignee: Mitsubishi Materials Corporation
    Inventors: Yoshirou Kuromitsu, Yoshiyuki Nagatomo, Takeshi Kitahara, Hiroshi Tonomura, Kazuhiro Akiyama
  • Patent number: 8901723
    Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: December 2, 2014
    Assignee: IXYS Corporation
    Inventors: Thomas Spann, Holger Ostmann, Kang Rim Choi
  • Patent number: 8853006
    Abstract: A method of manufacturing a semiconductor device comprises a mounting step of mounting a semiconductor element having an Au—Sn layer on a substrate, wherein the mounting step includes a paste supplying step of supplying an Ag paste having an Ag nanoparticle onto the substrate, a device mounting step of mounting a side of the Au—Sn layer of the semiconductor element on the Ag paste, and a bonding step of alloying the Au—Sn layer and the Ag paste to bond the semiconductor element to the substrate, wherein the Au—Sn layer has a content rate of Au of 50 at % to 85 at %.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: October 7, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Syota Shimonishi, Hiroyuki Tajima, Yosuke Tsuchiya, Akira Sengoku
  • Patent number: 8845909
    Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 30, 2014
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Tzu-Shih Shen
  • Patent number: 8823163
    Abstract: An antimony-free glass comprising TeO2 and/or Bi2O3 suitable for use in a frit for producing a hermetically sealed glass package is described. The hermetically sealed glass package, such as an OLED display device, is manufactured by providing a first glass substrate plate and a second glass substrate plate and depositing the antimony-free frit onto the first substrate plate. OLEDs may be deposited on the second glass substrate plate. An irradiation source (e.g., laser, infrared light) is then used to heat the frit which melts and forms a hermetic seal that connects the first glass substrate plate to the second glass substrate plate and also protects the OLEDs disposed therein. The antimony-free glass has excellent aqueous durability, good flow, and low glass transition temperature.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: September 2, 2014
    Assignee: Corning Incorporated
    Inventors: Melinda Ann Drake, Robert Michael Morena