Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.

Abstract: A multilayer capacitor includes a body including a capacitance formation region in which at least one first internal electrode and at least one second internal electrode are alternately stacked in a first direction with at least one dielectric layer interposed therebetween, and first and second external electrodes disposed on the body and spaced apart from each other to be connected to the at least one first internal electrode and the at least one second internal electrode, wherein a portion of the at least one first internal electrode and a portion of the at least one second internal electrode overlap each other in the first direction, the capacitance formation region further includes a third internal electrode connected to the first external electrode, a fourth internal electrode connected to the second external electrode, and a fifth internal electrode not connected to the first and second external electrodes and overlapping each of the third and fourth internal electrodes in the first direction, an intern

Abstract: A semiconductor device includes: a first semiconductor chip having a metal layer on a top surface; a first wiring member arranged to face the metal layer; a sintered-metal layer arranged between the metal layer and the first wiring member, having a first region and a plurality of second regions provided inside the first region, the second regions having lower tensile strength than the first region; and a metallic member arranged inside the sintered-metal layer, wherein the second regions of the sintered-metal layer have lower tensile strength than the metal layer of the first semiconductor chip.

Abstract: Semiconductor devices with a conformal coating in contact with a ground plane at a bottom side of the semiconductor devices and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a first surface of a package substrate. The semiconductor device can also include a molded material covering at least a portion of the package substrate and the semiconductor die. The semiconductor device can also include a ground plane in the package substrate and exposed through an opening in a second surface of the package substrate opposite the first surface. The semiconductor device can also include a conformal coating coupled to the ground plane through the opening that can shield the semiconductor device from electromagnetic interference.

Abstract: A multilayer substrate includes a multilayer body, an internal wire, land electrodes, and a ground electrode. The internal wire extends toward the land electrode from a position where the internal wire overlaps the land electrode when viewed from a first surface and is electrically connected to the land electrode by a via conductor. The internal wire is electrically connected to the ground electrode by a via conductor that is provided in a region from a position where a capacitor is located where the via conductor at least partially overlaps the land electrode when viewed from the first surface.

Abstract: A multi-layered spacer of which a thermal expansion coefficient and a thermal conductivity are controllable and a double-sided cooling power module including the multi-layered spacer, is provided between a semiconductor chip and a substrate in a double-sided cooling power module. The multi-spacer includes first metal layers made of a first metal and provided as at least respective outermost layers, and a second metal layer made of a second metal having a thermal expansion coefficient lower than a thermal expansion coefficient of the first metal and disposed between the first metal layers provided as the outermost layers.

Abstract: A multilayer coil component includes a body including laminated ferrite layers, a coil conductor including conductive layers laminated in the body, and a pair of outer electrodes disposed on a lower surface of the body. Each of the pair of outer electrodes is electrically connected to a corresponding one of end portions of the coil conductor. Each of the outer electrodes includes an underlying electrode and a plating layer disposed on the underlying electrode. The underlying electrode is disposed at a distance from a side surface of the body.

Abstract: A Light Detection and Ranging (LiDAR) module for a vehicle can include a semiconductor integrated circuit with a microelectromechanical system (MEMS) and a substrate, the MEMS comprising a micro-mirror assembly including a mirror and a gimbal structure. The gimbal can be configured concentrically around and coplanar with the mirror. When rotated, the gimbal drives the mirror to oscillate at or near a resonant frequency and is coupled to the mirror via mirror-gimbal connectors. A support structure can be coupled to a backside of the mirror and gimbal structures and can increase the stiffness of the mirror to help the mirror better resist dynamic deformation. To limit the added rotational moment of inertia, the support structure can be etched to form a matrix of cells (e.g., formed by a mesh of circumferential and radial ridges) such that up to approximately 90% of the support structure material forming the support structure is removed.

Abstract: A power semiconductor module includes an insulating substrate, a first conductive circuit pattern, a second conductive circuit pattern, a first semiconductor device, a second semiconductor device, a sealing member, and a first barrier layer. The sealing member seals the first semiconductor device, the second semiconductor device, the first conductive circuit pattern, and the second conductive circuit pattern. At least one of the first barrier layer and the sealing member includes a first stress relaxation portion. This configuration improves the reliability of the power semiconductor module.

Abstract: A method is provided for producing a printed circuit board including at least one conductor element, which extends between connection points in the printed circuit board. In order to increase the productivity of a known method for producing a printed circuit board including at least one conductor element, which extends between connection points in the printed circuit board, the method comprises the following steps: Step A: providing a mold having at least one receptacle for a conductor element; Step B: arranging a conductor element in the receptacle of the mold; Step C: connecting the conductor element arranged in the receptacle of the mold to an electrically conductive sheetlike element at positions of the intended connection points; Step D: embedding the conductor element, which is connected to the electrically conductive sheetlike element, into insulating material; and Step E: working out the connection points from the electrically conductive sheetlike element.

Abstract: Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to a second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.

Abstract: A semiconductor device includes a mounting substrate; a first wiring electrode and a second wiring electrode disposed on a main surface of a mounting substrate; an interposing member disposed between the first wiring electrode and the second wiring electrode; a semiconductor element flip-chip connected with the first wiring electrode and the second wiring electrode via a first electrical connection member and a second electrical connection member so as to at least partially overlap the interposing member in a top surface view; and a resin disposed in contact with the semiconductor element and the mounting substrate. The wettability of the interposing member to the resin is higher than that of the mounting substrate to the resin. The resin is disposed in contact with the semiconductor element and the interposing member.

Abstract: An object is to provide a technique capable of suppressing a corrosion of a first electrode and a second electrode. A semiconductor element includes a semiconductor substrate, an Al electrode, a polyimide member selectively disposed on the Al electrode, and an Ni electrode. The polyimide member includes a protruding part which protrudes in a plane direction of an upper surface of the Al electrode and which has a lower portion having contact with the Al electrode in a cross-sectional view, in at least part of a peripheral part of the polyimide member in a top view. The Ni electrode is disposed on the Al electrode and the protruding part.

Abstract: A semiconductor chip (2) includes a surface electrode (3). A conductive bonding member (8) includes first and second bonding members (8a,8b) provided on the surface electrode (3). A lead electrode (9) is bonded to a part of the surface electrode (3) via the first bonding member (8a) and has no contact with the second bonding member (8b). A signal wire (11) is bonded to the surface electrode (3). The second bonding member (8b) is arranged between the first bonding member (8a) and the signal wire (11). A thickness of the first bonding member (8a) is larger than a thickness of the second bonding member (8b).

Abstract: Techniques and structures for improving shielding of an integrated circuit package are provided. The integrated circuit package includes a die including a plurality of bump sites and a substrate connected to the die at the plurality of bump sites. The substrate includes at least one layer that implements one or more signal traces and a plurality of shield traces. Each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias.

Abstract: A heat radiation structure includes: a hexagonal boron nitride layer; and a turbostratic structure boron nitride layer provided on a first surface of the hexagonal boron nitride layer.

Abstract: A feedthrough assembly includes: a ferrule; an insulating structure; and a seal fixedly securing the insulating structure within the ferrule, the seal comprising a glass and single-phase particulate dispersed therein; wherein the glass includes: 25% to 40% B2O3; 0 to 25% CaO; 0 to 25% MgO; 0 to 25% SrO; 0 to 10% La2O3; 5% to 15% SiO2; and 10% to 20% Al2O3; wherein all percentages are mole percentages of the glass.

Abstract: A semiconductor device includes: a semiconductor chip; a case storing the semiconductor chip; a wire bonded to the semiconductor chip; a cover fixed inside the case and including a concave portion disposed above the semiconductor chip and the wire; and a sealing resin potted inside the case and sealing the semiconductor chip, the wire and the cover, wherein the sealing resin is not filled in the concave portion so that a cavity is provided.

Abstract: A power semiconductor device includes a casing, a first insulating circuit board, a second insulating circuit board, and a sealing material. The first insulating circuit board is disposed to be surrounded by the casing. The second insulating circuit board is surrounded by the casing and spaced from the first insulating circuit board so as to sandwich a semiconductor element between the first insulating circuit board and the second insulating circuit board. The sealing material fills a region surrounded by the casing. The first or second insulating circuit board is provided with a hole extending from one main surface to the other main surface opposite to one main surface. From at least a portion of an inner wall surface of the casing a protrusion extending to a region overlapping the first or second insulating circuit board in a plan view extends toward the region surrounded by the casing.

Abstract: According to one embodiment, a ceramic copper circuit board a ceramic substrate, a copper circuit board provided at one surface of the ceramic substrate. A ratio of a thickness of the copper circuit board to a thickness of the ceramic substrate is 1.25 or more. A number of grain boundaries is not less than 5 and not more than 250 along every 10-mm straight line drawn in a front surface of the copper circuit board.

Abstract: Methods, devices, and systems are provided for the delivery of agents (e.g., nucleic acids, proteins, organic molecules, organelles, antibodies or other ligands, 5 etc.) into live cells and/or the extraction of the same from said cells. In various embodiments the photothermal platforms and systems incorporating such photothermal platforms are provided that permit efficient, high-throughput cargo delivery into live cells.

Abstract: The present invention relates to a silica glass member including: a main body including a silica glass and having a bonding part for bonding to another member; and a bonding film which is provided on the bonding part, has a thickness of 0.2 ?m to 10 ?m, and includes Au and a glass formed through melting of glass frit, in which the bonding film is produced from Au powder having an average particle diameter of 3 ?m or less and glass frit having a softening point of 850° C. or lower, a process for producing a silica glass member, and a process for bonding a ceramic and a silica glass.

Abstract: A semiconductor apparatus includes: a substrate including a circuit pattern on an upper surface side and a metal plate on a lower surface side; a semiconductor device joined to the circuit pattern via a conductive component; a case located to surround the substrate; a sealing material sealing the semiconductor device and the substrate in a section surrounded by the case; and a bonding agent bonding the case and the metal plate on a side face of the substrate.

Abstract: The present disclosure relates to power modules. The teachings thereof may be embodied in a power unit and/or a drive unit for driving the power unit, along with methods for producing a power module. For example, a power module may include: a power unit including a heat sink; a power device disposed on the heat sink; an insulating layer covering the heat sink and the power device; and a drive unit for driving the power unit, the drive unit comprising a contact element corresponding to the contact area of the power unit. An underside of the power unit is defined by an underside of the heat sink. A top side of the power unit is defined by a contact area thermally and/or electrically coupled to the power device and a surface of the insulating layer surrounding the contact area. The contact element may be disposed abutting the contact area of the power unit for making electrical and/or thermal contact with the power device.

Abstract: Provided is a semiconductor device having high heat conductivity and high productivity. A semiconductor device includes an insulating substrate, a semiconductor element, a die-bond material, a joining material, and a cooler. The insulating substrate has an insulating ceramic, a first conductive plates disposed on one surface of the insulating ceramic, and a second conductive plate disposed on another surface of the insulating ceramic. The semiconductor element is disposed on the first conductive plate through the die-bond material. The die-bond material contains sintered metal. The semiconductor element has a bending strength degree of 700 MPa or more, and has a thickness of 0.05 mm or more and 0.1 mm or less. The cooler is joined to the second conductive plate through the joining material.

Abstract: A semiconductor device of the present invention includes a circuit layer formed of a conductive material, a semiconductor element mounted on a first surface of the circuit layer, and a ceramic substrate disposed on a second surface of the circuit layer, in which a Ag underlayer having a glass layer and a Ag layer laminated on the glass layer is formed on the first surface of the circuit layer, and the Ag layer of the Ag underlayer and the semiconductor element are directly joined together.

Abstract: A semiconductor package includes a support member having a first surface and a second surface, and having a through-hole, a first metal layer for shielding disposed on an internal sidewall of the through-hole and the first surface and the second surface of the support member, a connection member disposed on the first surface of the support member, and having a redistribution layer, a semiconductor chip disposed in the through-hole, an encapsulant sealing the semiconductor chip located in the through-hole, and covering the second surface of the support member, a second metal layer for shielding disposed on the encapsulant, and connected to the first metal layer for shielding by a connecting trench via passing through the encapsulant, and a reinforcing via disposed in a region, overlapping the trench via for connection, of the support member, and connected to the first metal layer for shielding.

Abstract: A power module substrate of the present invention includes a ceramic substrate and a circuit layer having a circuit pattern. In an interface between the circuit layer and the ceramic substrate, a Cu—Sn layer and a Ti-containing layer are laminated in this order from the ceramic substrate side. In a cross-sectional shape of an end portion of the circuit pattern of the circuit layer, an angle ? formed between a surface of the ceramic substrate and an end face of the Cu—Sn layer is set in a range equal to or greater than 80° and equal to or smaller than 100°, and a maximum protrusion length L of the Cu—Sn layer or the Ti-containing layer from an end face of the circuit layer is set in a range equal to or greater than 2?m and equal to or smaller than 15 ?m.

Abstract: A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.

Abstract: Provided is a heat-sink-attached power-module substrate, in which a metal layer and first layers are formed from aluminum sheets having a purity of 99.99 mass % or greater and a heat sink and second layers are formed from aluminum sheets having a purity lower than that of the metal layer and the first layers: when a thickness is t1 (mm), a joined-surface area is A1 (mm2), yield strength at 25° C. is ?11 (N/mm2), yield strength at 200° C. is ?12 (N/mm2) in the second layers; a thickness is t2 (mm), a joined-surface area is A2 (mm2), yield strength at 25° C. is ?21 (N/mm2), and yield strength at 200° C. is ?22 (N/mm2) in the heat sink.

Abstract: Power semiconductor packages described herein each include a substrate having two or more metal layers and one or more insulating layers for separating the metal layers. The substrate insulating layers are formed from a polymer material to reduce the CTE mismatch between the substrate metal layers and the substrate insulating layers.

Abstract: A sensor integrated circuit includes an energy storage device having a first terminal coupled to a functional circuit and a blocking circuit coupled between a power supply pin and the first terminal of the energy storage device. The blocking circuit permits the energy storage device to store energy from an external power supply coupled to the power pin. The first terminal of the energy storage device is inaccessible from outside of the sensor IC. Additional features of the sensor IC can include a high regulator, a low regulator, and a low power circuit.

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Abstract: Disclosed are a coating layer including pores for thermal insulation and a method of preparing the same. As such, the coating layer may secure low thermal conductivity, low volume heat capacity and improved durability, such that the coating layer can be applied to an internal combustion engine.

Abstract: A power semiconductor module includes one or more power semiconductor dies attached to a first main face of a substrate, a plastic housing attached to the substrate, which together with the substrate encloses the one or more power semiconductor dies, a plurality of power terminals attached to the first main face of the substrate at a first end, and extending through the plastic housing at a second end to provide a point of external electrical connection for the one or more power semiconductor dies, a potting compound embedding the one or more power semiconductor dies, the first main face of the substrate and at least part of the first end of the plurality of power terminals, and an insulative coating applied only to parts of the plurality of power terminals disposed inside the plastic housing and in contact with just air. A corresponding method of manufacture also is provided.

Abstract: Arrays of objects on a substrate having void-free underfill as well as methods and systems of forming the same include forming a void-free layer of underfill material between a substrate and an array of multiple objects positioned on the substrate. The void-free layer of underfill material is cured to form a protective cured underfill layer that provides structural support to connections between the objects and the substrate.

Abstract: Aspects of the disclosure are directed to a package including a substrate, die coupled to the substrate, wick deposited on the die, and an evaporation-condensation chamber having a hollowed bottom and two bottom lips, wherein the wick mates into the hollowed enclosure and substantially merges with the two bottom lips forming a sealed chamber. Other aspects are directed to a method of forming a package including coupling a die to a substrate, depositing a wick on the die, and mating the wick with an evaporation-condensation chamber having a hollowed enclosure and two bottom lips, wherein the mating attaches the wick into the hollowed enclosure and substantially merges the wick with the two bottom lips forming a sealed chamber. By directly depositing the wick over the die and integrating the wick with the encapsulation-condensation chamber, this integrated solution provides significant improvement in package thermal resistance especially for high-power and high-performance applications.

Abstract: The bonded body of the present invention includes: a ceramic member made of ceramics; and a Cu member which is made of Cu or a Cu alloy and bonded to the ceramic member through a Cu—P—Sn-based brazing filler material and a Ti material, wherein a Cu—Sn layer, which is positioned close to the ceramic member and in which Sn forms a solid solution with Cu, and a Ti layer which is positioned between the Cu member and the Cu—Sn layer, are formed at a bonded interface between the ceramic member and the Cu member, a first intermetallic compound layer made of Cu and Ti is formed between the Cu member and the Ti layer, and a second intermetallic compound layer containing P is formed between the Cu—Sn layer and the Ti layer.

Abstract: For a purpose of raising the breakdown voltage of a semiconductor device, the creepage distance and clearance between an electrode terminal and another metallic portion are preferably increased. A semiconductor device is provided, the semiconductor device including: a semiconductor element; a case portion that houses the semiconductor element; and an external terminal provided to a front surface of the case portion, wherein the front surface of the case portion has, formed thereon: a wall portion that protrudes from the front surface; and a hollow portion that is provided to a region surrounded by the wall portion and is depressed relative to the front surface, and the external terminal is arranged on a floor surface of the hollow portion.

Abstract: A printed wiring board includes a first circuit substrate having a first surface and a second surface on the opposite side, and a second circuit substrate having a third surface and a fourth surface on the opposite side such that the first circuit substrate is laminated on the third surface and that the first surface and the third surface are opposing each other. The second circuit substrate has a mounting area on the third surface and includes pads positioned to mount an electronic component in the mounting area and a connection wire structure connected to the pads, and the first circuit substrate includes through-hole conductors extending from the first surface to the second surface and connected to the pads through the connection wire structure and has an opening portion formed through the first circuit substrate such that the opening portion is exposing the pads formed in the mounting area.

Abstract: An image sensor package includes a ceramic substrate with a cavity disposed in the ceramic substrate. A glass layer is adhered to the ceramic substrate and encloses the cavity in the ceramic substrate. An image sensor is disposed in the cavity between the glass layer and the ceramic substrate to electrically isolate the image sensor. An image sensor processor is disposed in the cavity and electrically coupled to the image sensor to receive image data from the image sensor.

Abstract: The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

Abstract: The inventive concept provides MIT devices molded by clear compound epoxy and fire detecting devices including the MIT device. The fire detecting device is supplied with a power source from a power control device. The fire detecting device includes a MIT device including a MIT chip molded by a clear compound epoxy, a diode bridge circuit supplied with the power source from the power control device for providing a non-polar power source, a notice circuit supplied with the non-polar power source from the diode bridge circuit for warning of a fire alarm in response to a detecting signal from the MIT device, and a stabilization circuit for maintaining the detecting signal for a certain period.

Abstract: A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Abstract: A method for manufacturing an electronic device includes a through electrode forming step of forming a through electrode on an insulating base substrate; an electronic element mounting step of mounting an electronic element on one surface of the base substrate; a cover body placing step of bonding a cover body accommodating the electronic element; a conductive film forming step of forming a conductive film on the other surface of the base substrate and on an end face of the through electrode exposing on the other surface; an electrode pattern forming step of forming an electrode pattern on the end face of the through electrode and on the surface of the periphery of the end face while leaving the conductive film; and an external electrode forming step of forming an external electrode by accumulating an electroless plated film on the surface of the electrode pattern by an electroless plating method.

Abstract: A power module includes: an insulating layer; a leadframe (metal layer) disposed on the insulating layer; a semiconductor chip disposed on the leadframe; and a mold resin formed so as to cover the semiconductor chip, at least a part of the metal layer, and at least a part of the insulating layer, wherein the insulating layer includes a relatively-soft insulating layer disposed at a side of the leadframe and a relatively-hard insulating layer disposed at an opposite side of the leadframes. Accordingly, there can be provided the power module with improved cooling capability and improved reliability, and the fabrication method for such a power module.

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

Abstract: A semiconductor device includes: a conductive-patterned insulating substrate; conductive blocks fixed to conductive patterns of the conductive-patterned insulating substrate; a semiconductor chip fixed to each conductive block; a printed circuit board that has a conductive post fixed to the semiconductor chip; and a resin. The semiconductor device is configured such that the average volume of a conductive film per unit area of each conductive pattern around a section thereof, to which the corresponding conductive block is fixed, is reduced from the conductive block toward the outside.

Abstract: A storage battery equalization device is provided with: a battery pack including a plurality of storage battery modules; a plurality of equalization circuits corresponding to the respective storage battery modules, each including a DC/AC mutual converter circuit, a variable capacitor, and a transformer; external wirings interconnecting secondary windings of the transformers; voltage monitors each being connected across both electrodes of a corresponding storage battery module; and an equalization control unit.

Abstract: An antimony-free glass suitable for use in a frit for producing a hermetically sealed glass package is described. The hermetically sealed glass package, such as an OLED display device, is manufactured by providing a first glass substrate plate and a second glass substrate plate and depositing the antimony-free frit onto the first substrate plate. OLEDs may be deposited on the second glass substrate plate. An irradiation source (e.g., laser, infrared light) is then used to heat the frit which melts and forms a hermetic seal that connects the first glass substrate plate to the second glass substrate plate and also protects the OLEDs. The antimony-free glass has excellent aqueous durability, good flow, low glass transition temperature and low coefficient of thermal expansion.