Abstract: A sensor device and method of making same that includes a silicon substrate with opposing first and second surfaces, a sensor formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the sensor, and a plurality of cooling channels formed as first trenches extending into the second surface but not reaching the first surface. The cooling channels instead can be formed on one or more separate substrates that are attached to the silicon substrate for cooling the silicon substrate.

Abstract: A liquid ejecting head includes a piezoelectric element including a first electrode, a second electrode, and a piezoelectric layer between the first and the second electrodes. The piezoelectric layer includes a buffer layer disposed on the first electrode and containing Bi and an element selected from Al, Si, Cr, and Mn and a complex oxide layer disposed on the buffer layer and having a perovskite structure containing Bi, Fe, Ba, and Ti.

Abstract: There is provided a multilayer ceramic capacitor including a ceramic body having first and second main surfaces, third and fourth end surfaces, and fifth and sixth side surfaces; a plurality of first and second internal electrodes having a dielectric layer to be alternately exposed to the third and fourth end surfaces; and first and second external electrodes formed on the end surfaces and the main surfaces and electrically connected to the first and second internal electrodes, wherein when a width of the first or second external electrode is A and a length of a margin part of the ceramic body in the length direction is B, a ratio (A/B) of the width of the first or second external electrode to the length of the margin part of the ceramic body in the length direction is 3.3 or less (A/B?3.3).

Abstract: An electronic component built-in substrate, includes, a substrate having an opening portion, a first wiring layer formed in the substrate, an electronic component arranged in the opening portion, a first insulating layer formed on one face of the substrate and sealing the electronic component, a second insulating layer formed on other face of the substrate, a second wiring layer formed on the first insulating layer, and a third wiring layer formed on the second insulating layer. The first insulating layer is formed of an inner insulating layer covering the one face of the substrate and filling an inside of the opening portion, and an outer insulating layer formed on the inner insulating layer.

Abstract: Solid state light emitting diode packages can be provided including a ceramic material and a leadframe structure, on the ceramic material, the leadframe structure including a portion thereof that integrates the leadframe structure with the ceramic material.

Abstract: A high frequency module includes a ground mounting electrode connected to a ground terminal of a component, a first ground in-plane conductor in a multilayer substrate on a portion under the component and connected to the ground mounting electrode with a first ground interlayer connecting conductor, a signal mounting electrode connected to a signal terminal of the component, and a signal in-plane conductor provided in the multilayer substrate on a portion under the first ground in-plane conductor and connected to the specific signal mounting electrode with a signal interlayer connecting conductor. The first ground in-plane conductor is between the component and the signal in-plane conductor, and the signal interlayer connecting conductor is on an outer side portion of the first ground in-plane conductor when seen from above.

Abstract: A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Abstract: A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Abstract: A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing 98 wt % or more of one metallic element such as silver having a melting point of 400° C. or higher, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members.

Abstract: Semiconductor packages are provided that have a base plate with a matrix of pure silver or a silver alloy and reinforcement particles. The reinforcement particles can include high thermal conductivity, low CTE particles selected from the group consisting of diamond, cubic boron nitride (c-BN), silicon carbide (SiC), and any combinations thereof. In some embodiments, the base plate is entirely comprised of the composite. In other embodiments, the base plate has a core made of the composite. The core can include at least one outer layer on the core. The semiconductor package can include one or more dice or transistors on the base plate, an insulated frame on the base plate, and one or more leads on the insulated frame.

Abstract: A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing copper and a low-melting-point metal such as tin, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members.

Abstract: A semiconductor package includes a wiring board; a semiconductor chip mounted on the wiring board; and a radiation plate mounted on the semiconductor chip, including an insulating member including a resin that is the same as a resin included in the wiring board, as a main constituent, a first metal foil formed on a first surface of the insulating member, a second metal foil formed on a second surface of the insulating member, the second surface being an opposite to the first surface, the radiation plate being provided with a through hole that penetrates the first metal foil, the insulating member and the second metal foil, and a metal layer formed to cover the inner surface of the through hole to thermally connect the first metal foil and the second metal foil by penetrating the insulating member in a thickness direction.

Abstract: A semiconductor arrangement includes a ceramic mount and at least one semiconductor component fixed-to the ceramic mount. The ceramic mount includes a first section, and the first section is electrically conductive.

Abstract: A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %.

Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.

Abstract: A method of manufacturing a semiconductor device comprises a mounting step of mounting a semiconductor element having an Au—Sn layer on a substrate, wherein the mounting step includes a paste supplying step of supplying an Ag paste having an Ag nanoparticle onto the substrate, a device mounting step of mounting a side of the Au—Sn layer of the semiconductor element on the Ag paste, and a bonding step of alloying the Au—Sn layer and the Ag paste to bond the semiconductor element to the substrate, wherein the Au—Sn layer has a content rate of Au of 50 at % to 85 at %.

Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.

Abstract: An antimony-free glass comprising TeO2 and/or Bi2O3 suitable for use in a frit for producing a hermetically sealed glass package is described. The hermetically sealed glass package, such as an OLED display device, is manufactured by providing a first glass substrate plate and a second glass substrate plate and depositing the antimony-free frit onto the first substrate plate. OLEDs may be deposited on the second glass substrate plate. An irradiation source (e.g., laser, infrared light) is then used to heat the frit which melts and forms a hermetic seal that connects the first glass substrate plate to the second glass substrate plate and also protects the OLEDs disposed therein. The antimony-free glass has excellent aqueous durability, good flow, and low glass transition temperature.

Abstract: A multichip module comprising: a base substrate; a wiring board disposed on the base substrate and having a wiring pattern; an adhesive layer configured to bond the base substrate to the wiring board while maintaining an electrical connection between the base substrate and the wiring board; and a plurality of chips connected to a surface of the wiring board, the surface being opposite the adhesive layer, wherein, assuming that ? is a coefficient of thermal expansion of the wiring board, ? is a coefficient of thermal expansion of the base substrate, and ? is a coefficient of thermal expansion of the adhesive layer, the relationship ?<?<? is satisfied.

Abstract: A package structure is provided, which includes a dielectric layer having opposing first and second surfaces, and through holes penetrating the surfaces; a strengthening layer formed on the first surface; a circuit layer formed on the second surface, and having wire bonding pads formed thereon and exposed from the through holes, and ball pads electrically connected to the wire bonding pads; a first solder mask layer formed on the first surface and the strengthening layer, and having first apertures formed therethrough for exposing the wire bonding pads; a second solder mask layer formed on the second surface and the circuit layer, and having second apertures formed therethrough for exposing the ball pads; and a semiconductor chip disposed on the first solder mask layer and electrically connected via conductive wires to the wire bonding pads exposed from the through holes. The strengthening layer ensures the steadiness of the chip to be mounted thereon without position shifting.

Abstract: An electric device with an insulating substrate consisting of an insulating layer and at least one metallization on a surface side of the insulating layer, the metallization being structured and having an electric component on the metallization. The metallization has a layer thickness that is stepped and is greater in an area adjoining the component.

Abstract: There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

Abstract: A method for fabricating an electronic device package having a column grid array is disclosed. A column grid array package includes a substrate, an integrated circuit located on a first side of the substrate, and a set of solder columns located on a second side of the substrate. The column grid array package also includes multiple two-tab electronic devices located on the second side of the substrate. The heights of the two-tab electronic devices are substantially identical to the heights of the solder columns.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A circuit board is provided with a plurality of arms and a heat radiation plate. The insulating substrate of the each of the arms includes: a passive element region to which a passive element is connected; an active element region to which an active element is connected; and a wiring region on which wiring lines of the element group are laid. In the each of the arms, the passive element region, the active element region and the wiring region align in a lengthwise direction of the insulating substrate, and the passive element region and the wiring region are arranged on both sides of the active element region which is located centrally.

Abstract: A semiconductor device and method is disclosed. One embodiment provides a method comprising placing a first semiconductor chip on a carrier. After placing the first semiconductor chip on the carrier, an electrically insulating layer is deposited on the carrier. A second semiconductor chip is placed on the electrically insulating layer.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device and a package substrate core having an upper and a lower surface. At least one pair of metal layers coats the upper and lower surfaces of the package substrate core. One pair of solder mask layers coats the outer metal layers of the at least one pair of metal layers. A plurality of vias is formed across the package substrate core and the at least one pair of metal layers. Advantageously, the plurality of vias is substantially distributed according to a homogeneous pattern in an area that is to be covered by the damage-sensitive device. A method for the production of such semiconductor package substrate is also described.

Abstract: A vibrating device has a package having an accommodating space in the interior thereof and a gyro element and an IC chip accommodated in the accommodating space. The package has a plate-like bottom plate having an IC chip mounting area and a vibrating element mounting area. The IC chip mounting area includes an IC chip mounting surface on which the IC chip is mounted. The vibrating element mounting area is arranged in parallel with the IC chip mounting area and includes a vibrating element mounting surface on which the gyro element is mounted. The thickness of the IC chip mounting area is smaller than that of the vibrating element mounting area. The IC chip mounting surface is located closer to a bottom side than the vibrating element mounting surface.

Abstract: A wafer-scale assembly circuit including a plurality of metal interconnect layers, where each metal layer includes patterned metal portions and where at least some of the patterned metal portions are RF signal lines. The circuit further includes at least one benzocyclobutene layer provided between two metal interconnect layers that includes at least one trench via formed around a perimeter of the benzocyclobutene layer at a circuit sealing ring, where the trench via provides a hermetic seal at the sealing ring. The benzocyclobutene layer also includes a plurality of stabilizing post vias formed through the benzocyclobutene layer adjacent to the trench via proximate to the sealing ring and extending around the perimeter of the benzocyclobutene layer, where the stabilizing vias operate to prevent the benzocyclobutene layer from shrinking in size.

Abstract: Three dimensional Panel-Level Packaging (3D-PLP) fabrication techniques for mass-production of small, simple three dimensional electronic component packages or units such as a DC-DC Converters are described where each package or unit consists of at least an active semiconductor die and a passive, two-terminal electrical circuit element (capacitor inductor and/or resistor).

Abstract: A power semiconductor module is provided in which power semiconductor chips with an aluminum-based chip metallization and power semiconductor chips with a copper-based chip metallization are included in the same module, and operated at different barrier-layer temperatures during use.

Abstract: Various embodiments include apparatus and methods having circuitry to test continuity of conductive paths coupled to dice arranged in a stack. In at least one of these embodiments, a method includes electrically coupling each of the conductive paths to at least one of a first supply node and a second supply node. One of the conductive paths includes conductive material inside a via that can extend at least partly through a die among the dice in the stack. The method also includes receiving signals from the conductive paths, and determining continuity of the conductive paths based on the signals without using a boundary scan.

Abstract: A circuit board and a semiconductor module with high endurance against thermal cycles, and which is hard to be broken under thermal cycles, even if thick metal circuit board and thick metal heat sink are used, corresponding to high power operation of a semiconductor chip are provided. This circuit board includes, an insulating-ceramic substrate, a metal circuit plate bonded to one face of the insulating-ceramic substrate, a metal heat sink bonded to another face of the insulating-ceramic substrate, wherein (t12?t22)/tc2/K<1.5, where, a thickness of the insulating ceramics substrate is tc, a thickness of the metal circuit plate is t1, a thickness of the metal heat sink is t2, and an internal fracture toughness value of the insulating ceramics substrate is K.

Abstract: A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %.

Abstract: After a semiconductor chip is cut out, an In-10 atom % Ag pellet is placed on a metal film. Next, an epoxy sheet on a stiffener is stuck to a ceramic substrate. At this time, the In alloy pellet is sandwiched between a central protrusion portion and the metal film. Then, an In alloy film is formed from the In alloy pellet by heating, melting, and then cooling the In alloy pellet. As a result, the semiconductor chip and a heat spreader are bonded via the metal film and the In alloy film.

Abstract: A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased.

Abstract: A semiconductor device includes a substrate including a first metal layer, a first semiconductor chip having sidewalls, and a first solder layer contacting the first semiconductor chip and the first metal layer. The first metal layer includes a groove extending around sidewalls of the first semiconductor chip. The groove is at least partly filled with excess solder from the first solder layer.

Abstract: The semiconductor device comprises a semiconductor chip and a printed wiring board having a recess in which the semiconductor chip is housed face-down, wherein the printed wiring board comprises multiple wiring layers below a circuit surface of the semiconductor chip on which connection terminals are formed, and the multiple wiring layers include a first wiring layer for forming signal wires, a second wiring layer for forming a ground plane, and a third wiring layer for forming power wires and power BGA and ground BGA pads in sequence from the circuit surface.

Abstract: An electret accelerometer is provided in which a diaphragm, an electret, a back plate and an electronic circuit are placed in a casing and the casing is sealed to isolate the diaphragm from external acoustic signals.

Abstract: To improve manufacture of an electronic circuit, the electronic circuit is composed of modules of sub-circuits arranged on a common substrate, such as a cooling body, and that are electrically interconnected by a planar electrical contact element.

Abstract: Disclosed is a semiconductor device wherein the adhesion of resin to a substrate is improved at a low cost. A semiconductor element and one or two substrates opposing one or both of the surfaces of the semiconductor element are sealed by a resin, a resin bonding coat which is formed by spraying a metal powder by a cold spray method is formed on one or both of the substrates, and recess portions which are widened from a film surface in a depth direction are formed on the resin bonding coat.

Abstract: In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit board with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.

Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.

Abstract: In inlets used for ID tags and the like, a defective connection between an integrated circuit part and an antenna is suppressed by improvement of tolerance for a bending or a pressing pressure. The integrated circuit part includes a semiconductor chip and a multilayer substrate having a concave portion. The semiconductor chip is mounted on the bottom of the concave portion. The multilayer substrate includes a connection electrode at the top surface and a connection electrode connected to the semiconductor chip on the bottom of the concave portion. The connection electrode on the bottom of the concave portion is connected to the connection electrode at the top surface by a penetration electrode inside a multilayer substrate. By such a configuration, the semiconductor chip is connected to the antenna.

Abstract: A light-emitting diode (LED) structure with an improved heat transfer path with a lower thermal resistance than conventional LED lamps is provided. For some embodiments, a surface-mountable light-emitting diode structure is provided having an active layer deposited on a substrate directly bonded to a metal plate that is substantially exposed for low thermal resistance by positioning the metal plate at the bottom of the light-emitting diode structure. This metal plate may then be soldered to a printed circuit board (PCB) that includes a heat sink. For some embodiments of the invention, the metal plate is thermally and electrically conductively coupled through several heat conduction layers to a large heat sink that may be included in the structure.

Abstract: The invention relates to a novel process for producing a metal ceramic substrate, especially a copper-ceramic substrate, in which at least one metal foil at a time is applied to the surface sides of a ceramic layer or a ceramic substrate using a high temperature bonding process and the metal foil is structured on at least one surface side for forming conductive tracks, contact surfaces, and the like.

Abstract: Disclosed are low profile discrete electronic component structures that are suitable for placement and use in a vertical interconnection mode either within an electronic interconnection substrate, between interconnection substrate and electronic component or within an IC package.

Abstract: A fully reflective and highly thermoconductive electronic module includes a metal bottom layer, a transparent ceramic layer and a patterned metal wiring layer. The metal bottom layer has a lower reflective surface. The transparent ceramic layer has an upper surface and a lower surface. The lower surface of the transparent ceramic layer is bonded to the lower reflective surface of the metal bottom layer. The metal wiring layer is bonded to the upper surface of the transparent ceramic layer. The lower reflective surface reflects a first light ray, transmitting through the transparent ceramic layer, to the upper surface of the transparent ceramic layer. A method of manufacturing the fully reflective and highly thermoconductive electronic module is also disclosed.

Abstract: Provided are a process for producing a highly reliable ceramic sheet with stable quality by reducing voids, and a ceramic substrate using the sheet. A highly reliable ceramic sheet with stable quality is obtained by using hydroxypropylmethyl cellulose as an organic binder, kneading a powder material, preferably, with a twin screw extruder, and then forming a sheet by means of a single screw extruder equipped with a sheet die, and the sheet is suitably used for a ceramic substrate and a ceramic circuit board.

Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.