Cap Or Lid Patents (Class 257/704)
  • Patent number: 10381287
    Abstract: This application discloses an device disposed on a substrate, and a heat sink disposed on the substrate over the device. The heat sink disposed on the substrate forms a cavity to hold a fluid between the heat sink and the device. The fluid can absorb heat emitted by the device and transfer at least a portion of the absorbed heat to the heat sink. A gasket can be disposed between and in contact with the substrate and the heat sink. The gasket can prevent the fluid from exiting the cavity formed by the heat sink disposed on the substrate. The heat sink can have an opening to the cavity, which can be detachably sealed by a plug. The plug can reduce a pressure within the cavity or allow removal of gas bubbles in the fluid held in the cavity.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: August 13, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Spencer Saunders, Terry Goode
  • Patent number: 10373883
    Abstract: A semiconductor package device comprises a substrate, an electronic component and a protection layer. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a first opening penetrating the substrate. The electronic component is disposed on the first surface of the substrate. The protection layer is disposed on the second surface of the substrate. The protection layer has a first portion adjacent to the first opening and a second portion disposed farther away from the first opening than is the first portion of the protection layer. The first portion of the protection layer has a surface facing away from the second surface of the substrate. The second portion of the protection layer has a surface facing away from the second surface of the substrate.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 6, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-An Fang, Chi Sheng Tseng
  • Patent number: 10347572
    Abstract: A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first side of the package component, a dielectric material formed over the first side of the package component, wherein four corners of the top surface of the package component are free from the dielectric material and a top package bonded on the first side of the package component, wherein the semiconductor die is located between the top package and the package component.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 10334370
    Abstract: Apparatus, systems and methods for reducing feedback in a hearing aid that includes a transducer configured to detect sound, a sound processor configured to process signals from the transducer, a receiver configured to receive signals outputted from the sound processor, and an acoustic feedback reduction system. The acoustic feedback reduction system is configured to provide signals to the sound processor to produce a null targeting signal steerable toward a source of feedback.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: June 25, 2019
    Assignee: Eargo, Inc.
    Inventors: Bret Herscher, Takahiro Unno, Daniel Shen, Florent Michel, Raphael Michel
  • Patent number: 10331182
    Abstract: An example heat exchanger may comprise a base to thermally conductively engage with a computing component, a plurality of fins that may extend from the base on the same side as the computing component, and an auxiliary fluid channel defined by the plurality of fins. The plurality of fins may transfer thermal energy from the computing component to a fluid medium surrounding the plurality of fins. The auxiliary fluid channel may facilitate the transfer of thermal energy from an electronic component, other than the computing component, disposed within the auxiliary fluid channel to a fluid medium flowing through the auxiliary fluid channel.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: June 25, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Kevin B. Leigh, George D. Megason, John Norton
  • Patent number: 10319666
    Abstract: A process of forming a thermal interface material structure includes forming an assembly that includes a thermal interface material disposed between a first mating surface and a second mating surface. The first mating surface is associated with a module lid, and the second mating surface is associated with a heat sink. Protruding surface features are incorporated onto the first mating surface or the second mating surface. The process also includes compressing the assembly to form a thermal interface material structure. The thermal interface material structure includes the thermal interface material disposed within an interface defined by the first mating surface and the second mating surface. The protruding surface features protrude from the first mating surface or the second mating surface into selected areas of the interface to limit relative movement of the mating surfaces into the selected areas during thermal cycling to reduce thermal interface material migration out of the interface.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric J. Campbell, Sarah K. Czaplewski, Elin F. Labreck, Jennifer I. Porto
  • Patent number: 10276957
    Abstract: An attachment structure for use with a standalone control unit. The control unit includes a threaded insert located in an enclosed cavity which allows screws to be used for grounding of an EMI/RFI board, along with creating a sealed, enclosed pocket. The attachment structure allows for grounding of the PCB to the sheet metal base plate without creating a leak path to the outside of the control unit. This ground approach encapsulates the screw to prevent the formation of a leak path.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: April 30, 2019
    Assignee: Continental Automotive Systems, Inc.
    Inventors: Wayne J Wright, Donald J Zito, Vladimir Mulina
  • Patent number: 10199562
    Abstract: A method of fabricating an electronic device, the method including: arranging a device chip with no bump located on a lower surface of the device chip on a mounting substrate including a bump located on an upper surface of the mounting substrate; and bonding a pad located on the lower surface of the device chip and the bump by applying an ultrasonic wave to the device chip from an upper surface of the device chip.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: February 5, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Shinji Yamamoto, Jumpei Konno, Takashi Miyagawa
  • Patent number: 10178786
    Abstract: A circuit package for electrically connecting a plurality of modules. The circuit package having a first and second mounting plate, each including a plurality of module connectors configured to receive and form electrical connections with the plurality of modules. The circuit package also having a first and second sidewall mounted to the first and second mounting plates. The first sidewall including a plurality of sidewall fins extending outward from the first sidewall so that the plurality of sidewall fins are positioned between the first and second mounting plates and at least partially interleave with the plurality of modules.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: January 8, 2019
    Assignee: Honeywell International Inc.
    Inventors: James L. Tucker, Romney R. Katti
  • Patent number: 10175073
    Abstract: A differential pressure detection element includes: a support portion having an opening; a cantilever portion supported in a cantilever manner by the support portion so as to protrude into the opening; a diffusion layer including a piezoresistive portion provided at a fixed end of the cantilever portion; a pair of wiring portions electrically connected to the diffusion layer; a first insulating layer covering the diffusion layer; and a second insulating layer laid on the first insulating layer. A linear expansion coefficient of the first insulating layer is smaller than a linear expansion coefficient of a material of which the cantilever portion is composed, and a linear expansion coefficient of the second insulating layer is larger than the linear expansion coefficient of the first insulating layer.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: January 8, 2019
    Assignee: FUJIKURA LTD.
    Inventors: Hayato Arai, Tatsuya Shioiri, Naoki Takayama
  • Patent number: 10163755
    Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Xiao Li, Steven K. Groothuis, Jian Li, Jaspreet S. Gandhi, James M. Derderian, David R. Hembree
  • Patent number: 10157863
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a die structure formed over the substrate. The semiconductor device structure also includes a lid structure formed over the die structure. The lid structure includes a top portion with a top length and a bottom portion with a bottom length, and the top length is greater than the bottom length. The semiconductor device structure also includes a package layer formed between the lid structure and the die structure, and a sidewall of the bottom portion of the lid structure is not aligned with a sidewall of the die structure.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Chi-Yang Yu, Yu-Chih Liu
  • Patent number: 10134690
    Abstract: Embodiments herein may relate to a package with one or more layers. A silicon die may be coupled with the one or more layers via an adhesive. A package stiffener may also be coupled with the adhesive adjacent to the die. A magnetic thin film may be coupled with the package stiffener. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Hao-Han Hsu, Ying Ern Ho, Jaejin Lee
  • Patent number: 10128230
    Abstract: An RC-IGBT has a chip area of the semiconductor chip larger than that of a semiconductor chip including an IGBT section but not including an FWD section, as it is provided with the FWD section. It is demanded to reduce the chip area of the RC-IGBT semiconductor chip. Provided is a semiconductor device including: a transistor section including a plurality of transistors; a free wheeling diode section being at least opposite to one side of the transistor section and provided outside the transistor section, when the transistor section is seen from a top view; and a gate runner section and a gate pad section provided to contact the transistor section and not surrounding an entire periphery of the transistor section, when the transistor section is seen from a top view.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tohru Shirakawa, Hiroyuki Tanaka
  • Patent number: 10121720
    Abstract: A semiconductor device, such as a semiconductor power device, includes: a semiconductor die having a semiconductor die front surface, a package formed onto the semiconductor die, the package having a portion facing the front surface of the semiconductor die, and a thermally-conductive layer including graphene over the front portion of the package facing the front surface of the semiconductor die.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: November 6, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10099919
    Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chih Liang, Chia-Hua Chu, Te-Hao Lee, Jiou-Kang Lee, Chung-Hsien Lin
  • Patent number: 10096584
    Abstract: In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: October 9, 2018
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Guido Boenig, Irmgard Escher-Poeppel, Edward Fuergut, Martin Gruber, Thorsten Meyer
  • Patent number: 10091899
    Abstract: The embodiments disclose a method for creating a digital device protective artwork case conforming to digital device shapes and sizes and includes electronically stitched artwork designs that seamlessly wraparound the digital device protective artwork case, a shock absorbing flexible bumper core with flexible buttons to operate digital device buttons, a flexible back, a hard outer shell back, a hard outer shell portable charger external battery with blinking LED eyes battery level indicators, a tempered glass front face, a digital device protective artwork case website including at least one processor, at least one digital electronic stitching processor, at least one database, at least one communication device, an internet connection, and at least one manufacturing data interface to transfer user selections of protective artwork case styles and stock artwork designs to at least to at least one manufacturing device including an electronically stitched image application device and a mold material depositing dev
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: October 2, 2018
    Inventor: Eli Altaras
  • Patent number: 10078683
    Abstract: Embodiments of the present invention are directed to a system and method for a central intelligence system for managing, analyzing, and maintaining large scale, connected information systems. The centralized information system may receive data from servers, databases, mainframes, processes, and other technological assets. A user is able to use the centralized information system to run analysis on the data associated with the connected systems, including: historical analysis, real-time analysis, and predictive modeling. The system can monitor the data and automatically correct identified errors without the need of human intervention. The centralized information system can also generate risk management profiles and automatically modify data to conform to the risk management profiles.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: September 18, 2018
    Assignee: JPMorgan Chase Bank, N.A.
    Inventor: Prithviraj Sensharma
  • Patent number: 10054609
    Abstract: A method for manufacturing a semiconductor device includes: preparing a first substrate; forming a metal film having a Ti layer as the most outermost surface on one surface of the first substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a first pad portion; preparing a second substrate; forming on one surface of the second substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a second pad portion; vacuum annealing the first substrate and the second substrate to remove an oxide film formed on the Ti layer in the first pad portion and the second pad portion; and bonding the first pad portion and the second pad portion together.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: August 21, 2018
    Assignee: DENSO CORPORATION
    Inventors: Toshihiko Takahata, Eiichi Taketani
  • Patent number: 10056268
    Abstract: An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board. The semiconductor chip is electrically connected to the top surface. The lid is attached to the top surface enclosing semiconductor chip and includes a perimeter recess. The lid-ring is juxtaposed within the perimeter recess. The lid-ring exerts a reverse bending moment upon the lid to limit warpage of the electronic package.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventor: Shidong Li
  • Patent number: 10043730
    Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: August 7, 2018
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Tien-Yu Lee, Ferdinand F. Fernandez, Suresh Ramalingam, Ivor G. Barber, Inderjit Singh, Nael Zohni
  • Patent number: 10035388
    Abstract: The present invention provides a MEMS and a sensor having the MEMS which can be formed without a process of etching a sacrifice layer. The MEMS and the sensor having the MEMS are formed by forming an interspace using a spacer layer. In the MEMS in which an interspace is formed using a spacer layer, a process for forming a sacrifice layer and an etching process of the sacrifice layer are not required. As a result, there is no restriction on the etching time, and thus the yield can be improved.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: July 31, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mayumi Yamaguchi, Konami Izumi, Fuminori Tateishi
  • Patent number: 9991243
    Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Nitin Deshpande, Bassam M. Ziadeh, Yoshihiro Tomita
  • Patent number: 9980038
    Abstract: A surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a cover, and the MEMS microphone die is substrate-mounted and acoustically coupled to an acoustic port provided in the surface mount package. The substrate and the cover are joined together to form the MEMS microphone, and the substrate and cover cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: May 22, 2018
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9969611
    Abstract: An improved microelectromechanical device includes an upper plate, a lower plate, and a spacing structure. The upper plate includes a first surface and an opposite second surface. The lower plate is spaced from the upper plate. The lower plate includes a third surface that faces the first surface of the upper plate and a fourth surface that is opposite of the third surface. The lower plate also includes a series of structures disposed with the third surface of the lower plate. The spacing structure is coupled to the upper and lower plate. The spacing structure includes a base portion that is sealed to the first surface of the upper plate and the third surface of the lower plate. The spacing structure further includes a protrusion that extends from the base portion between the upper and lower plates.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: May 15, 2018
    Assignee: Eagle Technology, LLC
    Inventors: Arlynn W. Smith, Dan Chilcott
  • Patent number: 9935058
    Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 9922901
    Abstract: A thermally conductive sheet including a sheet body that is a cured product of a thermally conductive resin composition including a binder resin and carbon fibers covered with insulating coating films, wherein the carbon fibers exposed on a surface of the sheet body are not covered with the insulating coating films and are covered with a component of the binder resin.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: March 20, 2018
    Assignee: DEXERIALS CORPORATION
    Inventors: Keisuke Aramaki, Hiroki Kanaya, Masahide Daimon
  • Patent number: 9916991
    Abstract: A semiconductor device is provided with a substrate made of a semiconductor material, an interconnect layer, at least one electronic element, and a sealing resin. The substrate has a main surface and a pair of lateral surfaces that are orthogonal to the main surface and face in opposite directions to each other. A recessed portion that is recessed from the main surface and has an opening portion that opens on at least one of the pair of lateral surfaces is formed in the substrate. The interconnect layer is formed on the substrate. The electronic element is an orientation sensor, for example, and is accommodated in the recessed portion of the substrate. The sealing resin covers the electronic element.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: March 13, 2018
    Assignee: ROHM CO. LTD.
    Inventors: Yuichi Nakao, Yasuhiro Fuwa
  • Patent number: 9899238
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
  • Patent number: 9892990
    Abstract: Semiconductor package lid thermal interface material standoffs are disclosed and may include a substrate, a semiconductor die bonded to the substrate, a package lid bonded to the substrate and the semiconductor die thermal interface material in contact the semiconductor die, and standoffs that define a distance between the package lid and the substrate. The package lid may comprise thermal conducting material. The standoff may be within a portion of the thermal interface material. The package lid may provide a hermetic seal with the substrate. A passive device may be bonded to the substrate and covered by the package lid. A standoffs may also be formed on portions of the lid that are not in contact with the substrate. The standoff may be formed on four edges of the package lid. The standoff may comprise structures pressed into the lid.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: February 13, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jesse E. Galloway, Paul Mescher
  • Patent number: 9883270
    Abstract: A microphone includes a base and a microelectromechanical system (MEMS) die mounted to the base. The microphone also includes an integrated circuit fixed to the base. The microphone further includes a lid mounted to the base that encloses the MEMS die and the integrated circuit within a cavity formed by the base and the lid. The lid has an indented portion extending into but not fully through the lid.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: January 30, 2018
    Assignee: Knowles Electronics, LLC
    Inventor: Tony K. Lim
  • Patent number: 9847304
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a bottom surface and a side surface extending from the bottom surface. The side surface can be oriented at a non-perpendicular angle relative to the bottom surface. In another example, an electronic device package can include a top planar surface having a first area, a bottom planar surface having a second area, and a side surface extending between the top surface and the bottom surface. The second area can be larger than the first area. In yet another example, an electronic device package can include a substrate defining a plane, an electronic component disposed on the substrate, and a layer of material disposed about a lateral side of the electronic component. The layer of material can be oriented at an angle of less than 90 degrees relative to the plane.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Eric Li, Joshua Heppner, Rajendra Dias, Mitul Modi
  • Patent number: 9837389
    Abstract: A display device including a plurality of semiconductor light emitting devices, each corresponding semiconductor light emitting device having a first conductive electrode, a second conductive electrode and a light-emitting surface configured to emit light; a first wiring line electrically connected to the first conductive electrode; and a second wiring line disposed to cross the first conductive electrode, and be electrically connected to the second conductive electrode. Further, the second wiring line is formed to surround a periphery of the light-emitting surface of the semiconductor light emitting devices to reflect light emitted by the light emitting devices toward a front surface of the display device.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: December 5, 2017
    Assignee: LG ELECTRONICS INC.
    Inventor: Hwanjoon Choi
  • Patent number: 9818698
    Abstract: An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Der-Chyang Yeh
  • Patent number: 9818637
    Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: November 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Mukta G. Farooq, John A. Fitzsimmons, Mark D. Jaffe, Randy L. Wolf
  • Patent number: 9776857
    Abstract: A method of fabricating a micro electro mechanical system (MEMS) structure includes providing a first substrate structure including a bonding pad structure. The bonding pad structure has at least one recess therein. A second substrate structure is provided and bonded with the bonding pad structure of the first substrate structure.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Ying Chien, Ching-Hou Su, Chyi-Tsong Ni, Yi Hsun Chiu
  • Patent number: 9754899
    Abstract: A semiconductor structure and a method of fabricating the same. The semiconductor structure comprises: a layer element, one or more supporting elements disposed on a first surface of the layer element, and one or more anchoring elements disposed within the layer element and connected to the one or more supporting elements to couple the one or more supporting elements to the layer element to strengthen the layer element.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: September 5, 2017
    Assignee: Advanpack Solutions PTE LTD
    Inventors: Shoa Siong Raymond Lim, Hwee Seng Jimmy Chew
  • Patent number: 9741640
    Abstract: A light-emitting element according to the present invention includes a semiconductor light-emitting element having a front surface and a rear surface so that light is extracted from the rear surface, and having a first n-side electrode and a first p-side electrode on the front surface, and a support element having a conductive substrate having a front surface and a rear surface as well as a second n-side electrode and a second p-side electrode formed on the front surface of the conductive substrate, the first n-side electrode and the second n-side electrode, and the first p-side electrode and the second p-side electrode are so bonded to one another respectively that the semiconductor light-emitting element is supported by the support element in a facedown posture downwardly directing the front surface, and the support element has an n-side external electrode and a p-side external electrode formed on the rear surface of the conductive substrate, a conductive via passing through the conductive substrate from th
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: August 22, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto
  • Patent number: 9728868
    Abstract: The present invention is directed to a liquid and solid phase power connect for packaging of an electrical device using a using a phase changing metal. The phase changing metal transitions back and forth between a liquid phase and a solid phase while constantly maintaining connection to the electrical device. The packaging uses a substrate, a restraining housing, and a lid to encase an electrical contact on the electrical device and restrain the phase changing metal. In one embodiment, the entire electrical device is encased and a voltage isolator is utilized to limit the contact areas between the phase changing metal and the electrical device. A method for relieving contact stress by transitioning the phase changing metal from a solid to a liquid is also taught.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: August 8, 2017
    Assignee: Cree Fayetteville, Inc.
    Inventor: Alexander Lostetter
  • Patent number: 9711425
    Abstract: A sensing module is provided. The sensing module includes a sensing device. The sensing device includes a first substrate having a first surface and a second surface opposite thereto. The sensing device also includes a sensing region adjacent to the first surface and a conducting pad on the first surface. The sensing device further includes a redistribution layer on the second surface and electrically connected to the conducting pad. The sensing module also includes a second substrate and a cover plate bonded to the sensing device so that the sensing device is between the second substrate and the cover plate. The conducting pad is electrically connected to the second substrate through the redistribution layer. The sensing module further includes an encapsulating layer filled between the second substrate and the cover plate to surround the sensing device.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: July 18, 2017
    Assignee: XINTEC INC.
    Inventors: Shu-Ming Chang, Po-Chang Huang, Tsang-Yu Liu, Yu-Lung Huang, Chi-Chang Liao
  • Patent number: 9679784
    Abstract: A wafer-level packaged optical subassembly includes: a substrate element, the substrate element including a top layer and a base layer being bonded with the top layer; a top window cover being bonded with the top layer of the substrate element; and a plurality of active optoelectronic elements disposed within the substrate element. At least one primary cavity is defined in the substrate element by the top layer and the base layer, and configured for accommodating the active optoelectronic elements. A plurality of peripheral cavities are defined around the at least one primary cavity as alignment features for external opto-mechanical parts.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 13, 2017
    Assignee: SAE Magnetics (H.K.) Ltd.
    Inventors: Dennis Tak Kit Tong, Vincent Wai Hung
  • Patent number: 9653679
    Abstract: A method of making a magnetoresistive structure is disclosed. The method includes forming a pillar structure including a magnetic tunnel junction on a substrate that includes a first electrode, depositing a stressed layer onto a pillar structure sidewall, and depositing a second electrode above the magnetic tunnel junction.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Gen P. Lauer, Adam M. Pyzyna
  • Patent number: 9653376
    Abstract: A heat dissipation package structure includes a substrate, a chip disposed on the substrate and a heat dissipation sheet. The heat dissipation sheet comprises a covering portion disposed on a back surface of the chip, a first lateral covering portion disposed on a first lateral surface of the chip and a first conducting portion disposed on the substrate. The back surface comprises a first width, the covering portion comprises a second width, the chip comprises a thickness, and there is an interval between the chip and the substrate. The second width is not larger than summation of the first width, double the interval and double the thickness for making the chip disposed between the heat dissipation sheet and the substrate is not within a completely sealed space so as to prevent the heat dissipation sheet from deformation and separation from the chip or the substrate cause of air expansion.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 16, 2017
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventor: Chin-Tang Hsieh
  • Patent number: 9637376
    Abstract: An integrated circuit packaging structure comprises at least one Micro Electrical Mechanical Systems (MEMS) gyroscope die mounted directly on a multi-layer flexible substrate having at least one metal layer and wire-bonded to the flexible substrate and a lid or die coating protecting the MEMS die and wire bonds.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: May 2, 2017
    Assignee: Compass Technology Company Limited
    Inventors: Kelvin Po Leung Pun, Chee Wah Cheung
  • Patent number: 9637378
    Abstract: The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by increasing an area in which a getter layer is deposited, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having one or more residual gases. A cavity is formed within a top surface of the substrate. The cavity has a bottom surface and sidewalls extending from the bottom surface to the top surface. A getter layer, which absorbs the one or more residual gases, is deposited over the substrate at a position extending from the bottom surface of the cavity to a location on the sidewalls. By depositing the getter layer to extend to a location on the sidewalls of the cavity, the area of the substrate that is able to absorb the one or more residual gases is increased.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: May 2, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Jen Chan, Lee-Chuan Tseng, Shih-Wei Lin, Che-Ming Chang, Chung-Yen Chou, Yuan-Chih Hsieh
  • Patent number: 9607923
    Abstract: An electronic device is provided, which includes an electronic element and a heat dissipating element disposed on the electronic element through a thermal conductor, wherein a width of the thermal conductor is smaller than a width of the electronic element. The thermal conductor includes silver to thereby greatly increase the thermal conductivity of the thermal conductor and hence improve the thermal conduction efficiency of the electronic device.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: March 28, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chung-Jen Hung, Chi-An Pan, Chi-Hsiang Hsu, Liang-Yi Hung
  • Patent number: 9607951
    Abstract: According to an embodiment of the present invention, a chip package is provided. The chip package includes a substrate. A chip is disposed on the substrate. A stiffener is disposed on the substrate. The thermal conductivity of the stiffener is higher than the thermal conductivity of the substrate.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: March 28, 2017
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Uming Ko, Tzu-Hung Lin, Tai-Yu Chen
  • Patent number: 9601686
    Abstract: A method of making a magnetoresistive structure is disclosed. The method includes forming a pillar structure including a magnetic tunnel junction on a substrate that includes a first electrode, depositing a stressed layer onto a pillar structure sidewall, and depositing a second electrode above the magnetic tunnel junction.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Gen P. Lauer, Adam M. Pyzyna
  • Patent number: 9577406
    Abstract: Various implementations relating to an illumination package including an edge-emitting laser diode (EELD) are disclosed. In one embodiment, an illumination package includes a heat spreader including a base and a stub that extends from the base, an EELD configured to generate illumination light, the EELD being mounted to a side surface of the stub, and a substrate coupled to the base at a location spaced from the EELD, the substrate being electrically connected to the EELD.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 21, 2017
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Sridhar Canumalla, Ketan R. Shah