Cap Or Lid Patents (Class 257/704)
  • Patent number: 10916527
    Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Xiao Li, Anilkumar Chandolu
  • Patent number: 10883680
    Abstract: A light-emitting module includes: a package substrate that is provided with a recessed portion having an opening at an upper surface thereof; a light-emitting device that is housed in the recessed portion; a window member that is provided on the upper surface such that the window member covers the opening; and a sealing portion that bonds the package substrate and the window member. The window member includes a lens portion facing the light-emitting device and a flange portion that projects from the lens portion and bonds to the sealing portion. The lens portion and the flange portion are formed of the same glass material.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 5, 2021
    Assignee: NIKKISO CO., LTD.
    Inventors: Hidenori Konagayoshi, Nobuhiro Torii, Tetsumi Ochi, Hiroki Kiuchi
  • Patent number: 10879160
    Abstract: The semiconductor package includes a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Jae Woong Yu, So Hyun Jung
  • Patent number: 10879214
    Abstract: Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 ?m per 1 mm range. A method of manufacturing the die stack structure is also provided.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Wen-Chih Chiou, Yung-Lung Chen
  • Patent number: 10872837
    Abstract: The present disclosure relates to an air-cavity semiconductor package, which includes a thermal carrier, a ring structure, a package lid, and at least one semiconductor device. The thermal carrier has a carrier body, a heat slug residing within the carrier body, a top coating layer formed over a top surface of the heat slug, and a bottom coating layer formed over a bottom surface of the heat slug. The ring structure includes a ring body with an interior opening, which resides over the thermal carrier, such that a portion of a top surface of the thermal carrier is exposed through the interior opening. The package lid resides over the ring structure and has a recess conjoined with the interior opening forming an enclosed cavity. The at least one semiconductor device is attached to the exposed portion of the top surface of the thermal carrier and encapsulated in the enclosed cavity.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 22, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Robert Charles Dry, Christine Blair
  • Patent number: 10863282
    Abstract: A MEMS package has a MEMS chip, a package substrate which the MEMS chip is adhered, a chip-cover which wraps the MEMS chip, and a cover-supporting part which supports the chip-cover from the inside. In the MEMS package, the chip-cover is supported by the cover-supporting part to form a back chamber, surrounded by the chip-cover and the package substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: December 8, 2020
    Assignee: SAE Magnetics (H.K.) Ltd.
    Inventors: Koichi Shiozawa, Masashi Shiraishi, Jumpei Tsuchiya, Lik Hang Ken Wan, Toyotaka Kobayashi, Hironobu Hayashi
  • Patent number: 10833208
    Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 10, 2020
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Alexandre Mas, Eric Saugier, Gaetan Lobascio, Benoit Besancon
  • Patent number: 10805716
    Abstract: The present invention discloses a package structure of a MEMS microphone. The package structure comprises a package substrate and a package shell, wherein the package shell is provided on the package substrate and forms a closed cavity with the package substrate. In the package structure provided by the present invention, the sound-absorbing layer is arranged on the inner wall of the Helmholtz resonant cavity. The sound-absorbing layer has a certain absorption capacity to high-frequency sound waves, but has a very low absorption to low-frequency sound waves, so it may be equivalent to a “low-pass filter”. Through the absorption of the high-frequency sound waves, a high-frequency amplitude value of sound waves can be suppressed, reducing high-frequency response of the Helmholtz resonant cavity. That is, a high-frequency cut-off frequency of the sound waves is improved, widening operation bandwidth of the MEMS microphone.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 13, 2020
    Assignee: GOERTEK.INC
    Inventor: Guoguang Zheng
  • Patent number: 10795452
    Abstract: User expectations demand that keypad layout and size, as well as keypad performance and illumination remain the same or improve over time. In various implementations, the keyboards disclosed and detailed herein incorporate an array of thermoset bare die light emitting diodes in an effort to more evenly distribute light through a keyboard structure without increasing keyboard thickness, as compared to prior art designs.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 6, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Benjamin Patrick Sullivan, James David Holbery, Siyuan Ma, David Michael Lane, Thomas Joseph Longo
  • Patent number: 10785576
    Abstract: A MEMS package has a MEMS chip, a package substrate, a dammed-seal part. The MEMS chip has an element substrate which a movable element is formed, the package substrate has a sound hole. The dammed-seal part has an annular dam-member which is formed on the element substrate so as to surround the movable element, and a gel member. The MEMS chip is mounted on the package substrate so that the movable element opposes to the sound hole. The gel member is formed by hardening of gel which is applied on the annular dam-member from outside so as to surround the annular dam-member.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 22, 2020
    Assignee: SAE Magnetics (H.K.) Ltd.
    Inventors: Akio Nakao, Masashi Shiraishi
  • Patent number: 10784165
    Abstract: According to an embodiment, a semiconductor device includes a silicon substrate, a device layer, and a lower layer. The device layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: September 22, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shingo Masuko, Kazuo Fujimura, Yoshiharu Takada, Ichiro Mizushima
  • Patent number: 10781097
    Abstract: A micromechanical component, having a carrier wafer having at least one micromechanical structure that is situated in a cavern; a thin-layer cap situated on the carrier wafer, by which the cavern is hermetically sealed; and a cap wafer situated on the thin-layer cap in the region of the cavern having the micromechanical structure, the cap wafer hermetically sealing a region of the thin-layer cap above the cavern.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 22, 2020
    Assignee: Robert Bosch GmbH
    Inventor: Christoph Schelling
  • Patent number: 10720350
    Abstract: A sensor wafer may be configured for in-situ measurements of parameters during an etch process. The sensor wafer may include a substrate, a cover, and one or more components positioned between the substrate and the cover. An etch-resistant coating is formed on one or more surfaces of the cover and/or substrate. The coating is configured to resist etch processes that etch the cover and/or substrate for a longer period than standard thin film materials of the same or greater thickness than the protective coating.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: July 21, 2020
    Assignee: KLA-TENCORE CORPORATION
    Inventors: Andrew Nguyen, Farhat Quli, Mei Sun, Vasudev Venkatesan
  • Patent number: 10696547
    Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 30, 2020
    Assignee: SiTime Corporation
    Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
  • Patent number: 10679929
    Abstract: A semiconductor package device includes a leadframe, a first die and a package body. The leadframe includes a first die paddle and a lead. The first die paddle has a first surface and a second surface opposite to the first surface. The first die is disposed on the first surface of the first die paddle. The package body covers the first die and at least a portion of the first surface of the first die paddle and exposing the lead. The package body has a first surface and a second surface opposite to the first surface. The second surface of the package body is substantially coplanar with the second surface of the first die paddle. The lead extends from the second surface of the package body toward the first surface of the package body. A length of the lead is greater than a thickness of the package body.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 9, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING KOREA, INC.
    Inventors: Junyoung Yang, Sangbae Park
  • Patent number: 10651278
    Abstract: An object is to provide a technology capable of suppressing a crack of a crystalline nitride layer which is generated due to a stress caused by difference in thermal expansion coefficients between a crystalline nitride and diamond. A semiconductor device includes a crystalline nitride layer, a structure containing silicon, and a diamond layer. The structure is disposed on a first main surface of the crystalline nitride layer. The diamond layer is disposed at least on a lateral portion of the structure and has a void between the diamond layer and the first main surface of the crystalline nitride layer. The void is a stress absorbing space, for example.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: May 12, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeo Furuhata, Tomohiro Shinagawa
  • Patent number: 10640367
    Abstract: A waterproofed environmental sensing device with water detection provisions includes an environmental sensor to sense one or more environmental properties. The device further includes an electronic integrated circuit implemented on a substrate and coupled to the environmental sensor via a wire bonding. An air-permeable cap structure is formed over the environmental sensor, and a protective layer is formed over the wire bonding to protect the wire bonding against damage.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Apple Inc.
    Inventors: Krishna Prasad Vummidi Murali, Kuolung Lei, Richard Yeh, Yun X. Ma
  • Patent number: 10643913
    Abstract: A stiffener apparatus for reducing warpage of an integrated circuit package during heating and cooling are provided. The stiffener apparatus includes an IC substrate configured to receive an IC die on a top side of the IC substrate. The stiffener apparatus includes a primary stiffener ring adhered to the top side of the IC substrate and defining an opening in a region of the IC die such that the primary stiffener ring surrounds the region of the IC die. The primary stiffener ring defines a plurality of grooves. The stiffener apparatus includes a secondary stiffener ring having a plurality of catches configured to engage with the plurality of grooves to removably attach the secondary stiffener ring to the primary stiffener ring on a side of the primary stiffener ring opposite the IC substrate. A method of using a stiffener apparatus during a manufacturing operation is also provided.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 5, 2020
    Assignee: Google LLC
    Inventors: Woon Seong Kwon, Phillip La, Michael Trent Wise
  • Patent number: 10643983
    Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having a stiffener that extends beyond a package substrate outer edge, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a package substrate having a first side, a second side opposite the first side, and an outer edge extending between the first side and the second side; an IC die coupled with the first side of the package substrate, where the IC die includes a power terminal; a stiffener coupled with the first side of the package substrate, where the stiffener surrounds the IC die and includes a conductive routing region coupled with the IC die power terminal, and a passive electronic device coupled with the conductive routing region. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Khang Choong Yong, Howe Yin Loo
  • Patent number: 10615090
    Abstract: An object of the present invention is to provide a seal ring having a metal brazing material layer on one surface of a base material containing KOVAR and a metal plating layer on the other surface, ensuring that the seal ring can prevent generation of a stain on the surface of a metal plating layer and excellent airtightness of an electronic component housing package can be achieved. The present invention has attained the object above by a seal ring which is an annular sealing ring having a nickel layer on the first surface of a base material containing KOVAR (iron-nickel-cobalt alloy) and a metal brazing material layer on the second surface opposite the first surface, wherein the thickness of the nickel layer is from 0.1 to 20 ?m.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: April 7, 2020
    Assignees: TANAKA KIKINZOKU KOGYO K.K., KYOCERA CORPORATION
    Inventors: Harumi Takeoka, Kazuharu Yoshida, Ryuta Ido, Junichi Takeuchi
  • Patent number: 10600700
    Abstract: This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method may include: providing a top wafer structure, where the top wafer structure includes a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, where the bottom wafer structure includes a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad, to form multiple pads. This application may mitigate a problem that bonded pads are connected to each other.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: March 24, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: YiPing Mao, GuangNing Li
  • Patent number: 10562761
    Abstract: Aspects of the disclosure provide a waterproof packaging technique for fabricating waterproof microphones in mobile devices. A device based on the waterproof packaging technique can include a microelectromechanical system (MEMS) device, a housing enclosing the MEMS device, and a liquid-resistant air inlet passive device (LRAPD) on the housing. The LRAPD can include at least one channel connecting an exterior of the housing with a chamber formed between the housing and the MEMS device. An inside surface of the channel can be coated with a liquid-repellant coating. In some examples, the liquid-repellant coating can be a self-assembled monolayer (SAM) coating.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: February 18, 2020
    Inventors: Kathirgamasundaram Sooriakumar, Anu Austin, Ian Rose Bihag
  • Patent number: 10546820
    Abstract: A radio frequency module includes a wiring substrate, a plurality of components mounted on an upper surface of the wiring substrate, a sealing resin layer laminated on the upper surface of the wiring substrate and covering the plurality of components, a groove formed in an upper surface of the sealing resin layer and extending between predetermined components of the plurality of components, and a shielding wall made of conductive paste in the groove. The sealing resin layer has a stepped area defining the higher portion and lower portion in the upper surface. The groove intersects the stepped area when the wiring substrate is seen in plan view.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 28, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihisa Masuda, Ryoichi Kita, Issei Yamamoto, Katsuki Nakanishi, Yukio Nakazawa
  • Patent number: 10522434
    Abstract: A semiconductor device is provided. The semiconductor device includes a terminal portion and a casing portion. The terminal portion has a through hole in a principal surface portion. The casing portion has a depression at a position facing the through hole and has an end surface facing portion facing an end surface of the terminal portion. An end surface protruding portion is provided on at least one of the end surface and the end surface facing portion.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 31, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshihiro Kodaira
  • Patent number: 10519033
    Abstract: This application relates to transducer apparatus (300, 400), especially for MEMS capacitive transducers. The apparatus has a voltage bias generator (102) for receiving a supply voltage (VDD) and generating a bias voltage (VB) for biasing a capacitive transducer (101). A voltage supply path extends between a supply voltage input terminal (309a) and the voltage bias generator (102). A programmable trim circuit (207), in use, controls the bias voltage generated by the voltage bias generator. A first filter (301) is configured to applying filtering to the voltage supply path. A programming contact pad (308) is configured to form an external contact of the transducer apparatus when packaged and is electrically coupled to the programmable trim circuit via a signal path that does not include the first filter.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: December 31, 2019
    Assignee: Cirrus Logic, Inc.
    Inventor: Ian Johnson Smith
  • Patent number: 10508023
    Abstract: An embodiment is MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Jung-Huei Peng, Shang-Ying Tsai, Hung-Chia Tsai, Yi-Chuan Teng
  • Patent number: 10453760
    Abstract: A lid array panel includes multiple lids, where each lid includes an outer side wall. The lid array panel further includes a bridge section surrounding and attached to the outer side walls of the lids, where the lids are connected to each other by the bridge section, the lid array panel further includes a reinforcement attached to the bridge section. A package structure includes a carrier, a chip disposed on an upper surface of the carrier, a lid, a bridge section, and a reinforcement. The lid includes a top wall and an outer side wall, the top wall and the outer side wall of the lid together define a cavity, and the outer side wall of the lid is attached to the upper surface of the carrier. The bridge section surrounds, and is attached to, the outer side wall of the lid. The reinforcement is attached to the bridge section.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: October 22, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang Chin Tsai, Hsun-Wei Chan
  • Patent number: 10446456
    Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: October 15, 2019
    Assignee: Invensas Corporation
    Inventors: Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram
  • Patent number: 10446506
    Abstract: A wafer level package includes a substrate including bonding pads and a first protection dam and having a plurality of circuit pattern units disposed on a side; a printed circuit board having a plurality of connection pads, a second protection dam and via holes disposed thereon; and a connection unit connected to some of the plurality of connection pads and the second protection dam disposed on the printed circuit board. Freedom of design can be improved through the wafer level package and the manufacturing method thereof, and reliability of the wafer level package can be improved. The manufacturing process can be simplified as the bridge process is omitted when wiring is designed, and the size of an element may be reduced.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 15, 2019
    Assignee: WISOL CO., LTD.
    Inventors: Jung Hoon Han, Eun Tae Park, Jin Ho Ha, Jun Woo Yong
  • Patent number: 10439118
    Abstract: A device and techniques for fabricating the device are described for forming a wafer-level thermal sensor package using microelectromechanical system (MEMS) processes. In one or more implementations, a wafer level thermal sensor package includes a thermopile stack, which includes a substrate, a dielectric membrane, a first thermoelectric layer, a first interlayer dielectric, a second thermoelectric layer, a second interlayer dielectric, a metal connection assembly, a passivation layer, where the passivation layer includes at least one of a trench or a hole, and where the substrate includes a cavity adjacent to the at least one trench or hole, and a bond pad disposed on the passivation layer and electrically coupled to the metal connection assembly; and a cap wafer assembly coupled to the thermopile stack, the cap wafer assembly including a wafer having a cavity formed on a side of the wafer configured to be adjacent to the thermopile stack.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: October 8, 2019
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Arvin Emadi, Nicole D. Kerness, Arkadii V. Samoilov, Abhishek Sahasrabudhe
  • Patent number: 10438901
    Abstract: Some features pertain to a package that includes an enhanced electromagnetic shield. The package includes a substrate, an electronic component coupled to the substrate, and a mold partially surrounding the electronic component. The package further includes a first shield over the mold, and a second shield over the first shield. One of the first shield or the second shield is a high permeability shield and the remaining first or second shield is a high conductivity shield relative to the high permeability shield.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 8, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Anna Katharina Krefft, Claus Reitlinger
  • Patent number: 10420222
    Abstract: Methods and system which eliminate steps in the mounting a discrete device to an electronic circuit using a conductive film, shortening the time required to attach each discrete device. The methods place a discrete device onto the conductive tape and partially cure portions of the adhesive. The discrete device is then removed from the conductive tape along with the adhesive and conductive particles which have been transferred onto the contact pads of the discrete device. The discrete device is then placed on the substrate and aligned. Pressure and heat are applied to complete the bond.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: September 17, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Brent S. Krusor, Ping Mei
  • Patent number: 10381287
    Abstract: This application discloses an device disposed on a substrate, and a heat sink disposed on the substrate over the device. The heat sink disposed on the substrate forms a cavity to hold a fluid between the heat sink and the device. The fluid can absorb heat emitted by the device and transfer at least a portion of the absorbed heat to the heat sink. A gasket can be disposed between and in contact with the substrate and the heat sink. The gasket can prevent the fluid from exiting the cavity formed by the heat sink disposed on the substrate. The heat sink can have an opening to the cavity, which can be detachably sealed by a plug. The plug can reduce a pressure within the cavity or allow removal of gas bubbles in the fluid held in the cavity.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: August 13, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Spencer Saunders, Terry Goode
  • Patent number: 10373883
    Abstract: A semiconductor package device comprises a substrate, an electronic component and a protection layer. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a first opening penetrating the substrate. The electronic component is disposed on the first surface of the substrate. The protection layer is disposed on the second surface of the substrate. The protection layer has a first portion adjacent to the first opening and a second portion disposed farther away from the first opening than is the first portion of the protection layer. The first portion of the protection layer has a surface facing away from the second surface of the substrate. The second portion of the protection layer has a surface facing away from the second surface of the substrate.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 6, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-An Fang, Chi Sheng Tseng
  • Patent number: 10347572
    Abstract: A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first side of the package component, a dielectric material formed over the first side of the package component, wherein four corners of the top surface of the package component are free from the dielectric material and a top package bonded on the first side of the package component, wherein the semiconductor die is located between the top package and the package component.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 10334370
    Abstract: Apparatus, systems and methods for reducing feedback in a hearing aid that includes a transducer configured to detect sound, a sound processor configured to process signals from the transducer, a receiver configured to receive signals outputted from the sound processor, and an acoustic feedback reduction system. The acoustic feedback reduction system is configured to provide signals to the sound processor to produce a null targeting signal steerable toward a source of feedback.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: June 25, 2019
    Assignee: Eargo, Inc.
    Inventors: Bret Herscher, Takahiro Unno, Daniel Shen, Florent Michel, Raphael Michel
  • Patent number: 10331182
    Abstract: An example heat exchanger may comprise a base to thermally conductively engage with a computing component, a plurality of fins that may extend from the base on the same side as the computing component, and an auxiliary fluid channel defined by the plurality of fins. The plurality of fins may transfer thermal energy from the computing component to a fluid medium surrounding the plurality of fins. The auxiliary fluid channel may facilitate the transfer of thermal energy from an electronic component, other than the computing component, disposed within the auxiliary fluid channel to a fluid medium flowing through the auxiliary fluid channel.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: June 25, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Kevin B. Leigh, George D. Megason, John Norton
  • Patent number: 10319666
    Abstract: A process of forming a thermal interface material structure includes forming an assembly that includes a thermal interface material disposed between a first mating surface and a second mating surface. The first mating surface is associated with a module lid, and the second mating surface is associated with a heat sink. Protruding surface features are incorporated onto the first mating surface or the second mating surface. The process also includes compressing the assembly to form a thermal interface material structure. The thermal interface material structure includes the thermal interface material disposed within an interface defined by the first mating surface and the second mating surface. The protruding surface features protrude from the first mating surface or the second mating surface into selected areas of the interface to limit relative movement of the mating surfaces into the selected areas during thermal cycling to reduce thermal interface material migration out of the interface.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric J. Campbell, Sarah K. Czaplewski, Elin F. Labreck, Jennifer I. Porto
  • Patent number: 10276957
    Abstract: An attachment structure for use with a standalone control unit. The control unit includes a threaded insert located in an enclosed cavity which allows screws to be used for grounding of an EMI/RFI board, along with creating a sealed, enclosed pocket. The attachment structure allows for grounding of the PCB to the sheet metal base plate without creating a leak path to the outside of the control unit. This ground approach encapsulates the screw to prevent the formation of a leak path.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: April 30, 2019
    Assignee: Continental Automotive Systems, Inc.
    Inventors: Wayne J Wright, Donald J Zito, Vladimir Mulina
  • Patent number: 10199562
    Abstract: A method of fabricating an electronic device, the method including: arranging a device chip with no bump located on a lower surface of the device chip on a mounting substrate including a bump located on an upper surface of the mounting substrate; and bonding a pad located on the lower surface of the device chip and the bump by applying an ultrasonic wave to the device chip from an upper surface of the device chip.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: February 5, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Shinji Yamamoto, Jumpei Konno, Takashi Miyagawa
  • Patent number: 10178786
    Abstract: A circuit package for electrically connecting a plurality of modules. The circuit package having a first and second mounting plate, each including a plurality of module connectors configured to receive and form electrical connections with the plurality of modules. The circuit package also having a first and second sidewall mounted to the first and second mounting plates. The first sidewall including a plurality of sidewall fins extending outward from the first sidewall so that the plurality of sidewall fins are positioned between the first and second mounting plates and at least partially interleave with the plurality of modules.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: January 8, 2019
    Assignee: Honeywell International Inc.
    Inventors: James L. Tucker, Romney R. Katti
  • Patent number: 10175073
    Abstract: A differential pressure detection element includes: a support portion having an opening; a cantilever portion supported in a cantilever manner by the support portion so as to protrude into the opening; a diffusion layer including a piezoresistive portion provided at a fixed end of the cantilever portion; a pair of wiring portions electrically connected to the diffusion layer; a first insulating layer covering the diffusion layer; and a second insulating layer laid on the first insulating layer. A linear expansion coefficient of the first insulating layer is smaller than a linear expansion coefficient of a material of which the cantilever portion is composed, and a linear expansion coefficient of the second insulating layer is larger than the linear expansion coefficient of the first insulating layer.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: January 8, 2019
    Assignee: FUJIKURA LTD.
    Inventors: Hayato Arai, Tatsuya Shioiri, Naoki Takayama
  • Patent number: 10163755
    Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Xiao Li, Steven K. Groothuis, Jian Li, Jaspreet S. Gandhi, James M. Derderian, David R. Hembree
  • Patent number: 10157863
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a die structure formed over the substrate. The semiconductor device structure also includes a lid structure formed over the die structure. The lid structure includes a top portion with a top length and a bottom portion with a bottom length, and the top length is greater than the bottom length. The semiconductor device structure also includes a package layer formed between the lid structure and the die structure, and a sidewall of the bottom portion of the lid structure is not aligned with a sidewall of the die structure.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Chi-Yang Yu, Yu-Chih Liu
  • Patent number: 10134690
    Abstract: Embodiments herein may relate to a package with one or more layers. A silicon die may be coupled with the one or more layers via an adhesive. A package stiffener may also be coupled with the adhesive adjacent to the die. A magnetic thin film may be coupled with the package stiffener. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Hao-Han Hsu, Ying Ern Ho, Jaejin Lee
  • Patent number: 10128230
    Abstract: An RC-IGBT has a chip area of the semiconductor chip larger than that of a semiconductor chip including an IGBT section but not including an FWD section, as it is provided with the FWD section. It is demanded to reduce the chip area of the RC-IGBT semiconductor chip. Provided is a semiconductor device including: a transistor section including a plurality of transistors; a free wheeling diode section being at least opposite to one side of the transistor section and provided outside the transistor section, when the transistor section is seen from a top view; and a gate runner section and a gate pad section provided to contact the transistor section and not surrounding an entire periphery of the transistor section, when the transistor section is seen from a top view.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tohru Shirakawa, Hiroyuki Tanaka
  • Patent number: 10121720
    Abstract: A semiconductor device, such as a semiconductor power device, includes: a semiconductor die having a semiconductor die front surface, a package formed onto the semiconductor die, the package having a portion facing the front surface of the semiconductor die, and a thermally-conductive layer including graphene over the front portion of the package facing the front surface of the semiconductor die.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: November 6, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10099919
    Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chih Liang, Chia-Hua Chu, Te-Hao Lee, Jiou-Kang Lee, Chung-Hsien Lin
  • Patent number: 10096584
    Abstract: In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: October 9, 2018
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Guido Boenig, Irmgard Escher-Poeppel, Edward Fuergut, Martin Gruber, Thorsten Meyer
  • Patent number: 10091899
    Abstract: The embodiments disclose a method for creating a digital device protective artwork case conforming to digital device shapes and sizes and includes electronically stitched artwork designs that seamlessly wraparound the digital device protective artwork case, a shock absorbing flexible bumper core with flexible buttons to operate digital device buttons, a flexible back, a hard outer shell back, a hard outer shell portable charger external battery with blinking LED eyes battery level indicators, a tempered glass front face, a digital device protective artwork case website including at least one processor, at least one digital electronic stitching processor, at least one database, at least one communication device, an internet connection, and at least one manufacturing data interface to transfer user selections of protective artwork case styles and stock artwork designs to at least to at least one manufacturing device including an electronically stitched image application device and a mold material depositing dev
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: October 2, 2018
    Inventor: Eli Altaras