Cap Or Lid Patents (Class 257/704)
  • Patent number: 11948838
    Abstract: The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: April 2, 2024
    Assignee: Qorvo US, Inc.
    Inventor: Deep C. Dumka
  • Patent number: 11848245
    Abstract: A power semiconductor apparatus includes a power semiconductor element having low and high potential side electrodes and a sense electrode, high and low potential side conductors electrically connected with the high potential side electrodes, respectively, a sense wiring electrically connected with the sense electrode, and a first metal portion facing the low potential side conductor or the low potential side conductor across the sense wiring. When viewed from an array direction of the sense wiring and the first metal portion, the sense wiring has a facing portion facing the high or low potential side conductor, the first metal portion forms a recess in a part overlapping the facing portion, and a depth of the recess is formed such that a distance between a bottom of the recess and the sense wiring is larger than a distance between the sense wiring and the high or low potential side conductor.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: December 19, 2023
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Hironori Nagasaki, Shintaro Tanaka, Takashi Hirao
  • Patent number: 11774308
    Abstract: A sensor device includes a sensor unit sensitive for a property of a gaseous medium. The sensor unit is formed on a first surface of a sensor substrate. A frame structure on the first surface includes a first loop portion laterally surrounding a first area that includes the sensor unit. A communicating channel accesses the first area through at least one of a lateral port in the first loop portion and a base port in the sensor substrate. A lid structure completely covers the frame structure and the first area.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: October 3, 2023
    Assignee: Infineon Technologies AG
    Inventors: Rainer Leuschner, Kerstin Kaemmer, Roland Meier, Marten Oldsen, Karolina Zogal
  • Patent number: 11705415
    Abstract: A semiconductor device includes: a first semiconductor chip; plural redistribution lines provided on a main face of the first semiconductor chip, the plural redistribution lines including a redistribution line that includes a first land and a redistribution line that includes a second land; a first electrode provided within the first land, one end of the first electrode being connected to the first land, and another end of the first electrode being connected to an external connection terminal; and a second electrode provided within the second land, one end of the second electrode being connected to the second land, wherein a shortest distance between an outer edge of the second land and an outer edge of the second electrode, is less than, a shortest distance between an outer edge of the first land and an outer edge of the first electrode.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: July 18, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Taiichi Ogumi
  • Patent number: 11621211
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die, a molding material, a first bonding layer, and a thermal interface material. The semiconductor die is disposed over the substrate. The molding material surrounds the semiconductor die. The first bonding layer is disposed over the semiconductor die. The thermal interface material is disposed over the molding material.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 4, 2023
    Assignee: MediaTek Inc.
    Inventors: Ya-Jui Hsieh, Chia-Hao Hsu, Tai-Yu Chen, Yao-Pang Hsu
  • Patent number: 11586160
    Abstract: Methods and systems for reducing substrate particle scratching using machine learning are provided. A machine learning model is trained to predict process recipe settings for a substrate temperature control process to be performed for a current substrate at a manufacturing system. First training data and second training data are generated for the machine learning model. The first training data includes historical data associated with prior process recipe settings for a prior substrate temperature control process performed for a prior substrate at a prior process chamber. The second training data is associated with a historical scratch profile of one or more surfaces of the prior substrate after performance of the prior substrate temperature control process according to the prior process recipe settings.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: February 21, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Kartik B Shah, Satish Radhakrishnan, Karthik Ramanathan, Karthikeyan Balaraman, Adolph Miller Allen, Xinyuan Chong, Mitrabhanu Sahu, Wenjing Xu, Michael Sterling Jackson, Weize Hu, Feng Chen
  • Patent number: 11559827
    Abstract: An ultrasonic transducer includes a membrane, a bottom electrode, and a plurality of cavities disposed between the membrane and the bottom electrode, each of the plurality of cavities corresponding to an individual transducer cell. Portions of the bottom electrode corresponding to each individual transducer cell are electrically isolated from one another. Each portion of the bottom electrode corresponds to each individual transducer that cell further includes a first bottom electrode portion and a second bottom electrode portion, the first and second bottom electrode portions electrically isolated from one another.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: January 24, 2023
    Assignee: BFLY Operations, Inc.
    Inventors: Susan A. Alie, Keith G. Fife, Joseph Lutsky, David Grosjean
  • Patent number: 11545409
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: January 3, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Tatsuo Nishizawa, Motohito Hori, Eiji Mochizuki
  • Patent number: 11482461
    Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
  • Patent number: 11464118
    Abstract: Methods for manufacturing an electronic device include providing a substrate having a plurality of radio-frequency components provided thereon, the radio-frequency components including an antenna and a matching circuitry. A cap is attached to the substrate over the antenna and the matching circuitry and a molding operation is performed to encapsulate the cap and at least a portion of the substrate with a mold compound.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: October 4, 2022
    Assignee: PCI PRIVATE LIMITED
    Inventors: Handi Kartadihardja, Nelson Ranola, Chi Wei Yap, Stephen Conner
  • Patent number: 11442026
    Abstract: Disclosed is a method of making a crack structure on a substrate, the crack structure being usable as a tunnelling junction structure in a nanogap device, including the controlled fracture or release of a patterned layer under built-in stress, thereby forming elements separated by nanogaps or crack-junctions. The width of the crack-defined nanogap is controlled by locally release-etching the film at a notched bridge patterned in the film. The built-in stress contributes to forming the crack and defining of the width of the crack-defined nanogap. Further, by design of the length of the bridge in a range between sub-??? to >25???, the separation between the elements, defined by the width of the crack-defined nanogaps, can be controlled for each individual crack structure from <2 nm to >100 nm. The nanogaps can be used for tunneling devices in combination with nanopores for DNA, RNA or peptides sequencing.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: September 13, 2022
    Assignee: Zedna AB
    Inventors: Valentin Dubois, Frank Niklaus, Göran Stemme
  • Patent number: 11418687
    Abstract: An embodiment comprises: a lens barrel; a holder; a filter disposed in the holder; a circuit board having an aperture; a reinforcing member including a first region corresponding to the aperture and a second region in which the circuit board is disposed; and an image sensor disposed in the first region of the reinforcing member, wherein the first region of the reinforcing member includes a protruding part protruding farther than the second region of the reinforcing member, and the image sensor is disposed on the upper surface of the protruding part.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: August 16, 2022
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Min Soo Kim, In Hoe Kim, Hyun Ah Oh, Sung Il Lee, Jong Ho Chung
  • Patent number: 11404349
    Abstract: In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, Ravindranath V. Mahajan, Robert L. Sankman, James C. Matayabas, Jr., Ken P. Hackenberg, Nayandeep K. Mahanta, David D. Olmoz
  • Patent number: 11387161
    Abstract: A device package and a method of forming a device package are described. The device package includes a lid with one or more legs on an outer periphery of the lid, a top surface, and a bottom surface, where the lid is disposed on the substrate. The legs of the lid are attached to the substrate with a sealant. The device package also has one or more dies disposed on the substrate. The die(s) are below the bottom surface of the lid, where each of the dies has a top surface and a bottom surface. The device package further includes a retaining structure disposed between the bottom surface of the lid and the top surface of the die, where the retaining structure has one or more inner walls. The device package includes a thermal interface material disposed within the inner walls of the retaining structure and above the top surface of the die.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventor: Feras Eid
  • Patent number: 11365116
    Abstract: The present invention is to provide an optical scanner module. An optical scanner apparatus scans laser light by oscillating a mirror with a piezoelectric element. A package that mounts the optical scanner apparatus and electrically is connected to a substrate via a connector. A package cover that is fixed to the package and seals the optical scanner apparatus so that the optical scanner apparatus is not visually recognized from an outside. The package and the package cover are bonded by a heat curing adhesive agent. A vent for releasing gas in a space where the optical scanner apparatus is sealed is formed in the package cover, and the vent is blocked by ultraviolet curing resin.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: June 21, 2022
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Tsukasa Yamada, Takahiro Wakasugi, Shinobu Kasahara
  • Patent number: 11367628
    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: June 21, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Priyal Shah, Milind S. Bhagavat, Brett P. Wilkerson, Lei Fu, Rahul Agarwal
  • Patent number: 11335648
    Abstract: A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 17, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
  • Patent number: 11317184
    Abstract: The present disclosure provides a vibration sensor and an audio device. The vibration sensor includes a housing having an inner wall and an inner chamber, an elastic sheet, a mass piece and a MEMS chip having a back cavity, the elastic sheet, the mass piece and the MEMS chip being arranged in the chamber. The elastic sheet is attached to the inner wall, the mass piece is mounted on one side of the elastic sheet away from the inner wall. The elastic sheet covers the concave cavity and defines a first through hole communicated with the concave cavity. The mass piece is provided with a second through hole communicated with the first through hole. And the first and the second through holes communicate with the back cavity and the concave cavity. The vibration sensor provided by the present disclosure has simple structure, small height and high sensitivity.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: April 26, 2022
    Assignee: AAC Acoustic Technologies (Shenzhen) Co., Ltd.
    Inventor: Jinyu Zhang
  • Patent number: 11305984
    Abstract: A waterproofed environmental sensing device with water detection provisions includes an environmental sensor to sense one or more environmental properties. The device further includes an electronic integrated circuit implemented on a substrate and coupled to the environmental sensor via a wire bonding. An air-permeable cap structure is formed over the environmental sensor, and a protective layer is formed over the wire bonding to protect the wire bonding against damage.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 19, 2022
    Assignee: Apple Inc.
    Inventors: Krishna Prasad Vummidi Murali, Kuolung Lei, Richard Yeh, Yun X. Ma
  • Patent number: 11296010
    Abstract: The disclosure describes a heat-dissipating object having a reservoir structure so that a reservoir system can be formed in an electronic device, allowing for a liquid TIM in the gap between the heat-dissipating object and the heat-generating object of the electronic device. The reservoir structure comprises a seal ring, a connecting hole and a reservoir which is a space for taking in a liquid material and releasing it again when needed. As a specific case of the heat-dissipating object and the electronic device, a lid having a reservoir structure and a lidded flip chip package based on the lid are particularly described in details of the embodiments of the present invention.
    Type: Grant
    Filed: February 8, 2020
    Date of Patent: April 5, 2022
    Inventor: Yuci Shen
  • Patent number: 11291106
    Abstract: An electronic device includes a packaged device and a thermal dissipater. The packaged device includes a component that generates thermal energy, a package that encapsulates the component, and an interconnect that forms a portion of a high thermal conduction between the component and a circuit card. The thermal dissipater obtains the thermal energy using the circuit card and radiates the thermal energy.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: March 29, 2022
    Assignee: Dell Products L.P.
    Inventors: Isaac Q. Wang, Jordan H. Chin, James L. Petivan, Robert Boyd Curtis, Tim M. Spencer
  • Patent number: 11282764
    Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Liangbiao Chen, Yong Liu, Tzu-Hsuan Cheng, Stephen St. Germain, Roger Arbuthnot
  • Patent number: 11270919
    Abstract: A method of forming a custom module lid. The method may include placing a multichip module (MCM) between a module base and a temporary lid, target components are exposed through viewing windows in the temporary lid, a top surface of the target components is measured and mapped to create a target profile, the target profile is used to form custom pockets in a custom lid, and the custom pockets correspond to the target components.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Amilcar R. Arvelo, Michael J. Ellsworth, Eric J. McKeever, Thong N. Nguyen, Edward J. Seminaro
  • Patent number: 11259399
    Abstract: Embodiments herein may include apparatuses, systems, and processes related to a socket with a first side to receive a package substrate and a second side coupled with a printed circuit board (PCB), which may be a mother board, where the socket has a cavity into which a thermal conductor is inserted to conduct heat from the package substrate to the PCB. In embodiments, the PCB may contain thermal vias to conduct heat from one side of the PCB to the other side. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Hongfei Yan, Yuan-Liang Li, Leo Liu, Chunlei Guo
  • Patent number: 11257690
    Abstract: A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wensen Hung
  • Patent number: 11251111
    Abstract: Embodiments include apparatuses, methods, and systems that may include a leadframe of a circuit package to conduct heat generated by an integrated circuit (IC) included in the circuit package, while being a part of an interconnect of the circuit package. In various embodiments, a circuit package may include a package substrate, and an IC attached to the package substrate. A leadframe may be disposed on the IC to conduct heat generated by the IC. In addition, the leadframe may be a part of an interconnect of the circuit package, and the leadframe may be electrically coupled to a component of the IC. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventor: Hyoung Il Kim
  • Patent number: 11211364
    Abstract: Semiconductor device assemblies are provided with one or more layers of thermally conductive material disposed between adjacent semiconductor dies in a vertical stack. The thermally conductive material can be configured to conduct heat generated by one or more of the semiconductor dies in laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), or via adhering a film comprising the layer of thermally conductive material to one or more of the semiconductor dies.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hyunsuk Chun, Xiaopeng Qu
  • Patent number: 11180365
    Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chih Liang, Chia-Hua Chu, Te-Hao Lee, Jiou-Kang Lee, Chung-Hsien Lin
  • Patent number: 11137296
    Abstract: A force sensor includes a package substrate, a MEMS-based device, a package body and a force touching member. The MEMS-based device is disposed on the package substrate and electrically connected with the package substrate. The package body encapsulates the MEMS-based device. The force touching member including a rod is disposed on the package body and corresponding to the MEMS-based device. The force sensor allows a greater assembly tolerance.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 5, 2021
    Assignee: MIRAMEMS SENSING TECHNOLOGY CO., LTD
    Inventors: Li-Tien Tseng, Yu-Hao Chien, Chih-Liang Kuo, Yu-Te Yeh
  • Patent number: 11107747
    Abstract: A semiconductor package is provided. The semiconductor package includes a substrate and a semiconductor die over the substrate. A heat-dissipating feature covers the substrate and the semiconductor die, and a composite thermal interface material (TIM) structure is thermally bonded between the semiconductor die and the heat-dissipating feature. The composite TIM structure includes a metal-containing matrix material layer and polymer particles embedded in the metal-containing matrix material layer.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Liang Shao, Jen-Yu Wang, Chung-Jung Wu, Chih-Hang Tung, Chen-Hua Yu
  • Patent number: 11101241
    Abstract: The semiconductor device includes, on the cooling substrate, first main terminal, second main terminal, third main terminal, and fourth main terminal, each having a polygonal-shape. The first external-connection face on upper surface of the first main terminal is connected to positive electrode, and the fourth external-connection face on upper surface of the fourth main terminal is connected to negative electrode. First semiconductor element electrically connected between side surface of the first main terminal and side surface of the second main terminal, and second semiconductor element electrically connected between side surface of the third main terminal and side surface of the fourth main terminal are provided. The second main terminal and the third main terminal are disposed adjacent to each other while being separated, and the first main terminal and the fourth main terminal are disposed adjacent to each other while being separated.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: August 24, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hideyo Nakamura
  • Patent number: 11069729
    Abstract: A photoelectric conversion device, including: a photoelectric conversion substrate having a plurality of photoelectric conversion portions and a microlens array arranged on the plurality of photoelectric conversion portions; a light-transmitting plate covering the microlens array; and a film arranged between the microlens array and the light-transmitting plate, wherein the film has a refractive index within a range from 1.05 to 1.15, an average transmittance of light in a wavelength region within a range from 400 nm to 700 nm of 98.5% or higher, and a film thickness within a range from 500 nm to 5000 nm.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: July 20, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Satoshi Yamabi, Yoshinori Kotani, Akio Kashiwazaki, Yoshihiro Ohashi, Masami Tsukamoto
  • Patent number: 10993039
    Abstract: An acoustic microelectronic device includes a support, a set of at least one membrane suspended on a face of the support above a cavity by an anchoring zone, and at least one acoustic insulation trench arranged adjacent to the membrane. The device includes at least one bridge connecting the portions of two opposite edges of the trench and located overhanging at least one zone of the trench so as to form, in the zone of the trench, an acoustic insulation box below the bridge.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: April 27, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stephane Fanget, Caroline Coutier, Philippe Robert
  • Patent number: 10981781
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
  • Patent number: 10966337
    Abstract: An electrical converter having pluggable converter components includes a first electronic assembly having electronic parts an assembly carrier, a housing chassis and a housing cover, wherein at least one of the electronic parts is a power semiconductor switch having a wide band gap and made of GaN or of InGaN. The power semiconductor switch is operated with a reverse bias of at least 400 V and at a clock frequency of at least 40 kHz during operation of the electrical converter. The first electronic assembly is mechanically plugged into the assembly carrier by connecting elements, and the first electronic assembly together with the assembly carrier is mechanically plugged and locked by further connecting elements to the housing chassis or to the housing cover using corresponding locking elements on the housing chassis or to the housing cover, respectively.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 30, 2021
    Assignee: Siemens Aktiengesellschaft
    Inventor: Stefan Pfefferlein
  • Patent number: 10958860
    Abstract: A method includes preparing a circuit board that includes a first metal pattern over a first face side of the substrate, a first electrode in a periphery of the first metal pattern, a second electrode over a second face side of the substrate, and a second metal pattern thermally connected to the first metal pattern and in which an electronic device is fixed on the first metal pattern and an electronic component is electrically connected to the second electrode, and connecting the first electrode and a third electrode of the electronic device by a bonding wire with the electronic device being heated. By a board support stage, the electronic device is heated by transferring heat to the electronic device via the second and then first metal pattern with the circuit board being supported to form a space including the electronic component between the second face and the board support stage.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 23, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Satoshi Nozu, Yu Aoki, Koji Tsuduki
  • Patent number: 10957623
    Abstract: Forming a thermal interface material structure includes forming an assembly that includes a thermal interface material disposed between a first mating surface and a second mating surface. The first mating surface is associated with a module lid, and the second mating surface is associated with a heat sink. Protruding surface features are incorporated onto the first mating surface or the second mating surface. The process also includes compressing the assembly to form a thermal interface material structure. The thermal interface material structure includes the thermal interface material disposed within an interface defined by the first mating surface and the second mating surface. The protruding surface features protrude from the first mating surface or the second mating surface into selected areas of the interface to limit relative movement of the mating surfaces into the selected areas during thermal cycling to reduce thermal interface material migration out of the interface.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Eric J. Campbell, Sarah K. Czaplewski-Campbell, Elin F. LaBreck, Jennifer I. Bennett
  • Patent number: 10943857
    Abstract: A substrate for semiconductor elements includes a terminal part including a first surface, a second surface opposite to the first surface, and side surfaces joining the first surface and the second surface, and a resin part covering the side surfaces and exposing the first surface of the terminal part. The resin part has a multi-layer structure including a first resin and a second resin, and the first resin is provided in contact with the side surfaces of the terminal part. The first resin and the second resin include a filler, and an amount of the filler included in the first resin is smaller than an amount of the filler included in the second resin.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: March 9, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kentaro Kaneko, Harunobu Sato, Tsukasa Nakanishi, Junichi Nakamura, Koji Watanabe
  • Patent number: 10916527
    Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Xiao Li, Anilkumar Chandolu
  • Patent number: 10883680
    Abstract: A light-emitting module includes: a package substrate that is provided with a recessed portion having an opening at an upper surface thereof; a light-emitting device that is housed in the recessed portion; a window member that is provided on the upper surface such that the window member covers the opening; and a sealing portion that bonds the package substrate and the window member. The window member includes a lens portion facing the light-emitting device and a flange portion that projects from the lens portion and bonds to the sealing portion. The lens portion and the flange portion are formed of the same glass material.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 5, 2021
    Assignee: NIKKISO CO., LTD.
    Inventors: Hidenori Konagayoshi, Nobuhiro Torii, Tetsumi Ochi, Hiroki Kiuchi
  • Patent number: 10879160
    Abstract: The semiconductor package includes a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Jae Woong Yu, So Hyun Jung
  • Patent number: 10879214
    Abstract: Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 ?m per 1 mm range. A method of manufacturing the die stack structure is also provided.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Wen-Chih Chiou, Yung-Lung Chen
  • Patent number: 10872837
    Abstract: The present disclosure relates to an air-cavity semiconductor package, which includes a thermal carrier, a ring structure, a package lid, and at least one semiconductor device. The thermal carrier has a carrier body, a heat slug residing within the carrier body, a top coating layer formed over a top surface of the heat slug, and a bottom coating layer formed over a bottom surface of the heat slug. The ring structure includes a ring body with an interior opening, which resides over the thermal carrier, such that a portion of a top surface of the thermal carrier is exposed through the interior opening. The package lid resides over the ring structure and has a recess conjoined with the interior opening forming an enclosed cavity. The at least one semiconductor device is attached to the exposed portion of the top surface of the thermal carrier and encapsulated in the enclosed cavity.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 22, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Robert Charles Dry, Christine Blair
  • Patent number: 10863282
    Abstract: A MEMS package has a MEMS chip, a package substrate which the MEMS chip is adhered, a chip-cover which wraps the MEMS chip, and a cover-supporting part which supports the chip-cover from the inside. In the MEMS package, the chip-cover is supported by the cover-supporting part to form a back chamber, surrounded by the chip-cover and the package substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: December 8, 2020
    Assignee: SAE Magnetics (H.K.) Ltd.
    Inventors: Koichi Shiozawa, Masashi Shiraishi, Jumpei Tsuchiya, Lik Hang Ken Wan, Toyotaka Kobayashi, Hironobu Hayashi
  • Patent number: 10833208
    Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 10, 2020
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Alexandre Mas, Eric Saugier, Gaetan Lobascio, Benoit Besancon
  • Patent number: 10805716
    Abstract: The present invention discloses a package structure of a MEMS microphone. The package structure comprises a package substrate and a package shell, wherein the package shell is provided on the package substrate and forms a closed cavity with the package substrate. In the package structure provided by the present invention, the sound-absorbing layer is arranged on the inner wall of the Helmholtz resonant cavity. The sound-absorbing layer has a certain absorption capacity to high-frequency sound waves, but has a very low absorption to low-frequency sound waves, so it may be equivalent to a “low-pass filter”. Through the absorption of the high-frequency sound waves, a high-frequency amplitude value of sound waves can be suppressed, reducing high-frequency response of the Helmholtz resonant cavity. That is, a high-frequency cut-off frequency of the sound waves is improved, widening operation bandwidth of the MEMS microphone.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 13, 2020
    Assignee: GOERTEK.INC
    Inventor: Guoguang Zheng
  • Patent number: 10795452
    Abstract: User expectations demand that keypad layout and size, as well as keypad performance and illumination remain the same or improve over time. In various implementations, the keyboards disclosed and detailed herein incorporate an array of thermoset bare die light emitting diodes in an effort to more evenly distribute light through a keyboard structure without increasing keyboard thickness, as compared to prior art designs.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 6, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Benjamin Patrick Sullivan, James David Holbery, Siyuan Ma, David Michael Lane, Thomas Joseph Longo
  • Patent number: 10781097
    Abstract: A micromechanical component, having a carrier wafer having at least one micromechanical structure that is situated in a cavern; a thin-layer cap situated on the carrier wafer, by which the cavern is hermetically sealed; and a cap wafer situated on the thin-layer cap in the region of the cavern having the micromechanical structure, the cap wafer hermetically sealing a region of the thin-layer cap above the cavern.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 22, 2020
    Assignee: Robert Bosch GmbH
    Inventor: Christoph Schelling
  • Patent number: 10785576
    Abstract: A MEMS package has a MEMS chip, a package substrate, a dammed-seal part. The MEMS chip has an element substrate which a movable element is formed, the package substrate has a sound hole. The dammed-seal part has an annular dam-member which is formed on the element substrate so as to surround the movable element, and a gel member. The MEMS chip is mounted on the package substrate so that the movable element opposes to the sound hole. The gel member is formed by hardening of gel which is applied on the annular dam-member from outside so as to surround the annular dam-member.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 22, 2020
    Assignee: SAE Magnetics (H.K.) Ltd.
    Inventors: Akio Nakao, Masashi Shiraishi
  • Patent number: 10784165
    Abstract: According to an embodiment, a semiconductor device includes a silicon substrate, a device layer, and a lower layer. The device layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: September 22, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shingo Masuko, Kazuo Fujimura, Yoshiharu Takada, Ichiro Mizushima