Abstract: Methods and apparatus provide for: applying an inorganic barrier layer to at least a portion of a flexible substrate, the barrier layer being formed from a low liquidus temperature (LLT) material; and sintering the inorganic barrier layer while maintaining the flexible substrate below a critical temperature.

Abstract: A more thinnable hermetic sealing cap can be provided. This hermetic sealing cap (10) is employed for an electronic component housing package (100) housing an electronic component (40) and includes a cap body portion (1) mainly composed of Ti.

Abstract: A shielded embedded electronic component substrate includes a core dielectric layer having a die opening. An electrically conductive die shield lines the die opening. An electronic component is mounted within the die opening and to the die shield, where the die shield shields the electronic component. By mounting the electronic component within the die opening, the shielded embedded electronic component substrate is made relatively thin. Further, heat generated by the electronic component is dissipated to the die shield and to the ambient environment. Accordingly, the shielded embedded electronic component substrate is well suited for use when the electronic component generates a significant amount of heat, e.g., in high power applications.

Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.

Abstract: A vacuum hermetic organic packaging carrier is provided. The organic packaging carrier includes an organic substrate, a conductive circuit layer, and an inorganic hermetic insulation film. The organic substrate has a first surface. The conductive circuit layer is located on the first surface and exposes a portion of the first surface. The inorganic hermetic insulation film at least covers the exposed first surface to achieve an effect of completely hermetically sealing the organic packaging carrier.

Abstract: A semiconductor component includes a semiconductor element that has a plurality of signals, a wiring board that is disposed below the semiconductor element and that draws the plurality of signals of the semiconductor element, a heat conduction member that dissipates heat generated by the semiconductor element, a joining member that is disposed between the semiconductor element and the heat conduction member and that joins the heat conduction member to the semiconductor element, a support member formed with an opening so as to surround the semiconductor element that supports the heat conduction member, a first adhesive member that is disposed between the support member and the wiring board to bond the support member with the wiring board and a second adhesive member that is disposed between the support member and the heat conduction member to bond the support member with the heat conduction member.

Abstract: A capped integrated device includes a semiconductor chip, incorporating an integrated device and a protective cap, bonded to the semiconductor chip for protection of the integrated device by means of a bonding layer made of a bonding material. The bonding material forms anchorage elements within recesses, formed in at least one between the semiconductor chip and the protective cap.

Abstract: This disclosure provides systems, methods and apparatus for fabricating spacers for electromechanical systems devices. In one aspect, a method of forming a spacer on a spacer portion of a device surface of an electromechanical systems device includes exposing the device surface to spacer particles suspended in a fluid. The spacer particles are allowed to attach to the spacer portion. Each of the spacer particles can have at least one dimension of about 1 micron to 10 microns. The electromechanical systems device can also include a sacrificial layer that is subsequently removed between the device surface and a substrate surface of a substrate on which the electromechanical systems device is formed.

Abstract: An electronic device, including a substrate, a functional structure constituting a functional element formed on the substrate, and a cover structure forming a cavity portion in which the functional structure is disposed, is disclosed. In the electronic device, the cover structure includes a laminated structure of an interlayer insulating film and a wiring layer, the laminated structure being formed on the substrate in such a way that it surrounds the cavity portion, and the cover structure has an upside cover portion covering the cavity portion from above, the upside cover portion being formed with part of the wiring layer that is disposed above the functional structure.

Abstract: An RF package includes a substrate mountable on a base plate, a non-conductive cover overlying the substrate, and quasi-serpentine stepped source leads attached to an upper surface of the substrate and extending from at least one of a pair of opposite sides of the upper surface of the substrate to tapered lower surfaces of the cover. The cover includes a recess to receive the substrate. The recess includes stress distribution surface areas to engage and press outer edge portions of opposite sides of the substrate against a base plate or heat sink. The tapered lower surfaces of the cover engage with and press against the stepped source leads when securing the RF package to the base plate or heat sink using one or more fasteners or bolts. The cover includes structural features to improve preferential deformation when a mounting force is applied.

Abstract: A semiconductor package is provided, which includes: a micro electro mechanical system (MEMS) chip; a cap provided on the MEMS chip; an electronic element provided on the cap including a plurality of first conductive pads and second conductive pads; a plurality of first conductive elements electrically connected to the first conductive pads and the MEMS chip; a plurality of second conductive elements formed on the second conductive pads, respectively; and an encapsulant formed on the MEMS chip covering the cap, the electronic element, the first conductive elements and the second conductive elements, with the second conductive elements being exposed from the encapsulant. Thus, the size of the semiconductor package is reduced. A method of fabricating the semiconductor package is also disclosed.

Abstract: A packaging scheme for MEMS device is provided. A method of packaging MEMS device in a semiconductor structure includes forming an insulation fence that surrounds the MEMS device on the semiconductor structure. The method further includes attaching a wafer of dielectric material to the insulation fence. The lid wafer, the insulation fence, and the semiconductor structure enclose the MEMS device.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

Abstract: An optical device package includes a substrate having an upper surface, a distal end, a proximal end, and distal and proximal longitudinally extending notches co-linearly aligned with each other. A structure is mounted to the substrate and has at least one recessed portion. The structure can be a lid or a frame to which a lid is bonded. An optical fiber is positioned within at least one of the proximal longitudinally extending notch and the distal longitudinally extending notch and within the recessed portion of the structure mounted to the substrate. The optical device package can also include conductive legs extending upwardly from bonding pads on the upper surface of the substrate to facilitate flip mounting of the optical device package onto a circuit board or other such platform.

Abstract: A semiconductor package which includes a substrate formed from AlN and electrical terminals formed from tungsten on at least one surface of the substrate by bulk metallization to serve as electrical connection to a component within the package.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a stiffener, having a stiffener opening completely through the stiffener, on the substrate; molding an encapsulation on the substrate and directly on an outer upper periphery surface of the stiffener and exposing an inner upper periphery surface of the stiffener, the encapsulation exposing a portion of the substrate; mounting an integrated circuit over the substrate and within the perimeter of the stiffener; and attaching a lid plate on the inner upper periphery surface of the stiffener and over the integrated circuit, the lid plate extending above an encapsulation top side.

Abstract: A chip card in the form of an ID-1 card, a plug-in SIM or a USB token has a layered compound (12) with two (4, 5) or three (4, 5, 9) layers extending over the complete chip card (1). An exterior foil layer (4) has on its outward facing front side (4a) a communication contact layout (2) and on its back side (4b) a flip chip (7), as well as a flip chip contact layout (6) which is electroconductively connected with the communication contact layout (2) on the front side.

Abstract: One embodiment of a micro-electronic device includes a substrate including micro-electronic components thereon, and a cover including a ring of sealing material secured to the substrate and a raised ring of material positioned opposite the cover from the ring of sealing material.

Abstract: A semiconductor package is provided for carrying a sleeve member and a fan wheel axially coupled to the sleeve member so as to provide a heat dissipating function. The semiconductor package includes: a substrate; a coil module and at least an electronic component disposed on the substrate; and an encapsulant formed on the substrate for encapsulating the coil module and the electronic component so as to prevent the coil module and the electronic component from disturbing air flow generated by the fan wheel during operation, thereby avoiding generation of noises or vibrations.

Abstract: A method of manufacturing a ball grid array, BGA, integrated circuit package, comprising forming a double sided printed circuit board, PCB, with blind vias interconnecting electrically the circuits on the opposed surfaces of the PCB, with at least one through-hole to allow fluid or gas to pass through the PCB, and an integrated circuit connected to the printed circuit on one side of the PCB; soldering a lid onto the said one side of the PCB to enclose the integrated circuit, whilst allowing thermally expanding gas or fluid to escape through the or each through-hole, whereby to form a package which is hermetically sealed except for the or each through-hole, and which has a cavity between the integrated circuit and the lid; applying a BGA to the side of the PCB opposed to the said one side, whereby to solder the balls of the BGA to respective portions of the printed circuit and to align one of the balls axially with each through-hole; and soldering the ball or balls into the through-hole, or into each respectiv

Abstract: In inlets used for ID tags and the like, a defective connection between an integrated circuit part and an antenna is suppressed by improvement of tolerance for a bending or a pressing pressure. The integrated circuit part includes a semiconductor chip and a multilayer substrate having a concave portion. The semiconductor chip is mounted on the bottom of the concave portion. The multilayer substrate includes a connection electrode at the top surface and a connection electrode connected to the semiconductor chip on the bottom of the concave portion. The connection electrode on the bottom of the concave portion is connected to the connection electrode at the top surface by a penetration electrode inside a multilayer substrate. By such a configuration, the semiconductor chip is connected to the antenna.

Abstract: A package structure includes a first die, and a second die over and bonded to the first die. The second die has a size smaller than a size of the first die. A dummy chip is over and bonded onto the first die. The dummy chip includes a portion encircling the second die. The dummy chip includes a material selected from the group consisting essentially of silicon and a metal.

Abstract: In order to connect a semiconductor device including an integrated circuit to an external circuit typified by an antenna, the shape of the contact electrode to be formed in the semiconductor device is devised, so that bad connection between the external circuit and the contact electrode is not easily caused and the contact electrode with high reliability is provided. The contact electrode is formed by a screen printing method using a squeegee having a chamfered corner or having a wedge shape. The contact electrode has a peripheral portion and a central portion. The peripheral portion has a tapered portion with its film thickness gradually decreasing from the central portion toward the end portion, and the central portion has a projection portion that continues from the tapered portion.

Abstract: The present invention includes a semiconductor laser element, a lead, a first packaging member and a second packaging member. The lead includes a mount surface for supporting the semiconductor laser element. The first packaging member includes a first wall and a second wall. The first and the second walls are spaced from each other in a direction that is along the mount surface and crosses a laser beam emission direction of the semiconductor laser element, with the semiconductor laser element arranged between the first and the second walls. The second packaging member is pressed in between the first and the second walls and faces the mount surface and the semiconductor laser element.

Abstract: An electronic component mounting substrate including a support layer made of resin with first and second surfaces, an organic insulation layer on the first surface of the support layer with a first surface on opposite side of the first surface of the support layer and a second surface in contact with the first surface of the support layer, an inorganic insulation layer on the first surface of the organic layer, a conductor on the second surface of the support layer, and a first conductive circuit on the second surface of the organic layer. The inorganic layer has a second conductive circuit and a pad for mounting an electronic component inside the inorganic layer. The organic layer has a via conductor inside the organic layer and connecting the first and second circuits. The support layer has a conductive post inside the support layer and connecting the first circuit and the conductor.

Abstract: A method and structures are provided for implementing enhanced thermal conductivity between a lid and heat sink for stacked modules. A chip lid and lateral heat distributor includes cooperating features for implementing enhanced thermal conductivity. The chip lid includes a groove along an inner side wall including a flat wall surface and a curved edge surface. The lateral heat distributor includes a mating edge portion received within the groove. The mating edge portion includes a bent arm for engaging the curved edge surface groove and a flat portion. The lateral heat distributor is assembled into place with the chip lid, the mating edge portion of the lateral heat distributor bends and snaps into the groove of the chip lid. The bent arm portion presses on the curved surface of the groove, and provides an upward force to push the flat portion against the flat wall surface of the groove.

Abstract: A packaged MEMS device, wherein at least two support structures are stacked on each other and are formed both by a support layer and a wall layer coupled to each other and delimiting a respective chamber. The chamber of the first support structure is upwardly delimited by the support layer of the second support structure. A first and a second dice are accommodated in a respective chamber, carried by the respective support layer of the first support structure. The support layer of the second support structure has a through hole allowing wire connections to directly couple the first and the second dice. A lid substrate, coupled to the second support structure, closes the chamber of the second support structure.

Abstract: A sacrificial material applied to a thin die prior to die attach provides stability to the thin die and inhibits warpage of the thin die as heat is applied to the die and substrate during die attach. The sacrificial material may be a material that sublimates at a temperature near the reflow temperature of interconnects on the thin die. A die attach process deposits the sacrificial material on the die, attaches the die to a substrate, and applies a first temperature to reflow the interconnects. At the first temperature, the sacrificial material maintains substantially the same thickness. A second temperature is applied to sublimate the sacrificial material leaving a clean surface for the later packaging processes. Examples of the sacrificial material include polypropylene carbonate and polyethylene carbonate.

Abstract: A pressure-contact power semiconductor module is arranged on a heat sink. The power semiconductor module is used with at least one substrate provided with conductor tracks and power semiconductor components. The module has a mounting body, on the underside of which the at least one substrate is arranged, and which is formed with cutouts. The module also includes a load connection element which is provided with contact feet that project away from strip sections and make pressure contact with the conductor tracks. The power semiconductor module additionally has a dimensionally stable cover, which covers the mounting body on all sides and is connected to the mounting body by means of snap-action latching connections. At least one pad element is restrained between the cover and the strip sections of the load connection elements.

Abstract: A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism.

Abstract: A shielded package includes a shield assembly having a shield fence, a shield lid, and a shield lid adhesive electrically coupling the shield lid to the shield fence. The shield fence includes a porous sidewall through which molding compound passes during molding of the shielded package. Further, the shield fence includes a central aperture through which an electronic component is die attached and wire bonded.

Abstract: A Ferroelectric tunnel FET switch as ultra-steep (abrupt) switch with subthreshold swing better than the MOSFET limit of 60 mV/decade at room temperature combining two key principles: ferroelectric gate stack and band-to-band tunneling in gated p-i-n junction, wherein the ferroelectric material included in the gate stack creates, due to dipole polarization with increasing gate voltage, a positive feedback in the capacitive coupling that controls the band-to-band (BTB) tunneling at the source junction of a silicon p-i-n reversed bias structure, wherein the combined effect of BTB tunneling and ferroelectric negative capacitance offers more abrupt off-on and on-off transitions in the present proposed Ferroelectric tunnel FET than for any reported tunnel FET or any reported ferroelectric FET.

Abstract: An integrated circuit package is described. The integrated circuit package comprises a substrate having a plurality of sides, where each pair of adjacent sides forms a corner; a die coupled to a first surface of the substrate; a lid having a first portion positioned over the die and a plurality of foot portions, each foot portion of the plurality of foot portions being coupled to the first surface of the substrate at a corresponding corner of the substrate, where a side of the integrated circuit package above the substrate and between two associated foot portions has an opening; and a plurality of contact elements coupled to a second surface of the substrate. A method of forming an integrated circuit package is also shown.

Abstract: In accordance with the present invention, there is provided a quad flat no leads (QFN) semiconductor device or package including a leadframe wherein the leads of the leadframe are selectively formed so that portions one or more prescribed leads are exposed in a package body of the semiconductor package and electrically connected to an electromagnetic interference (EMI) shielding layer applied to the package body. In certain embodiments of the present invention, one or more tie bars of the leadframe may also be formed so as to be exposed in the package body of the semiconductor package and electrically connected to the shielding layer applied to the package body. Thus, in the present invention, the shielding layer may be electrically connected to one or more leads alone or in combination with one or more tie bars of the leadframe.

Abstract: An integrated circuit package includes a thermally and electrically conductive package lid. The package lid may be in electrical communication with an electrically conductive pad connected to a power plane, ground plane, or signal route in the integrated circuit. The electrically conductive package lid may provide an electrical connection for electrical power or electrical signals or may serve as an electrical ground. In some embodiments, the package lid may include a thermally and electrically conductive material. In other embodiments, the package lid may include an electrically insulative substrate coated on at least one surface with a layer of metal or another conductive material. The conductive layer may be electrically connected to electrical ground, a reference voltage, or a signal pay by at least one electrically conductive via.

Abstract: A surface mount electronic device packaging assembly includes a body having an aperture defined therethrough. The aperture is adapted to receive an electronic device therein. The body has a first surface and a second surface. An electrically conductive contact pad is disposed on the first surface of the body. The contact pad is adapted to receive a lead from the electronic device. A thermally conductive base pad is disposed on the second surface of the body. A top surface of the base pad is adapted to receive the electronic device thereon.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone. The inventive package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate which performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the die and the package, and providing an exterior surface for making electrical connections between package and a user's printed circuit board.

Abstract: A semiconductor device has a base substrate having a plurality of metal traces. A conductive polymer cover is provided having an opening. The conductive polymer cover forms a cavity when attached to the base substrate. At least one die is attached to an interior surface of the conductive polymer cover and positioned over the opening. The conductive polymer cover and the at least one die are electrically coupled to metal traces on the first surface of the base substrate.

Abstract: The present invention integrates a shield on a flat, no-lead (FN) semiconductor package, which has multiple rows of contact pads along any side. The FN semiconductor package will have at least one inner row and one outer row of contact pads on at least one side. The inner and outer rows of contact pads and a die attach pad form the foundation for the FN semiconductor package. A die is mounted on the die attach pad and connected by wirebonds to certain contact pads of the inner rows of contact pads. An overmold body is formed over the die, die attach pad, wirebonds, and inner row of contact pads, and substantially encompasses each contact pad of the outer row of contact pads. A conformal coating is applied over the overmold body, including the exposed surfaces of the contact pads of the outer row of contact pads, providing a shield.

Abstract: According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Abstract: A package enclosing at least one microelectronic element (60) such as a sensor die and having electrically conductive connection pads (31) for electric connection of the package to another device is manufactured by providing a sacrificial carrier; applying an electrically conductive pattern (30) to one side of the carrier; bending the carrier in order to create a shape of the carrier in which the carrier has an elevated portion and recessed portions; forming a body member (45) on the carrier at the side where the electrically conductive pattern (30) is present; removing the sacrificial carrier; and placing a microelectronic element (60) in a recess (47) which has been created in the body member (45) at the position where the elevated portion of the carrier has been, and connecting the microelectronic element (60) to the electrically conductive pattern (30). Furthermore, a hole (41) is arranged in the package for providing access to a sensitive surface of the microelectronic element (60).

Abstract: A system and method for controlling temperature of a MEMS sensor are disclosed. In a first aspect, the system comprises a MEMS cap encapsulating the MEMS sensor and a CMOS die vertically arranged to the MEMS cap. The system includes a heater integrated into the MEMS cap. The integrated heater is activated to control the temperature of the MEMS sensor. In a second aspect, the method comprises encapsulating the MEMS sensor with a MEMS cap and coupling a CMOS die to the MEMS cap. The method includes integrating a heater into the MEMS cap. The integrated heater is activated to control the temperature of the MEMS sensor.

Abstract: An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.

Abstract: An encapsulation for an organic light emitting diode (OLED) device is disclosed. The encapsulation includes a sealing dam surrounding the cell region of the OLED device to support a cap. Spacer particles are randomly located in the cell region to prevent the cap from contacting the active components, thereby protecting them from damage. The sealing dam provides a sealing region between the edge of the cap and dam in which an adhesive is applied to seal the OLED device. The use of the sealing dam advantageously enables devices to be formed with narrower sealing widths.

Abstract: A multi-chip electronic package and methods of manufacture are provided. The method comprises adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier. The adjusting comprises placing a chip shim on the chips and placing a seal shim between a lid and the chip carrier. The seal shim is thicker than the chip shim. The adjusting further comprise lowering the lid until the pistons contact the chip shim. The method further comprises separating the lid and the chip carrier and removing the chip shim and the seal shim. The method further comprises dispensing thermal interface material on the chips and lowering the lid until a gap filled with the thermal interface material is about a particle size of the thermal interface material. The method further comprises sealing the lid to the chip carrier with sealant.

Abstract: An electronic component has a substrate, a die bonding pad provided on an upper surface of the substrate, a semiconductor element bonded onto the die bonding pad by a die bonding resin, a conductive pattern disposed adjacent to the die bonding pad, and a coating member covering the conductive pattern. At least an outer peripheral portion of a surface of the die bonding pad is made of an inorganic material. The inorganic material of the outer peripheral portion is exposed. The die bonding pad and the conductive pattern are separated by an air gap such that the coating member does not come into contact with the die bonding pad.

Abstract: A semiconductor package includes a semiconductor substrate having a semiconductor device arranged on one surface thereof; a cap substrate having one surface that opposes the one surface of the semiconductor substrate via a gap; a spacer that is arranged between the one surface of the semiconductor substrate and the one surface of the cap substrate, and that joins the semiconductor substrate and the cap substrate; and a filter that is provided on the cap substrate so as to overlap with the semiconductor device without overlapping with the spacer. The semiconductor package and method of manufacture can suppress exfoliation of the filter caused by chipping during the dicing step.

Abstract: Methods are provided for production of pre-collapsed capacitive micro-machined ultrasonic transducers (cMUTs). Methods disclosed generally include the steps of obtaining a nearly completed traditional cMUT structure prior to etching and sealing the membrane, defining holes through the membrane of the cMUT structure for each electrode ring fixed relative to the top face of the membrane, applying a bias voltage across the membrane and substrate of the cMUT structure so as to collapse the areas of the membrane proximate to the holes to or toward the substrate, fixing and sealing the collapsed areas of the membrane to the substrate by applying an encasing layer, and discontinuing or reducing the bias voltage. CMUT assemblies are provided, including packaged assemblies, integrated assemblies with an integrated circuit/chip (e.g., a beam-steering chip) and a cMUT/lens assembly. Advantageous cMUT-based applications utilizing the disclosed pre-collapsed cMUTs are also provided, e.g.

Abstract: A method for forming wavelength-conversion LED encapsulant structure includes forming an LED encapsulant structure body, forming a layer of a wavelength-conversion material on a first surface, disposing the first surface to cause the wavelength-conversion material to be in contact with a surface region of the LED encapsulant structure body, applying a pressure between the first surface and the surface region of the LED encapsulant structure body, and causing at least a portion of the wavelength-conversion material to be at least partially embedded in the surface region of the LED encapsulant structure body.

Abstract: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.