Of High Thermal Conductivity Ceramic (e.g., Beo) Patents (Class 257/705)
  • Patent number: 10410959
    Abstract: Package deflection and mechanical stress of microelectronic packaging is minimized in a two step manufacturing process. In a first step, a ceramic insulator is high-temperature bonded between a wraparound lead layer and a buffer layer of a same material as the lead layer to provide a symmetrically balanced three-layer structure. In a second step, the three-layer structure is high temperature bonded, using a lower melt point braze, to a heat spreader. This package configuration minimizes package deflection, and thereby improves thermal dissipation and reliability of the package.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 10, 2019
    Assignee: Kyocera International, Inc.
    Inventors: Franklin Kim, Mark Eblen, Shinichi Hira
  • Patent number: 10405430
    Abstract: Close-contact layers that are capable of improving the degree of contact between electrodes and a ceramic insulating layer can be formed at low cost by firing a glass paste. When the electrodes, the ceramic insulating layer, and the close-contact layers are fired at the same time, the glass paste is sintered last, and thus, formation of voids, defects, and the like in portions of the ceramic insulating layer, on which the electrodes are disposed, as a result of shrinkage of the electrodes and the ceramic insulating layer at the time of firing being hindered by stress generated due to the difference in the degree of shrinkage can be suppressed. Therefore, the structure of the ceramic insulating layers in the above portions can be elaborated by the close-contact layers.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: September 3, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tatsunori Kan
  • Patent number: 10134607
    Abstract: A method for bonding wafers is provided. The method comprises the steps of providing a first wafer having an exposed first layer, the first layer comprising a first metal; and providing a second wafer having an exposed second layer, the second layer comprising a second metal, the first metal and the second metal capable of forming a eutectic mixture having a eutectic melting temperature. The method further comprises the steps of contacting the first layer with the second layer; and applying a predetermined pressure at a predetermined temperature to form a solid-state diffusion bond between the first layer and the second layer, wherein the predetermined temperature is below the eutectic melting temperature.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: November 20, 2018
    Assignee: Agency for Science, Technology and Research
    Inventors: Vivek Chidambaram, Sunil Wickramanayaka, Jinghui Xu, Zhipeng Ding, Li Yan Siow
  • Patent number: 10128164
    Abstract: An electronic component has a semiconductor element and a thermally conductive support member. A heat sink is disposed on one surface of the circuit body, and a thermally conductive insulating member is interposed between the heat sink and the support member. Input and output terminals and a ground terminal are also provided. A sealing resin is formed to expose a part of each of the input and output terminals and the ground terminal and one surface of the heat sink, and to cover a periphery of the electronic component structure. A main body conductor layer is formed to be insulated from the input and output terminals and cover an immersion region of the sealing resin and one surface of the heat sink immersed in a cooling medium. A ground conductor layer covers at least a part of the ground terminal and is electrically connected with the main body conductor layer.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: November 13, 2018
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Hiroyuki Temmei, Mina Amo, Nobutake Tsuyuno, Takeshi Tokuyama, Toshiaki Ishii, Toshiya Satoh
  • Patent number: 9899305
    Abstract: A semiconductor package structure is disclosed. The semiconductor package structure includes: a substrate having a front surface and a back surface; a chip-on-interposer structure mounted on the front surface of the substrate; a back side stiffener mounted over the back surface of the substrate and surrounding a projection of the chip-on-interposer structure from a back surface perspective; and a plurality of conductive bumps mounted on the back surface of the substrate.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ting-Yu Yeh, Wei-Ming Chen, Yi-Chiang Sun
  • Patent number: 9728482
    Abstract: A semiconductor device includes a housing, a substrate housed in and fixed to the housing, and a semiconductor module package disposed on a surface of the substrate. A protrusion is formed on the housing, protrudes towards the substrate, located adjacent to the semiconductor module package, and directly or indirectly urges the substrate in a direction away from the protrusion.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: August 8, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Yamamoto, Yousuke Hisakuni
  • Patent number: 9617455
    Abstract: A silicone resin composition is provided that exhibits an increased adhesiveness relative to insulating circuit substrates and can prevent bubble production even when moisture absorption has occurred, exhibits an excellent heat resistance, and is free of problems such as cracking. A silicone resin composition for use as a sealant for a power semiconductor module includes an insulating circuit substrate having a Cu layer formed on a surface thereof. The silicone resin composition is formed on the Cu layer of the insulating circuit substrate, and has, after curing, a penetration of 35 to 70 and an adhesive strength of 50 to 180 kPa between the silicone resin composition and the insulating circuit substrate. The penetration is measured in accordance with JIS K 2220.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: April 11, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Higashidate, Yuji Ichimura
  • Patent number: 9426929
    Abstract: A MMIC package is disclosed comprising: a leadframe based overmolded package, a die positioned within the overmolded package; and a partial waveguide interface, wherein the partial waveguide interface is integral with the overmolded package facilitating low cost and reliable assembly. Also disclosed is an overmolded package where the die sits on a metal portion exposed on the bottom of the package and the package is configured for attachment to a chassis of a transceiver such that heat from the die is easily dissipated to the chassis with a direct thermal path. The disclosure facilitates parallel assembly of MMIC packages and use of pick and place/surface mounting technology for attaching the MMIC packages to the chassis of transceivers. This facilitates reliable and low cost transceivers.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 23, 2016
    Assignee: ViaSat, Inc.
    Inventors: David R. Laidig, Kenneth V. Buer, Michael R. Lyons, Noel A. Lopez
  • Patent number: 9273574
    Abstract: According to the present invention, there is provided an exhaust gas purifying filter capable of effectively removing collected particulate matter. An exhaust gas purifying filter of the present invention includes an inflow surface into which exhaust gas including particulate matter flows, an exhaust surface which exhausts purified gas, and a filter substrate which is constructed of a porous body, wherein the filter substrate includes porous partitions and gas passages which are enclosed by the partitions, and a porous film, which includes silicon carbide and pores having a smaller pore diameter than the pores of the partitions, is provided on the surface of the partitions, and a silicon dioxide layer is formed on at least an outer surface portion of the porous film.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: March 1, 2016
    Assignees: SUMITOMO OSAKA CEMENT CO., LTD., HONDA MOTOR CO., LTD.
    Inventors: Masamichi Tanaka, Atsushi Kishimoto, Tadashi Neya, Keita Ishizaki
  • Patent number: 9035448
    Abstract: Semiconductor packages are provided that have a base plate with a matrix of pure silver or a silver alloy and reinforcement particles. The reinforcement particles can include high thermal conductivity, low CTE particles selected from the group consisting of diamond, cubic boron nitride (c-BN), silicon carbide (SiC), and any combinations thereof. In some embodiments, the base plate is entirely comprised of the composite. In other embodiments, the base plate has a core made of the composite. The core can include at least one outer layer on the core. The semiconductor package can include one or more dice or transistors on the base plate, an insulated frame on the base plate, and one or more leads on the insulated frame.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 19, 2015
    Assignee: Materion Corporation
    Inventors: George Michael Wityak, Richard Koba
  • Patent number: 9000557
    Abstract: A device including a first layer of first transistors interconnected by at least one first interconnection layer, where the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, where the second layer is less than about 2 micron thick, where the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, where the connection path includes at least one through-layer via, where the at least one through-layer via is formed through and in direct contact with a source or drain of at least one of the second transistors.
    Type: Grant
    Filed: March 17, 2012
    Date of Patent: April 7, 2015
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 8872333
    Abstract: A millimeter wave integrated waveguide interface package device may comprise: (1) a package comprising a printed wiring board (PWB) and a monolithic microwave integrate circuit (MMIC), wherein the MMIC is in communication with the PWB; and (2) a waveguide interface integrated with the package. The package may be adapted to operate at high frequency and high power, where high frequency includes frequencies greater than about 5 GHz, and high power includes power greater than about 0.5 W.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: October 28, 2014
    Assignee: ViaSat, Inc.
    Inventors: Noel A Lopez, Michael R Lyons, Dave Laidig, Kenneth V Buer
  • Patent number: 8853006
    Abstract: A method of manufacturing a semiconductor device comprises a mounting step of mounting a semiconductor element having an Au—Sn layer on a substrate, wherein the mounting step includes a paste supplying step of supplying an Ag paste having an Ag nanoparticle onto the substrate, a device mounting step of mounting a side of the Au—Sn layer of the semiconductor element on the Ag paste, and a bonding step of alloying the Au—Sn layer and the Ag paste to bond the semiconductor element to the substrate, wherein the Au—Sn layer has a content rate of Au of 50 at % to 85 at %.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: October 7, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Syota Shimonishi, Hiroyuki Tajima, Yosuke Tsuchiya, Akira Sengoku
  • Patent number: 8772912
    Abstract: An electronic device includes a heat sink, a substrate mounted on the heat sink, a coating layer formed on the substrate, a lead frame fixed to the heat sink, and a mold resin sealing the substrate and the lead frame. The coating layer is made of one of a polyimide-based resin and a polyamideimide-based resin. The lead frame has a fixing terminal fixed to the heat sink through an adhesive layer. The adhesive layer is made of the same material as the coating layer.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: July 8, 2014
    Assignee: DENSO CORPORATION
    Inventors: Shotaro Miyawaki, Katsuhiko Kawashima, Atsushi Kashiwazaki, Takashi Yoshimizu
  • Patent number: 8742559
    Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: June 3, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Noriyuki Takahashi
  • Patent number: 8703286
    Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Saikumar Jayaraman, Paul A. Koning, Ashay Dani
  • Patent number: 8664752
    Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: March 4, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
  • Publication number: 20140001626
    Abstract: It is an object of the present invention to provide a semiconductor device capable of preventing deterioration due to penetration of moisture or oxygen, for example, a light-emitting apparatus having an organic light-emitting device that is formed over a plastic substrate, and a liquid crystal display apparatus using a plastic substrate. According to the present invention, devices formed on a glass substrate or a quartz substrate (a TFT, a light-emitting device having an organic compound, a liquid crystal device, a memory device, a thin-film diode, a pin-junction silicon photoelectric converter, a silicon resistance element, or the like) are separated from the substrate, and transferred to a plastic substrate having high thermal conductivity.
    Type: Application
    Filed: August 27, 2013
    Publication date: January 2, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Patent number: 8598458
    Abstract: An electronic device includes an electronic component, a joining member to be mechanically joined with the electronic component, and a metal conductor located between the electronic component and the joining member to mechanically join the electronic component and the joining member. The metal conductor is made of porous noble metal to have pores, and includes an end surface without being covered by the electronic component and the joining member. Furthermore, a reinforcing resin is impregnated from the end surface of the metal conductor to the pores inside of the metal conductor, so as to mechanically reinforce the metal conductor.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: December 3, 2013
    Assignee: DENSO CORPORATION
    Inventors: Hiroshi Ishino, Takao Izumi, Kazuhiro Tsuruta, Nobuyuki Kato
  • Patent number: 8587088
    Abstract: A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a vertical surface of the stack, as opposed to a top surface or adjacent of the stack to reduce the volume of the NVM package.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: November 19, 2013
    Assignee: Apple Inc.
    Inventor: Nicholas Seroff
  • Patent number: 8575657
    Abstract: A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 5, 2013
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Vincent Gambin, Rajinder Sandhu, Benjamin Poust, Michael Wojtowicz
  • Publication number: 20130241046
    Abstract: The present invention provides a ceramic heat sink material for a pressure contact structure configured by providing a resin layer on a ceramic substrate, wherein the resin layer has durometer (Shore) hardness (A-type) of 70 or less, and an average value of gaps existing in an interface between the ceramic substrate and the resin layer is 3 ?m or less. Further, it is preferable that the resin layer is formed by solidifying a thermosetting resin which is fluidized at a temperature of 60° C. Due to above structure, there can be obtained a ceramic heat sink and a semiconductor module using the heat sink having a good close-contacting property with respect to the pressing member.
    Type: Application
    Filed: November 17, 2011
    Publication date: September 19, 2013
    Applicants: TOSHIBA MATERIALS CO., LTD., KABUSHIKI KAISHA TOSHIBA
    Inventor: Kimiya Miyashita
  • Patent number: 8525342
    Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: September 3, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Arvind Chandrasekaran, Brian Henderson
  • Patent number: 8502373
    Abstract: By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: August 6, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Kenneth Kaskoun, Shiqun Gu, Matthew Nowak
  • Patent number: 8492202
    Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Ito, Toshiaki Ishii, Katsuo Arai, Takuya Nakajo, Hidemasa Kagii
  • Patent number: 8421219
    Abstract: A semiconductor component includes a semiconductor element that has a plurality of signals, a wiring board that is disposed below the semiconductor element and that draws the plurality of signals of the semiconductor element, a heat conduction member that dissipates heat generated by the semiconductor element, a joining member that is disposed between the semiconductor element and the heat conduction member and that joins the heat conduction member to the semiconductor element, a support member formed with an opening so as to surround the semiconductor element that supports the heat conduction member, a first adhesive member that is disposed between the support member and the wiring board to bond the support member with the wiring board and a second adhesive member that is disposed between the support member and the heat conduction member to bond the support member with the heat conduction member.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: April 16, 2013
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi So, Hideo Kubo, Seiji Ueno, Osamu Igawa
  • Patent number: 8415207
    Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: April 9, 2013
    Assignee: Infineon Technologies AG
    Inventors: Karsten Guth, Ivan Nikitin
  • Patent number: 8314484
    Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Ito, Toshiaki Ishii, Katsuo Arai, Takuya Nakajo, Hidemasa Kagii
  • Patent number: 8309979
    Abstract: A light emitting device is provided having high luminous output while maintaining high wall plug efficiency, wherein the high thermal and electrical conductivity paths of the device are separated during the semiconductor wafer and die level manufacturing step. The device includes an electrical conducting mirror layer, which reflects at least 60% of generated light incident on it, and an isolation layer having electrical insulating properties and thermal conducting properties. A first electrode, which is not in contact with the main semiconductor layers of the device, is located on the mirror layer. A light emitting module, system and projection system incorporating the light emitting device are also described, as is a method of manufacture of the device.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: November 13, 2012
    Assignee: PhotonStar LED Limited
    Inventors: James Stuart McKenzie, Majd Zoorob
  • Patent number: 8283773
    Abstract: A semiconductor device includes an insulating substrate having a ceramic substrate and metal coating layers on opposite surfaces of the ceramic substrate, a semiconductor chip mounted on one surface of the insulating substrate, a heat sink directly or indirectly fixed to the other surface of the insulating substrate and thermally connected to the semiconductor chip through the insulating substrate and at least one anti-warping sheet disposed on at least one surface of the heat sink. The anti-warping sheet is made of a metal sheet having a coating layer and has coefficient of thermal expansion between those of the insulating substrate and the heat sink.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: October 9, 2012
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Shogo Mori, Eiji Kono, Keiji Toh
  • Patent number: 8253233
    Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: August 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Karsten Guth, Ivan Nikitin
  • Patent number: 8232635
    Abstract: A hermetically sealed semiconductor package that includes a power semiconductor die having electrodes thereof electrically connected to the external surface mountable terminals of the package without the use of wirebonds.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: July 31, 2012
    Assignee: International Rectifier Corporation
    Inventor: Weidong Zhuang
  • Patent number: 8217512
    Abstract: A thermal interface device (100) includes a base member (102) and a pocket (104) which is filled with a thermally conductive material or medium such as diamond dust suspended in a solvent such as propylene glycol or a thermally conductive material such as thermally conductive rubber. The pocket (104) is hermitically sealed to the base member (102) in order to keep the thermally conductive material within the pocket. The filled pocket (104) forms a deformable “pillow” having a high thermal conductance. The deformable pocket (104) can contour to the shape of a device it is pressed against such as an electronic device undergoing testing.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: July 10, 2012
    Assignee: EADS North America, Inc.
    Inventors: Gary Carlson, Frank Landon, Jeffrey Chen, Mark Minot, Joseph Talbert
  • Patent number: 8193043
    Abstract: An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: June 5, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Oseob Jeon, Chung-Lin Wu, Eddy Tjhia, Bigildis C. Dosdos
  • Patent number: 8183088
    Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 22, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Byoung-Ok Lee
  • Patent number: 8080866
    Abstract: In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: December 20, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Michael Grillberger, Frank Feustel
  • Patent number: 8072065
    Abstract: A millimeter wave system or package may include at least one printed wiring board (PWB), at least one integrated waveguide interface, and at least one monolithic microwave integrated circuit (MMIC). The package may be assembled in panel form incorporating parallel manufacturing techniques.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: December 6, 2011
    Assignee: ViaSat, Inc.
    Inventors: Noel A. Lopez, Michael R. Lyons, Dave Laidig, Kenneth V. Buer
  • Patent number: 8035127
    Abstract: A packaging substrate structure with a semiconductor chip embedded therein is disclosed, including a carrier board having a first and an opposed second surfaces and disposed with at least a through cavity; a semiconductor chip received in the through cavity, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is disposed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are disposed on surfaces of the electrode pads; a buffer layer disposed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer disposed on the buffer layer; and a first circuit layer disposed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures disposed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expa
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: October 11, 2011
    Assignee: Unimicron Technology Corp.
    Inventors: Kan-Jung Chia, Shang-Wei Chen
  • Patent number: 8030754
    Abstract: One embodiment in accordance with the invention is a system that can include a first wafer and a second wafer. The first wafer and the second wafer can be bonded together by a wafer bonding process that forms a gap between the first wafer and the second wafer. The gap can be configured for receiving a heat extracting material.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: October 4, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter G. Hartwell, Duncan Stewart
  • Patent number: 8030757
    Abstract: In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 4, 2011
    Assignee: Intel Corporation
    Inventors: Mukul Renavikar, Daewoong Suh, Carl Deppisch, Abhishek Gupta
  • Patent number: 8022513
    Abstract: A packaging substrate structure with electronic components embedded therein and a method for fabricating the same are disclosed. The packaging substrate structure comprises a core board with a wiring layer on the two opposite surfaces thereof; a first built-up structure disposed on at least one surface of the core board and having a cavity to expose the surface of the core board; an electronic component disposed in the cavity and having an active surface and an inactive surface, where the active surface has pluralities of electrode pads and the inactive surface faces the surface of the core board; and a solder mask disposed on the surfaces of the first built-up structure and the electronic component, where the solder mask has pluralities of first openings to expose the electrode pads of the electronic component. Accordingly, the packaging substrate disclosed by the present invention can efficiently enhance electrical performance and product reliability.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: September 20, 2011
    Assignee: Unimicron Technology Corp.
    Inventor: Shih-Ping Hsu
  • Patent number: 7948075
    Abstract: A silicon nitride substrate having appropriately adjusted warpage and surface roughness can be obtained by mixing magnesium oxide of 3 to 4 wt % and at least one kind of rare-earth element oxide of 2 to 5 wt % with silicon nitride source material powder to form a sheet-molded body, sintering the sheet-molded body, and performing a heat treatment at a temperature of 1,550 to 1,700 degree C. with a pressure of 0.5 to 6.0 kPa with a plurality of substrates being stacked. Also, a silicon nitride circuit board and a semiconductor module using the same are provided.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: May 24, 2011
    Assignee: Hitachi Metals, Ltd.
    Inventors: Youichirou Kaga, Junichi Watanabe
  • Patent number: 7944711
    Abstract: The present invention relates to a substantially package-like discrete electronic component of the type comprising a power electronic circuit, a body or casing, substantially parallelepiped, and electric connecting pins connected inside the body with said circuit and projecting from said body for an electric connection on the electronic printed circuit board. The body has a heat dissipating header having at least one surface emerging from the body and laying on a plane whereas the pins project from the body for a first section initially extended parallel to the plane. Advantageously a pair of pins has a substantially U-shaped bending, after the first section parallel to the plane for allowing a more stable bearing of the component during the step of welding to a heat dissipating intermediate die.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: May 17, 2011
    Assignee: Askoll Holding S.r.l.
    Inventor: Elio Marioni
  • Patent number: 7923833
    Abstract: A semiconductor module 10 includes a ceramic substrate having a front surface on which a semiconductor element 12 is mounted and a rear surface on the opposite side of the front surface, a front metal plate 15 joined to the front surface, a rear metal plate 16 joined to the rear surface, and a heat sink 13 joined to the rear metal plate 16. The rear metal plate 16 includes a joint surface 16b that faces the heat sink 13. The joint surface 16b includes a joint area and a non-joint area. The non-joint area includes recesses 18 which extend in the thickness direction of the rear metal plate 16. The joint area of the rear metal plate 16 is in a range from 65% to 85% of the total area of the joint surface 16b on the rear metal plate 16. As a result, excellent heat dissipating performance can be achieved while occurrence of distortion and cracking due to thermal stress is prevented.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: April 12, 2011
    Assignees: Showa Denko K.K., Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Yuichi Furukawa, Shinobu Yamauchi, Nobuhiro Wakabayashi, Shintaro Nakagawa, Keiji Toh, Eiji Kono, Kota Otoshi, Katsufumi Tanaka
  • Patent number: 7911051
    Abstract: An electronic circuit arrangement includes a heat sink and a first circuit carrier which is thermally coupled to the heat sink, lies flat on the latter and is intended to wire electronic components of the circuit arrangement. Provided for at least one electronic component is a special arrangement which is associated with a considerably increased heat dissipation capability for the relevant component and, in addition, also affords further advantages in connection with changes in the population and/or line routing which might occur in practice. The important factor for this is that the component is arranged under a second circuit carrier which is held in a recess in the first circuit carrier. The recess passes through to the top side of the heat sink.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: March 22, 2011
    Assignee: Continental Automotive GmbH
    Inventors: Robert Ingenbleek, Erik Jung, Alfred Kolb, Andreas Rekofsky, Roland Schöllhorn, Daniela Wolf
  • Patent number: 7891836
    Abstract: The present invention relates to a light-emitting device comprising a substrate, a circuitry, a LED in electrical connection with said circuitry, and a heat sink arranged to transport heat away from the LED, wherein the LED is in thermal contact with said heat sink through an opening in said substrate. The present invention also relates to methods for the manufacture of such a device.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: February 22, 2011
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Ronald Dekker, Eduard Johannes Meijer, Eugene Timmering, Marc Andre De Samber
  • Patent number: 7880183
    Abstract: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: February 1, 2011
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Chung Hoon Lee, Hong San Kim, James S. Speck
  • Patent number: 7781236
    Abstract: An optical element mounting method includes: illuminating ultraviolet light onto a polymer optical waveguide device; under the ultraviolet light illumination, capturing, by an image pickup device, the polymer optical waveguide device including a light incident/exiting position of a waveguide core; and judging, from a difference between bright and dark in a captured image, that a portion brighter than other portions or a portion darker than other portions is the light incident/exiting position of the waveguide core.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: August 24, 2010
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Toshihiko Suzuki, Shigemi Ohtsu, Keishi Shimizu, Kazutoshi Yatsuda, Akira Fujii, Eiichi Akutsu
  • Patent number: 7777325
    Abstract: A power semiconductor module comprising: a power semiconductor element; a case for receiving the power semiconductor element; a control terminal which is connected to a control electrode of the power semiconductor element, the control terminal is installed in a state of protruding from an upper surface of the case; and a conductive spring which is inserted into the control terminal so that an inner surface of the spring makes contact with at least a part of the side surface of the control terminal, the conductive spring is electrically connected to a printed substrate placed as opposed to the upper surface of the case by making pressurization contact with the printed substrate.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: August 17, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Junji Yamada
  • Patent number: RE41559
    Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: August 24, 2010
    Assignee: International Rectifier Corporation
    Inventor: Charles S. Cardwell