Of High Thermal Conductivity Ceramic (e.g., Beo) Patents (Class 257/705)
  • Patent number: 7772609
    Abstract: LED packages are provided that include a material that is both thermally conductive and has a coefficient of thermal expansion that is matched to that of an LED. The material can be a ceramic such as aluminum nitride. The package has a body that includes a bottom surface and a cavity disposed into the body. The cavity has a floor for bonding to the LED so that the LED sits within the cavity. The thermally conductive material is disposed between the floor of the cavity and the bottom surface of the package. The body can be fabricated from a number of layers where the thermally conductive material is in a layer disposed between the floor and the bottom surface. The other layers of the body can also be fabricated from the thermally conductive material. A light emitting device is made by attaching the LED to the LED package.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: August 10, 2010
    Assignee: LedEngin, Inc. (Cayman)
    Inventor: Xiantao Yan
  • Patent number: 7772601
    Abstract: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: August 10, 2010
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Chung Hoon Lee, Hong San Kim, James S. Speck
  • Patent number: 7772602
    Abstract: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: August 10, 2010
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Chung Hoon Lee, Hong San Kim, James S. Speck
  • Patent number: 7755165
    Abstract: A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: July 13, 2010
    Assignee: Intel Corporation
    Inventors: Cengiz A. Palanduz, Dustin P. Wood
  • Patent number: 7750461
    Abstract: The invention relates to a metal-ceramic substrate for electric circuits or modules, said substrate including a ceramic layer which is provided with at least one metallic layer of a first type applied to a surface of said ceramic layer in a plane manner. An insulating layer made up of a glass-containing material is applied to at least one partial region of a surface of the metallic layer of the first type, said surface opposing the ceramic layer, and a metallic layer of a second type is applied to the insulating layer, the insulating layer and the metallic layer of a second type respectively being thinner then the ceramic layer and the metallic layer of the first type.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: July 6, 2010
    Assignee: Curamix Electronics GmbH
    Inventors: Jürgen Schulz-Harder, Peter Haberl
  • Patent number: 7671455
    Abstract: A multi chip housing has a lead frame to which plural die are soldered. A heat spreader conductive cap encloses a volume containing the plural die or chips and is fixed to the periphery of the lead frame. The die may be silicon or GaN based MOSFETs or integrated circuits or a mixture thereof. The tops of the die are closely spaced from the interior of the cap and the volume is filled with a thermally conductive, electrically insulating plastic encapsulant. One die can be connected to the clip as well as the lead frame and the other may be an IC die insulated from the clip.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: March 2, 2010
    Assignee: International Rectifier Corporation
    Inventor: Mark Pavier
  • Patent number: 7663242
    Abstract: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding component and an additive component which is a CTE modifying component and/or a thermal conductivity enhancement component. Active solders containing intrinsic oxygen getters.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: February 16, 2010
    Inventors: Brian G. Lewis, Bawa Singh, John P. Laughlin, David V. Kyaw, Anthony E. Ingham, Attiganal N. Sreeram, Leszek Hozer, Michael J. Liberatore, Gerard R. Minogue
  • Patent number: 7659614
    Abstract: A method of forming packages containing SiC or other semiconductor devices bonded to other components or conductive surfaces utilizing transient liquid phase (TLP) bonding to create high temperature melting point bonds using in situ formed ternary or quaternary mixtures of conductive metals and the devices created using TLP bonds of ternary or quaternary materials. The compositions meet the conflicting requirements of an interconnect or joint that can be exposed to high temperature, and is thermally and electrically conductive, void and creep resistant, corrosion resistant, and reliable upon temperature and power cycling.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: February 9, 2010
    Inventor: Vivek Mehrotra
  • Patent number: 7635916
    Abstract: An IC package that employs top-side conduction cooling. The IC package has a low thermal resistance between a substrate housed within the package and the lid of the package. Thermal resistance is decreased by increasing the conduction cross-sections laterally through the package and lid and vertically from the package into the lid. The lid may also be modified with an extended mesa portion that reduces the gap between the lid and the IC. A thermally conductive spacer may also be interposed between the IC and the lid. Also, the package housing body and lid may be made from high thermal conductivity materials having thermal conductivities of 50 W/mK or greater with matching CTE between the lid and the package.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: December 22, 2009
    Assignee: Honeywell International Inc.
    Inventors: Ronald J. Jensen, Richard K. Spielberger
  • Patent number: 7608917
    Abstract: A power semiconductor module and an inverter apparatus in which a device or a joining part is not mechanically damaged even when the temperature in use becomes a high temperature in the range of 175 to 250° C., resulting in excellent reliability at high temperature retaining test and thermal cycling test. Low thermal expansion ceramic substrates are disposed above and below the device. A material having a coefficient of thermal expansion of 10 ppm/K or less is disposed between the ceramic substrates. In addition, an inorganic material having a coefficient of thermal expansion in the range of 2 to 6 ppm/K or less is disposed around the device.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: October 27, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Kajiwara, Kazuhiro Suzuki, Toshiaki Ishii, Kazutoshi Itou
  • Patent number: 7582962
    Abstract: A heat dissipation device comprises a multilayer substrate, a channel formed in the multilayer substrate, and tubes disposed within the channel, the tubes suitable for removing heat from a heat generating device located adjacent to the multilayer substrate.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: September 1, 2009
    Assignee: Rockwell Collins, Inc.
    Inventor: Jeanne S. Pavio
  • Patent number: 7567599
    Abstract: A semiconductor laser diode device comprises a semiconductor laser diode, a primary lead having a sub-mount for mounting the semiconductor laser diode, at least one secondary lead electrically insulated from the primary lead, a first resin member for integrally fixing the primary lead and the secondary lead while insulating the primary lead from the secondary lead, and a second resin member having an emitting opening through which laser beams generated by the semiconductor laser diode are emitted to the outside, and surrounding the primary lead and the first resin member so as to dissipate heat transferred to the primary lead and the first resin member to the outside.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: July 28, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Chang Ho Song
  • Patent number: 7534649
    Abstract: Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use as a dielectric substrate or underfill. In another alternative, dendrimers/hyperbranched materials are synthesized by different methods to produce low viscosity, high Tg, fast curing, mechanically and chemically stable materials for imprinting applications.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Stephen E. Lehman, Jr., James C. Matayabas, Jr., Saikumar Jayaraman
  • Patent number: 7535714
    Abstract: An apparatus and method for creating a metallic thermal interface is shown for connecting an electronic module to a heat sink. Using an interface metal such as indium or malleable indium alloys, which have superior heat transfer capability, but are subject to oxidization and degraded thermal transfer capability; a layer of interface material is confined in a recess in the heat sink base into which the module cap is received. The thermal interface region is then evacuated to bring the module top surface and recess major surface into intimate contact and sealed along the interface of the module and recess side walls to exclude air from the metallic interface region.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventor: Arvind Kumar Sinha
  • Publication number: 20090091020
    Abstract: A co-fired ceramic module includes a ceramic substrate and at least one heat-emitting device. The ceramic substrate has at least one high thermal conductivity material. The heat-emitting device is disposed on the ceramic substrate. The substrate further includes a cavity and the heat-emitting device is disposed in the cavity.
    Type: Application
    Filed: April 21, 2008
    Publication date: April 9, 2009
    Inventors: Chih-Hung WEI, Yu-Ping HSIEH
  • Patent number: 7504670
    Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 17, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Satoshi Shiraishi, Yoichi Kazama
  • Patent number: 7498671
    Abstract: A semiconductor module of the present invention comprises a first conductive layer (film) and a second conductive layer (film) which are separately formed on the main surface of a packed substrate, a thermal diffusion plate connected by solder to the upper surface of the first conductive layer, a semiconductor element connected by solder to the upper surface of the thermal diffusion plate, and a lead having one end connected by solder to the second conductive layer and the other end connected by solder to the semiconductor element, wherein the outer periphery of the connected region where the semiconductor element is connected by solder to the upper surface of the thermal diffusion plate is formed with protrusion parts protruding up from the connecting region and a turning of the semiconductor element in the upper surface of the thermal diffusion plate in the solder connecting process is suppressed by the protrusion parts.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: March 3, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Fujiwara, Masahide Harada, Hideto Yoshinari, Shosaku Ishihara, Shiro Yamashita, Isamu Yoshida, Ukyo Ikeda
  • Patent number: 7466019
    Abstract: The semi-conducting support comprises a graphite substrate having a front surface and a rear surface and at least a first stack arranged on the front surface of the substrate. The first stack successively comprises a single-crystal diamond layer, an electrically insulating oxide layer and a semi-conducting layer. The support can comprise a second stack arranged on the rear surface of the substrate and comprising the same succession of layers as the first stack or comprising a polymer material layer. A thermal connection passing through the first and/or second stacks and connecting the graphite substrate to an external surface of the support enables heat to be removed. The method can comprise production of the semi-conducting layer by molecular bonding of rectangular silicon strips onto the oxide layer.
    Type: Grant
    Filed: November 24, 2005
    Date of Patent: December 16, 2008
    Assignee: Commissariat A l'Energie Atomique
    Inventor: Simon Deleonibus
  • Publication number: 20080272482
    Abstract: An IC package that employs top-side conduction cooling. The IC package has a low thermal resistance between a substrate housed within the package and the lid of the package. Thermal resistance is decreased by increasing the conduction cross-sections laterally through the package and lid and vertically from the package into the lid. The lid may also be modified with an extended mesa portion that reduces the gap between the lid and the IC. A thermally conductive spacer may also be interposed between the IC and the lid. Also, the package housing body and lid may be made from high thermal conductivity materials having thermal conductivities of 50 W/mK or greater with matching CTE between the lid and the package.
    Type: Application
    Filed: March 23, 2007
    Publication date: November 6, 2008
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Ronald J. Jensen, Richard K. Spielberger
  • Patent number: 7432591
    Abstract: A thermal enhanced structure comprising a packaged electronic device and a heat sink that is removably attached thereto. The thermal enhanced structure includes a plastic ball grid array (PGBA) with an electronic chip, a plastic mold cover, and a heat spreader with a plurality of spaced apart securing studs positioned and caulked at a periphery edge thereof. The mold cover, the heat spreader and studs are molded and embedded with one another to form a single unit with improved torque strength and heat dissipation. The single molded unit and the plastic ball grid array are secured together by an adhesive material. Then the heat sink can be easily and removably attached to the molded single unit by fastening elements to the molded studs, thereby allowing more efficient controllable forces or pressures to be applied as the mechanical fastening elements are removably attached to the molded studs to thereby prevent stress and damage to the PBGA package.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: October 7, 2008
    Assignee: International Business Machines Corporation
    Inventors: Yasuharu Yamada, Tsutomu Nakae
  • Patent number: 7429789
    Abstract: A dielectric composition for forming a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like, the composition including at least two fluoropolymers and two inorganic fillers. A circuitized substrate including at least one such dielectric layer and at least one conductive layer thereon is also provided.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: September 30, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas
  • Patent number: 7375412
    Abstract: A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: May 20, 2008
    Assignee: Intel Corporation
    Inventors: Cengiz A. Palanduz, Dustin P. Wood
  • Patent number: 7372700
    Abstract: A plasma display device which has improved performance of heat dissipation and noise/vibration insulation is disclosed. In one embodiment, the plasma display device includes a plasma display panel, a first base member coupled with the plasma display panel, a second base member connected to the first base member, and a thermally conductive cushion member interposed between the first base member and the second base member.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: May 13, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Woo-Man Jeong
  • Publication number: 20070267737
    Abstract: Packaged devices and methods of forming packaged devices are provided. At least one device is disposed on a substrate. The material layer encapsulates the device and covers at least a portion of the substrate, wherein the material layer comprises at least a first portion adjacent to the device and a second portion over the first portion. The second portion has a thermal conductivity higher than a thermal conductivity of the first portion.
    Type: Application
    Filed: May 17, 2006
    Publication date: November 22, 2007
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Hsueh-Chung Chen, Yi-Lung Cheng
  • Patent number: 7297988
    Abstract: The present invention relates to a flip chip type nitride semiconductor light emitting device having p-type and n-type nitride semiconductor layers, and an active layer in between. The invention also has an ohmic contact layer formed on the p-type nitride semiconductor layer, a light-transmitting conductive oxide layer formed on the ohmic contact layer, and a highly reflective metal layer formed on the light-transmitting conductive oxide layer.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: November 20, 2007
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wan Chae, Suk Kil Yoon, Kun Yoo Ko, Hyun Wook Shim, Bong Il Yi
  • Patent number: 7294925
    Abstract: An optical scanner package having a heating dam is provided. The optical scanner package having a heating dam includes: an optical scanner on which a mirror surface is formed; a ceramic package in which the optical scanner is installed at the bottom of a cavity thereof; a glass lid covering a sidewall of the ceramic package; a heating dam formed on the sidewall of the ceramic package; and solder on the heating dam sealing between the glass lid and the sidewall of the ceramic package. The heating dam locally heats the solder to form hermetic sealing.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-kyoung Choi, Young-chul Ko
  • Patent number: 7250323
    Abstract: A method of making an energy conversion device includes forming a plurality of pores within a substrate and forming a junction region within each of the plurality of pores. Each of the junction regions has a depletion region and each of the plurality of pores defines an opening size in the substrate and a spacing from adjacent pores so that the depletion regions of each of the pores is at least substantially in contact with the depletion region of the pores which are adjacent.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: July 31, 2007
    Assignees: Rochester Institute of Technology, University of Rochester, BetaBatt Inc.
    Inventors: Larry L. Gadeken, Wei Sun, Nazir P. Kherani, Philippe M. Fauchet, Karl D. Hirschman
  • Patent number: 7230320
    Abstract: In an electronic circuit device including a substrate including a front surface on which an electronic circuit element is mounted and a reverse surface opposite to the front surface in a thickness direction of the substrate, an electrically conductive terminal member electrically connected to the electronic circuit element, a lead frame extending perpendicular to the thickness direction to face the reverse surface in the thickness direction, and a sealing resin covering at least partially the electronic circuit element, substrate and lead frame while at least a part of the electrically conductive terminal member is prevented from being covered by the sealing resin, the substrate extends to project outward from an end of the lead frame in a transverse direction perpendicular to the thickness direction while the end of the lead frame is covered by the sealing resin.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: June 12, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Doi, Noriyoshi Urushiwara, Akira Matsushita
  • Patent number: 7224057
    Abstract: A thermal enhance semiconductor package with a universal heat spreader mainly comprises a carrier, a semiconductor chip and a universal heat spreader. The semiconductor chip is electrically connected to the carrier in a flip-chip fashion and the universal heat spreader is mounted on the back surface of the semiconductor chip. Therein the universal heat spreader has a plurality of through holes for upgrading the efficiency of heat transmission. Moreover, a heat transmission pin is provided in one of the through holes to increase the areas for heat dissipation so as to enhance the thermal performance of the package.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: May 29, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Ching-Hsu Yang
  • Patent number: 7221048
    Abstract: A multilayer circuit carrier, electronic devices and panel, and a method for producing a multilayer circuit carrier include at least one semiconductor chip, at least one rewiring layer with a rewiring structure, and at least one insulation layer, which has passage structures.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: May 22, 2007
    Assignee: Infineon Technologies AG
    Inventors: Frank Daeche, Jochen Dangelmaier, Stefan Paulus, Bernd Stadler, Horst Theuss, Michael Weber
  • Patent number: 7211891
    Abstract: There is provided a small-size electronic heat pump device which is low in power consumption and which secures a vacuum gap without use of an additional circuit. The electronic heat pump device includes an emitter 1 and a collector 2. An electrically and thermally insulative spacer section 5 for keeping a space, i.e. vacuum gap G between an emitter electrode 11 and a collector electrode 21 constant is integrally formed in a semiconductor substrate 20 of the collector 2, which makes it possible to maintain the vacuum gap to be a specified space while a back flow of heat is prevented in a simple structure with a reduced number of component parts.
    Type: Grant
    Filed: November 26, 2004
    Date of Patent: May 1, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenji Shimogishi, Yoshihiko Matsuo, Yoichi Tsuda
  • Patent number: 7208829
    Abstract: A semiconductor component that is able to be produced simply, quickly, and yet reliably and that usable for power applications, and including a semiconductor chip, a lower, first main electrode layer formed on a first side of the semiconductor chip, a lower control electrode layer formed on the first side, an insulation layer formed on the first side between the lower first main electrode layer and the lower control electrode layer and which partly covers the lower first main electrode layer, an upper first main electrode layer which is formed on the lower first main electrode layer, an upper control electrode layer which is formed on the lower control electrode layer and the insulation layer and extends on the insulation layer partially above the lower first main electrode layer, and a second main electrode layer formed on a second side of the semiconductor chip.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: April 24, 2007
    Assignee: Robert Bosch GmbH
    Inventors: Henning Hauenstein, Rainer Topp, Jochen Seibold, Dirk Balszunat, Stefan Ernst, Wolfgang Feiler, Thomas Koester, Stefan Hornung, Dieter Streb
  • Patent number: 7205650
    Abstract: In a composite device of the laminate type having a laminate structure of a composite ceramic layer and a dielectric ceramic layer, the composite ceramic layer including a layer portion having the same composition as the dielectric ceramic layer and a plurality of particle portions formed on the surface of the layer portion. The particle portions are made from magnetic ceramic material. This prevents the ceramic layers of the device from cracking and separating when fired.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: April 17, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideki Yoshikawa, Takashi Umemoto, Hitoshi Hirano
  • Patent number: 7166914
    Abstract: A packaged semiconductor chip including the chip, and a package element such as a heat sink is made by connecting flexible leads between contacts on the chip and terminals on a dielectric element such as a sheet or plate and moving the sheet or plate away from the chip, and injecting a liquid material to form a compliant layer filling the space between the package element and the dielectric element, and surrounding the leads. The dielectric element and package element extend outwardly beyond the edges of the chip, and physically protect the chip. The assembly may be handled and mounted by conventional surface mounting techniques. The assembly may include additional circuit elements such as capacitors used in conjunction with the chip.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: January 23, 2007
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Tony Faraci
  • Patent number: 7164199
    Abstract: A microelectromechanical device package and a low-stress inducing method for packaging a microelectromechanical device are disclosed in this invention. The microelectromechanical device is accommodated within a cavity comprised by a first package substrate and a second substrate, wherein a third substrate is disposed between and bonded to both the microelectromechanical device lower semiconductor substrate and the package bottom substrate. The first and second package substrates are then bonded so as to package the microelectromechanical device inside.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: January 16, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Terry Tarn
  • Patent number: 7144757
    Abstract: This invention relates to a vertically integratable circuit and a method for producing same. Unlike known methods for producing vertical electric connections, the present method uses process steps in the production of the vertically integratable circuit itself to permit vertical integration. This simplifies the sequence of production for vertically integratable circuits and thus the three-dimensional integrated circuit as a whole, thereby optimizing plant running times since process steps are saved. Because finished substrates are no longer the starting point for producing the vertical electric connections, an improved yield is moreover obtained since no process steps which could in particular change the already produced active circuit elements, such as steps with high process temperatures, are necessary any longer after production of the circuit elements.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: December 5, 2006
    Assignee: Giesecke & Devrient GmbH
    Inventor: Thomas Grassl
  • Patent number: 7135768
    Abstract: Ultrasonically formed seals, their use in semiconductor packages, and methods of fabricating semiconductor packages. A brittle center member (such as glass) has a molded edge member. That edge member is ultrasonically welded to a body. The molded edge member and body are comprised of ultrasonically weldable materials. A hermetically sealed semiconductor package includes a lid with a brittle center plate and a molded edge. The molded edge is ultrasonically welded to a body. Locating features that enable accurate positioning of the lid relative to the body, and energy directors can be included. Pins having a relieved portion and a protruding portion can also be hermetically sealed to the body. Such pins can have various lengths that enable stadium-type pin rows. The pins can be within channels, which can hold a sealant. The body can include a device that is electrically connected to the pins.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: November 14, 2006
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Matthew E. Doty
  • Patent number: 7105920
    Abstract: A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated by forming a recess in a substrate, such as a multi-layer substrate formed of organic dielectric materials. A ceramic layer is then affixed to the substrate in the recess. A die may be attached to the ceramic layer and the substrate may be attached to a printed circuit board.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: September 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Yuan Su, Chen-Der Huang, Pei-Haw Tsao, Chuen-Jye Lin
  • Patent number: 7067903
    Abstract: A semiconductor device and package has a heat spreader directly disposed on the reverse surface of the semiconductor device. This heat spreader includes a diamond layer or a layer containing diamond and ceramics such as silicon carbide and aluminum nitride. The heat spreader is directly formed on a substrate for the semiconductor device. In particular, the heat spreader is composed of a diamond layer and one or two metal or ceramic members, which are bonded to the diamond layer with one or two polymer adhesive layers. This diamond layer has a fiber structure across the thickness or a microcrystalline structure. Cilia are formed on a surface of the diamond layer facing the one or two metal or ceramic members.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: June 27, 2006
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Takeshi Tachibana, Kazushi Hayashi, Kenichi Inoue, Yoshihiro Yokota, Koji Kobashi, Nobuyuki Kawakami, Takashi Kobori
  • Patent number: 7053493
    Abstract: A semiconductor device including a substrate, a semiconductor element mounted on the substrate and a stiffener attached via an adhesive to a surface of the substrate opposite a surface thereof on which the semiconductor element is mounted. The adhesive has a coefficient of thermal expansion smaller than that of the substrate and that of the stiffener, and the modulus of longitudinal elasticity of the adhesive is equal to or larger than 10 GPa. Otherwise, the adhesive has a coefficient of thermal expansion larger than that of the substrate and that of the stiffener, and the modulus of longitudinal elasticity of the adhesive is equal to or smaller than 10 GPa. The height of the stiffener is less than that of the external terminals.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: May 30, 2006
    Assignee: Fujitsu Limited
    Inventors: Takashi Kanda, Kenji Fukuzono
  • Patent number: 7049695
    Abstract: A structure and method are provided for dissipating heat from a semiconductor device chip. A first layer of a dielectric material (e.g. polyimide) is formed on a front side of a heat spreader (typically Si). A plurality of openings are formed through this first layer; the openings are filled with metal (typically Cu), thereby forming metal studs extending through the first layer. A second layer of metal is formed on the backside of the device chip. The first layer and the second layer are then bonded in a bonding process, thereby forming a bonding layer where the metal studs contact the second layer. The bonding layer thus provides a thermal conducting path from the chip to the heat spreader.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: May 23, 2006
    Assignee: International Business Machines Corporation
    Inventor: H. Bernhard Pogge
  • Patent number: 7023089
    Abstract: Some embodiments disclose a low temperature semiconductor packaging apparatus and method. An apparatus generally comprises a heat spreader, a silicon die, and a thermal interface material disposed between the heat spreader and the silicon die comprising a plurality of metals capable of forming a transient liquid phase bond. A method generally comprises attaching a silicon die to a substrate, depositing a thermal interface material on at least one of the silicon die and a heat spreader, and attaching the heat spreader to the silicon die, wherein the thermal interface material comprises a plurality of metals capable of forming a transient liquid phase bond. Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: April 4, 2006
    Assignee: Intel Corporation
    Inventor: Daoqiang Lu
  • Patent number: 7005738
    Abstract: The invention provides a semiconductor package having a substrate, a top surface and at least one semiconductor device attached to the top surface of the substrate. A cover is secured to the substrate creating a space between the cover and the substrate, with the semiconductor device residing within the space. The cover includes an inner chamber that is defined by an upper wall and a lower wall of the cover. The cavity contains a two-phase vaporizable liquid and a wick. Advantageously, the wick on the lower wall includes at least one recess that forms a thinned wall adjacent to a high heat generation portion of the semiconductor device. In one embodiment, the wick on the lower wall includes at least one channel that communicates with at least one of the recesses.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 28, 2006
    Assignee: Thermal Corp.
    Inventors: Jon Zuo, Donald M. Ernst
  • Patent number: 7002247
    Abstract: A thermal interposer is provided for attachment to the back surface of a semiconductor device so as to give a very low thermal resistance. In one preferred embodiment, the thermal interposer has two plates containing wick structures such as grooves. The thermal interposer is integrated with a semiconductor device so as to form a vapor chamber. In particular, the back surface of the semiconductor chip is in direct contact with the interior sealed volume of the vapor chamber, so as to greatly reduce the thermal resistance from the combination of the chip and the vapor chamber. Further, the upper plate is thermally coupled to a heat-sinking fixture such as a heat sink or a cold plate.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: February 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Lawrence S. Mok, Evan G. Colgan, Minhua Lu, Da-Yuan Shih
  • Patent number: 6987315
    Abstract: A ceramic multilayer substrate includes a plurality of ceramic substrates being stacked vertically, each substrate having a designated thickness; pattern layers formed on surfaces of the ceramic substrates so as to form circuit elements; external terminal vertically formed on side surfaces of the stacked ceramic substrates; and internal connection parts, each of which is formed on a part of one of the pattern layers, is connected to one of the external terminals so as to exchange signals with the outside, and is broad enough to surround at least partially the connected external terminal.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: January 17, 2006
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seok Taek Jun, Myoung Lib Moon, Duk Woo Lee
  • Patent number: 6953291
    Abstract: A hermetically sealed, opto-electronic array housing assembly having a ceramic base, electrical connectors, a metal can, and a glass window. The glass window can support a micro-lens array. The metal can receives the glass window. The electrical impedance of the electrical connectors is beneficially carefully controlled to enable high-speed data communications. A multi-element optical fiber connector can provide for optical communications to and/or from an opto-electronic array contained within the housing.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: October 11, 2005
    Assignee: Finisar Corporation
    Inventor: Yue Liu
  • Patent number: 6921969
    Abstract: The semiconductor module comprises a base element (1), an insulating element (2), which is metallized on both sides and rests on the base element by one of the two metallizations, and at least one semiconductor element (6) arranged on the other of the two metallizations. An electrically insulating layer (51) is arranged in the edge region of the insulating element (2), the surface of this insulating layer forming a common planar surface with the surface of the second metallization. The blunting of the edges and corners of the metallization by level embedding of the entire metallized insulating element improves the insulating property of semiconductor module in the area of the critical electrical field region. Moreover, the arrangement in one plane permits simple and low-cost production.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: July 26, 2005
    Assignee: ABB Research Ltd.
    Inventor: Wolfgang Knapp
  • Patent number: 6919630
    Abstract: A semiconductor package with an embedded heat spreader (EHS) is proposed, which can be used for the fabrication of a semiconductor package, such as a FCBGA (Flip-Chip Ball Grid Array) package with a heat spreader, and which is characterized by the provision of a plurality of recessed portions, either in the heat spreader attach area of the substrate, or in the support portion of the heat spreader, or in both, so as to allow the fill-in portions of the adhesive layer that are filled in these recessed portions to form anchor structures to benefit the heat spreader against crosswise shear stress. Moreover, since the provision of these recessed portions allows an increase in the contact area of the adhesive layer with the substrate and the heat spreader, it can help increase the adhesive strength to provide the heat spreader more securely adhered in position on the substrate.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: July 19, 2005
    Assignee: Siliconware Precision Industries Co. Ltd.
    Inventor: Cheng-Hsu Hsiao
  • Patent number: 6914325
    Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: July 5, 2005
    Assignee: Fuji Electric Co. Ltd.
    Inventors: Takatoshi Kobayashi, Tadashi Miyasaka, Katsumi Yamada, Akira Morozumi
  • Patent number: 6894373
    Abstract: Thin film circuit elements including capacitors, resistors, and inductance elements are formed on a large substrate, and semiconductor chips are wire bonded to the substrate. The elements and chips are sealed by potting a sealing resin. The large substrate is divided into multiple stripe substrates by dicing and a thin-film conductive layer is sputtered on cut surfaces of the stripe substrates, thereby electrically connecting edges of lower conductive patterns to edges of upper conductive patterns exposed from side surfaces of the sealing resin through the thin-film conductive layer. A Ni foundation layer and Au layer are successively plated on a surface of the thin-film conductive layer to form edge electrodes on side surfaces of the stripe substrates and the stripe substrates are divided finely into individual alumina substrates.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: May 17, 2005
    Assignee: Alps Electric Co., Ltd.
    Inventors: Kazuhiko Ueda, Seiichi Yokoyama