Of High Thermal Conductivity Ceramic (e.g., Beo) Patents (Class 257/705)
  • Patent number: 5798566
    Abstract: In accordance with the present invention, there is provided a ceramic IC package base which comprises a ceramic substrate, and a heat radiating member adhered to a side surface of the ceramic substrate and made of copper or copper alloy. The heat radiating member has an adhering portion at which it is adhered to the ceramic substrate. The adhering portion, when the heat radiating member is observed in a plan view, has one side which is equal to or larger than 8 mm. The adhering portion is of the thickness within the range from 0.25 mm to 0.76 mm. A ceramic IC package cover is also provided.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: August 25, 1998
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Kazuhisa Sato, Masanori Kitou, Hisashi Wakako, Kazuo Kimura
  • Patent number: 5798570
    Abstract: In construction of a plastic molded semiconductor package incorporating a metallic heat sink, the heat sink is made of a thin plate but provided with a central die support depressed from the plane of a surrounding lead support, the section opposite the die support being exposed outside a plastic package. Use of a thin plate as the material enables efficient, continuous processing in production. Presence of the depressed die support assures elongated boundary between the heat sink and the plastic package, thereby effectively reducing undesirable invasion of outer contaminant.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: August 25, 1998
    Assignee: Kabushiki Kaisha Gotoh Seisakusho
    Inventors: Norinaga Watanabe, Shinichi Nishi
  • Patent number: 5792984
    Abstract: An aluminum nitride housing is molded which includes open holes that pass through the walls. A lead frame is formed by machining or chemically milling individual leads and details therein to form desired circuitry patterns. The lead frame is inserted through the open holes in the aluminum nitride housing and chemically and mechanically bonded thereto using active braze The active braze attaches the lead frame not only to the open holes in the package, but also to the wall of the housing over a larger area. Active braze forms a strong bond between the aluminum nitride and the lead frame, and also forms an excellent and highly reliable thermal junction therebetween. Several different package constructions are illustrated. In one design the aluminum nitride takes on a bathtub configuration onto which a flat cover may be attached.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: August 11, 1998
    Assignee: CTS Corporation
    Inventor: Terry R. Bloom
  • Patent number: 5777385
    Abstract: An improved package structure for integrated-circuit chips is disclosed. In accordance with a preferred embodiment of the present invention, the integrated-circuit packaged structure comprises a wiring substrate, an integrated-circuit chip, and a heat spreader. The integrated-circuit chip has a first surface and a second surface, wherein the first surface is electrically and mechanically connected to the wiring substrate via a first set of solder joints. The heat spreader is connected to the second surface of the integrated-circuit chip via a second set of solder joints. The heat spreader includes an adhesion-promotion layer on top of a silicon layer, such that heat generated from the integrated-circuit chip can be efficiently transmitted to and subsequently dissipated by the heat spreader.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: July 7, 1998
    Assignee: International Business Machines Corporation
    Inventor: Leon Li-Heng Wu
  • Patent number: 5760466
    Abstract: A semiconductor device including an insulating substrate which has a semiconductor element-mounting portion for mounting a semiconductor element on the center of its top surface, and a plurality of metallized wiring layers which lead outward extendedly from the periphery of the semiconductor element-mounting portion to the rim of the top surface; a semiconductor element which is mounted on the semiconductor element-mounting portion and has electrodes connected to the inner end sections of the metallized wiring layers; a plurality of outer lead terminals which are attached to the outer end sections of the metallized wiring layers to connect the semiconductor element to an exterior electric circuit; and a molding resin which covers the insulating substrate, the semiconductor element and part of the outer lead terminals.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: June 2, 1998
    Assignee: Kyocera Corporation
    Inventors: Kenji Masuri, Yoshihiro Hosoi, Hisashi Kojima, Kazuhito Imuta, Hiroshi Matsumoto
  • Patent number: 5757081
    Abstract: An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: May 26, 1998
    Assignee: Siliconix Incorporated
    Inventors: Mike F. Chang, King Owyang, Fwu-Iuan Hshieh, Yueh-Se Ho, Jowei Dun
  • Patent number: 5744848
    Abstract: A photosemiconductor device-housing package comprising a metal substrate; an insulating support member on the top surface of which a photosemiconductor device is mounted; a metal frame member attached onto the metal substrate so as to surround the insulating support member and having a fixing region through its side face which fixes an optical fiber therein; outer lead terminals fixed in the metal substrate or the metal frame member via insulants; and a metal lid member attached to the top surface of the metal frame member to hermetically seal the photosemiconductor device, wherein the insulating support member is composed of an aluminum nitride-based sinter, the top surface of the insulating support member is coated with a thin-film brazing material, and the photosemiconductor device is fixed onto the insulating support member via the brazing material.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: April 28, 1998
    Assignee: Kyocera Corporation
    Inventor: Masaaki Harazono
  • Patent number: 5744863
    Abstract: An aluminum or copper heat sink is attached to a ceramic cap or exposed semiconductor chip using flexible-epoxy to provide improved thermal performance. The aluminum may be coated by anodizing or chromate conversion or the copper may be coated with nickel. Such structures are especilly useful for CQFP, CBGA, CCGA, CPGA, TBGA, PBGA, DCAM, MCM-L, single layer ceramic, and other chip carrier packages as well as for flip chip attachment to flexible or rigid organic circuit boards. These adhesive materials withstand thermal cycle tests of 0.degree. to 100.degree. C. for 1,500 cycles, -25.degree. to 125.degree. C. for 400 cycles, and -40.degree. to 140.degree. C. for 300 cycles; and withstand continuous exposure at 130.degree. C. for 1000 hours without loss of strength. Flexible-epoxies have a modulus of elasticity below 100,000 psi and a glass transition temperature below 25.degree. C., are much stronger than typical silicone adhesives, and do not contaminate the module or circuit board with silicone.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 28, 1998
    Assignee: International Business Machines Corporation
    Inventors: Thomas Moran Culnane, Michael Anthony Gaynes, Ping Kwong Seto, Hussain Shaukatullah
  • Patent number: 5723880
    Abstract: Thin films of 2H .alpha.-silicon carbide are produced by pulsed laser ablation.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 3, 1998
    Assignee: Kent State University
    Inventors: Mark Anthony Stan, Martin Owen Patton, Joseph Dale Warner
  • Patent number: 5706579
    Abstract: An integrated circuit package capable of carrying high wattage and efficiently dissipating heat generated by the die is fabricated from a die, printed wiring board and metal lid, with a beta-stageable resin which is preapplied to the lid and which contains a thermally conductive filler material. With the lid in place over the die and substrate board, the package is heated to cause the resin to flow and establish contact with the die. Further heating causes curing of the resin and a permanent thermal bridge between the die and the lid.
    Type: Grant
    Filed: April 9, 1996
    Date of Patent: January 13, 1998
    Assignee: RJR Polymers, Inc.
    Inventor: Richard J. Ross
  • Patent number: 5703397
    Abstract: A semiconductor ceramic multilayer package comprising an aluminum nitride substrate having a semiconductor element mounted on one surface thereof and a wiring pattern electrically connected to the semiconductor element, connecting terminals connected to the wiring pattern and disposed on the other surface of the aluminum nitride substrate, and a sealing member connected to the aluminum nitride substrate with a metallic bonding layer or a glass layer having a thickness of not more than 100 .mu.m in such a manner as to seal the semiconductor element possesses a notably improved heat-radiating property and accomplishes the object of increasing the number of pins and reducing the size of package.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: December 30, 1997
    Inventors: Mitsuyoshi Endo, Hironori Asai, Keiichi Yano, Yoshitoshi Sato
  • Patent number: 5698896
    Abstract: A high thermal conductive silicon nitride structural member of the present invention contains a rare earth element in the range of 1.0 to 7.5 wt. % calculated as oxide thereof and Li, Na, K, Fe, Ca, Mg, Sr, Ba, Mn and B as impurity cationic elements in a total amount not greater than 0.3 wt. %, and has the thermal conductivity not less than 60 W/(m.K), preferably not less than 80 W/(m.K). Also, a high thermal conductive silicon nitride sintered body consists of silicon nitride particles and a grain boundary phase, a crystal compound phase in the grain boundary phase being not less than 20 vol. %, preferably not less than 50 vol. %, with respect to the entire grain boundary phase, and has the thermal conductivity not less than 60 W/(m.K), preferably not less than 80 W/(m.K).
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: December 16, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michiyasu Komatsu, Yoshitoshi Sato, Katsuhiro Shinosawa, Mineyuki Yamaga
  • Patent number: 5682063
    Abstract: The present invention relates to a substrate for a semiconductor device having a diamond base material and a multisublayer wiring layer on the diamond base material, wherein the diamond base material is a diamond layer prepared by vapor phase deposition. The multisublayer wiring layer has at least one insulating sublayer having a relative dielectric constant of not larger than 5 or at least 12 and at least one metal wiring sublayer. The present invention is particularly useful as a substrate for a high performance, high-speed operation semiconductor device.
    Type: Grant
    Filed: January 5, 1996
    Date of Patent: October 28, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiyuki Yamamoto, Takahiro Imai, Naoji Fujimori
  • Patent number: 5675181
    Abstract: A ceramic substrate is a high-temperature fired body consisting of alumina as the main component, zirconia, and a ceramics sintering assisting agent. The assisting agent is one of yttria, calcia, magnesia, and ceria, in which yttria is added at 0.1-2 wt %, calcia is added at 0.02-0.5 wt %, magnesia is added at 0.02-0.4 wt %, and ceria is added at 0.02-0.5 wt %.
    Type: Grant
    Filed: January 19, 1996
    Date of Patent: October 7, 1997
    Assignees: Fuji Electric Co., Ltd., Sumitomo Metal Ceramics Inc.
    Inventors: Masaharu Nishiura, Shigemasa Saito, Akira Morozumi, Shizuyasu Yosida, Katumi Yamada, Toshio Nozaki, Hiroshi Miyama, Seigo Oiwa, Kazuya Matuura, Kazuhiko Teramura
  • Patent number: 5654586
    Abstract: In a power semiconductor component a ceramic substrate (SUB) and a metallic baseplate (BP) are connected, in order, via a connecting layer (2), a buffer layer (DP) made of a material having a low yield point and high thermal conductivity as well as a further connecting layer (3). The mechanical connections between the ceramic substrate and the baseplate have a high shear strength. Premature material fatigue and cracking on account of the different thermal expansion of the ceramic substrate and the baseplate are avoided by means of plastic deformation of the buffer layer. Connecting layers are, for example, sintered silver powder layers such as are advantageously used in the low-temperature connection technique for power semiconductor components.
    Type: Grant
    Filed: November 7, 1995
    Date of Patent: August 5, 1997
    Assignee: Siemens Aktiengesellschaft
    Inventor: Herbert Schwarzbauer
  • Patent number: 5644163
    Abstract: In a semiconductor device, a heat sink is fitted in an opening in a ceramics plate and a semiconductor element is mounted on the heat sink. A cap is fixed by a sealing ring to the surface of the ceramics plate so as to protect the semiconductor element. Connection pins are provided on the outer marginal surface portion of the ceramics plate. The opening of the ceramics plate is square in configuration and has a curvature radius R of R=1.0 mm at its corners, that is, has no angular corners, so that stress, being produced at the corner, is relieved.
    Type: Grant
    Filed: March 11, 1996
    Date of Patent: July 1, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ken-ichiro Tsuji
  • Patent number: 5640045
    Abstract: A packaging system for minimizing thermal-induced stress in a high power semiconductor device. The system is comprised of an electrically insulating, thermally conductive substrate having planar upper and lower surfaces, a semiconductor die having a planar lower heat extraction surface attached to said upper surface of said substrate, and electrically insulating thermal compound disposed between and in contact with the said lower heat extraction surface of said substrate and the system heat extraction upper surface. .DELTA.L.varies..DELTA.S is defined in Equation 12, wherein T.sub.B is the temperature at said outer edge of the lower heat extraction surface of said die, T.sub.D is the temperature at said outer edge of the lower surface of said substrate, and PPM is part per million.
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: June 17, 1997
    Assignee: Directed Energy, Inc.
    Inventor: George J. Krausse, III
  • Patent number: 5635761
    Abstract: Thin-film conductor technology is utilized to form resistors of precisely controlled value within the interior of multi-chip modules to properly terminate network circuits which interconnect one or more chips with either output pin connections or other chips on the multi-chip module. By forming and disposing the resistors within the interior of the multi-chip module, the terminating resistors may be manufactured during the multi-chip module manufacturing process. This approach preserves valuable surface area available for interconnecting the computer chips to the multi-chip module rather than consuming scarce surface area with termination resistors and other circuit elements necessary to adapt the multi-chip module and the other computer chips to each other.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: June 3, 1997
    Assignee: International Business Machines, Inc.
    Inventors: Tai A. Cao, Herbert I. Stoller, Thanh D. Trinh, Lloyd A. Walls
  • Patent number: 5627408
    Abstract: A semiconductor substrate is positioned in a cavity formed at the center of the major surface of a mounting portion. A plurality of inner leads comprising signal leads and power supply leads are arranged along the peripheral area of the major surface of the mounting portion, with their ends opposed to the semiconductor substrate. The inner leads are connected to the semiconductor substrate by way of bonding wires. All of the bonding wires connecting the signal leads to the semiconductor substrate have substantially the same length. The inner leads are formed on the surfaces of the ceramic layers that are partially laid one on the other to form a multilayer structure. The ceramic layer supports the signal leads and has a polygonal opening or cavity, the number of the corners of which is greater than that of the mounting portion.
    Type: Grant
    Filed: May 18, 1995
    Date of Patent: May 6, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Megumi Kusumi
  • Patent number: 5625226
    Abstract: One surface of a metal heat transfer slug contacts the surface of a semiconductor die which contains junction diffusions. The slug and die are molded into a surface mount package which exposes the opposite surface of the slug. Terminal leads are internally connected to the junction diffusions and extended beyond the molded periphery of the package.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: April 29, 1997
    Assignee: International Rectifier Corporation
    Inventor: Daniel M. Kinzer
  • Patent number: 5616956
    Abstract: Disclosed is a circuit substrate and a semiconductor device to which the circuit substrate is applied. The circuit substrate has an insulating layer and an electrically conductive layer. The insulating layer is composed of a sintered aluminum nitride composition containing: aluminum nitride; a first component given by a compound containing an element which is selected from the group consisting of group IIa elements and group IIIa elements of the periodic table; a second component given by either a simple boron or a boron compound; and a third component give by either a simple manganese or a manganese compound. The electrically conductive layer contains: a conductive component given by a metal or an electrically conductive compound for exhibiting electric conductivity; aluminum nitride; the first component; the second component; and the third component.
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: April 1, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Horiguchi, Jun Monma, Kazuo Kimura, Katsuyoshi Oh-Ishi, Fumio Ueno, Mitsuo Kasori, Hiroyasu Sumino
  • Patent number: 5576578
    Abstract: An insulating disk composed of electrically insulating and thermally conducting material. The disk has one side provided with a central recess having a cross section which is equal to a cross section of a component arranged adjacent to the disk. Consequently, the value of the extinction voltage of the partial discharge and the creeping-discharge and flashover resistance are substantially increased. Circumferential grooves and/or ribs can also be provided on the surface of the disk.
    Type: Grant
    Filed: May 16, 1994
    Date of Patent: November 19, 1996
    Assignee: Siemens Aktiengesellschaft
    Inventors: Wolfgang Fuhrer, Olaf Niermeyer, Gyorgy Papp
  • Patent number: 5574312
    Abstract: In the case of a power semiconductor module (1) according to the invention, substrates (8) having a power semiconductor assembly (2) are fitted on both sides of a heat sink (3). The power semiconductor assemblies (2) are made contact with by a stack of contact laminates (4), which contact laminates (4) run parallel to the heat sink (3). A very low-inductance structure is obtained thereby.
    Type: Grant
    Filed: May 5, 1995
    Date of Patent: November 12, 1996
    Assignee: ABB Management AG
    Inventors: Reinhold Bayerer, Thomas Stockmeier
  • Patent number: 5567985
    Abstract: Differences in thermal expansion properties between integrated circuit chips, especially of gallium arsenide, and the dielectric substrates (especially diamond and aluminum nitride) on which said chips are mounted are accommodating by interposing between the substrate and the chip a mixed metal layer comprising at least one ductile, thermally conductive metal such as copper and at least one other metal, preferably a refractory metal, having a lower coefficient of thermal expansion, preferably tungsten. A compliant metal layer, typically of aluminum, silver, copper or gold, is preferably interposed between the substrate and the mixed metal layer.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: October 22, 1996
    Assignee: General Electric Company
    Inventors: Charles D. Iacovangelo, Paul J. DiConza
  • Patent number: 5539254
    Abstract: A substrate subassembly for a high power module, and methods involving the same. The substrate subassembly contains only one switching transistor and has at least one integral short terminal lead tab. The substrate subassemblies can be pretested at significant operating current, to obtain enhanced characterization and matching of mounted switching transistors. Trimmable gate lead resistances can be incorporated in the substrate subassemblies. Enhanced compositional, geometrical and electrical module symmetry is available. New module structures and method are afforded.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: July 23, 1996
    Assignee: Delco Electronics Corp.
    Inventors: Charles T. Eytcheson, Donald E. Lake, deceased, Aiman I. Alhoussami, John D. Tagle, Timothy D. Martin, Lisa A. Viduya, Frank D. Lachenmaier
  • Patent number: 5532513
    Abstract: A lightweight composite lid for a package containing a semiconductor device formed of a porous ceramic body filled with a material having a thermal conductivity greater than air.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: July 2, 1996
    Assignee: Johnson Matthey Electronics, Inc.
    Inventors: Charles Smith, Masyood Akhtar, Michael M. Chau, David Savage
  • Patent number: 5510649
    Abstract: A semiconductor chip package is manufactured comprising a heatsink bonded to an aluminum nitride insulative layer by a thermally conductive and electrically nonconductive epoxy. The aluminum nitride insulative layer is bonded to several portions of a leadframe by an epoxy which is thermally conductive and electrically nonconductive and another epoxy which is thermally conductive and electrically conductive. A semiconductor die is bonded to the aluminum nitride insulative layer by a thermally conductive and electrically conductive epoxy.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: April 23, 1996
    Assignee: Motorola, Inc.
    Inventors: Indira Adhihetty, Brian J. Miller, Ramaswamy Padmanabhan
  • Patent number: 5508559
    Abstract: A method for forming a power circuit package (45) having a porous base structure (20) electrically isolated from a first porous die mount (21) and a second porous die mount (22) by a dielectric material (29). The porous base structure (20) is bonded to a second surface of the the dielectric material (29) whereas the first porous die mount (21), and the second porous die mount (22) are bonded to a first surface of the dielectric material (29). Simultaneous with the bonding step, the porous base structure (20), the first porous die mount (21), and the second porous die mount (22) are impregnated with a conductive material. Semiconductor die (32, 33, 34, and 35) are bonded to the impregnated die mounts. The semiconductor die (32, 33, 34, and 35) are then encapsulated by a molding compound.
    Type: Grant
    Filed: April 25, 1994
    Date of Patent: April 16, 1996
    Assignee: Motorola, Inc.
    Inventors: Samuel J. Anderson, Guillermo L. Romero
  • Patent number: 5504371
    Abstract: A ceramic element is formed by a rare earth and transition element oxide such as LaCoO.sub.3. The ceramic element is substantially isolated from the atmosphere by a case base, a case, etc.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: April 2, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hideaki Niimi, Kenjiro Mihara, Yuichi Takaoka
  • Patent number: 5498907
    Abstract: A plurality of power semiconductor switching devices are included in a circuit module in a pattern whereby interconnecting lead lengths are minimized to provide improved circuit characteristics and to insure uniform current sharing when said devices are paralleled during switch-on, switch-off and steady state conditions.
    Type: Grant
    Filed: September 12, 1994
    Date of Patent: March 12, 1996
    Assignee: Allied Signal Inc.
    Inventors: John J. Tumpey, Sampat Shekhawat, Gayton L. Silvestro, John J. Brogle
  • Patent number: 5463250
    Abstract: A package for power semiconductor components permitting high thermal dissipation and current conductance and including a frame assembly bonded to a substrate on which a power semiconductor chip is mounted. The frame assembly has a wirebonding grid for connecting short, uniform length wirebonds to the surface of the chip. The grid is configured so as to have a portion overlaying and spaced from the chip a distance less than a distance required to connect a wirebond of optimal length to each anode cell of the chip. The package allows a high power semiconductor device to be used as a surface mount device or as a hockey puck.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: October 31, 1995
    Assignee: Westinghouse Electric Corp.
    Inventors: Ngon B. Nguyen, Franklin B. Jones
  • Patent number: 5463248
    Abstract: A semiconductor package comprises an aluminum nitride substrate having a semiconductor element mounted thereon, a lead frame junctioned to the side of the aluminum nitride substrate directly contacting the mounted semiconductor element, and a ceramic sealing member junctioned to the aluminum nitride substrate so as to seal the semiconductor element. The lead frame has a coating layer of a nonmagnetic metallic material formed in a thickness of not more than 20 .mu.m on only one of the opposite surfaces of a lead frame matrix made of a ferromagnetic metal to which a bonding wire is to be junctioned. The layer of the nonmagnetic metallic material is formed by any of such thin film forming technique as the vacuum deposition technique, the spattering technique, and the plating technique. The coating layer formed on only one of the opposite surfaces of the lead frame matrix is capable of amply curbing the resistance and the dependency of inductance on frequency.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: October 31, 1995
    Assignees: Kabushiki Kaisha Toshiba, Sumitomo Metal Industries, Ltd., Sumitomo Metal Ceramics Inc.
    Inventors: Keiichi Yano, Takashi Takahashi, Kazuo Kimura, Yoshitoshi Sato, Kouji Yamakawa, Toshishige Yamamoto, Masafumi Fujii, Shizuki Hashimoto, Hiroshi Takamichi
  • Patent number: 5455385
    Abstract: A packaging assembly for a semiconductor circuit chip is formed of a hermetically sealable, `tub`-like structure. The tub-like structure is comprised a laminated stack of thin layers of low temperature co-fired ceramic (LTCC) material. The laminated stack of LTCC layers contains an internally distributed network of interconnect links through which a semiconductor die, that has been mounted at a floor portion of the tub, may be electrically connected to a plurality of conductive recesses or pockets located at top and bottom sidewall edge portions of the tub, thereby allowing multiple tubs to be joined together as a hermetically sealed assembly and electrically interconnected at the conductive pockets of adjacent tubs.
    Type: Grant
    Filed: June 28, 1993
    Date of Patent: October 3, 1995
    Assignee: Harris Corporation
    Inventors: Charles M. Newton, Edward G. Palmer, Albert Sanchez, Christopher A. Myers
  • Patent number: 5448450
    Abstract: A lead-on-chip integrated circuit package comprising at least one extremely thin adhesive layer transferred from a carrier onto the face of integrated circuit chips, and a lead frame laminated to the last adhesive layer, with cured adhesive acting as an insulator, integrated circuit chip connection pads bonded to and encapsulating the chip and lead frame. Thermally conductive and electrically insulating filling may be included with the adhesive to improve heat conduction from the IC. Compliant adhesive reduces thermally induced stresses between the lead frame and IC chip. Both the improved thermal performance and reduced moisture absorption of the encapsulated package improves the reliability of the integrated circuit package.
    Type: Grant
    Filed: October 28, 1991
    Date of Patent: September 5, 1995
    Assignee: Staktek Corporation
    Inventor: Carmen D. Burns
  • Patent number: 5446314
    Abstract: A heat-conductive honeycomb ceramic spacer having an array of apertures for facilitating assembly of a semiconductor device including a plurality of semiconductor stacks using a low-profile contact comprising a foil with raised portions corresponding to the locations of apertures in the ceramic spacer for forming contacts with the semiconductor stacks when the spacer and the stacks are sandwiched between the foil and another conductive sheet. Use of such a foil also allows disconnection of defective stacks in the device. Extra stacks are provided to compensate for defective stacks, according to an n-x design philosophy. Solder preforms may be included on the stacks and enhanced connections made to the foil of conductive sheet by causing reflux of the solder preforms. The invention may also be applied to multi-layer device constructions.
    Type: Grant
    Filed: June 9, 1992
    Date of Patent: August 29, 1995
    Assignee: International Business Machines Corporation
    Inventors: Paul J. Melnick, Anthony J. Mennella, Jr., Herman P. Meyer
  • Patent number: 5424676
    Abstract: Internal to the transistor, an additional, direct connection is made from the internal collector to the external collector of the transistor by a fixed shunt inductance. The external power supply V.sub.s is applied to the transistor collector through an adjustable external shunt element. The adjustable external shunt element allows the user to finetune the impedance matching circuit such that the transformation ratio of the output matching circuitry is minimized.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: June 13, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Henry Z. Liwinski
  • Patent number: 5422901
    Abstract: A VCSEL having a first mirror stack positioned on the surface of a substrate, an active region positioned on the first mirror stack and substantially coextensive therewith, and a second mirror stack positioned on the active region, the second mirror stack forming a ridge or mesa having a side surface. A metal contact layer is positioned on the side surface of the ridge or mesa and on portions of an end of the ridge or mesa to define a light emitting area, and a layer of diamond-like material is electrolytically plated on the metal contact layer so as to form a heat conductor to remove heat from the laser.
    Type: Grant
    Filed: November 15, 1993
    Date of Patent: June 6, 1995
    Assignee: Motorola, Inc.
    Inventors: Michael S. Lebby, Chan-Long Shieh, Ken Davis
  • Patent number: 5399906
    Abstract: A high-frequency semiconductor hybrid integrated circuit device with desirable high-frequency properties and reduced floating capacitance that is easily manufactured at lower cost with reduced labor. A coupling dielectric substrate bearing conducting films as a circuit pattern is joined to a main dielectric substrate mounted on a heat radiating plate and bearing elements for high frequency amplification to a heat sink. The coupling dielectric substrate should have the same circuit constants at the high-frequency circuit as the main dielectric substrate.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: March 21, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Katsuya Komuro
  • Patent number: 5382830
    Abstract: For the manufacture of a power semiconductor module, one proceeds from a ceramic base board on which copper plates and copper conductor paths are fastened by a suitable method. The ceramic base plate is then scratched and broken. As a result, ceramic side boards are produced which are connected to the base board via conductive paths. The side boards are then swung up, as a result of which the conductive paths fastened on the side boards come into a plane above the base plane. By means of suitable, possibly multiple, breaking and folding of the side boards and suitable development of the ends of the conductive paths, the connecting poles of the power semiconductor chips can be directly contacted. Electronic circuits can be arranged on the side boards.
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: January 17, 1995
    Inventors: Altan Akyurek, Peter Maier, Jurgen Schulz-Harder
  • Patent number: 5371403
    Abstract: A multi-layer package for semiconductor dies using two different types of dielectric materials improves the performance of a semiconductor package. The first material having a high dielectric constant is placed between the power and ground planes to form a decoupling capacitor and the second material having a low dielectric constant is used to contact the signal traces. Silicon carbide is preferred for the high dielectric constant material.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: December 6, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: Chin-Ching Huang, Elizabeth C. Galindo
  • Patent number: 5338974
    Abstract: An RF power transistor is mounted on a ceramic substrate with a plurality of input leads extending from one edge of the substrate, a plurality of output leads extending from an opposite edge of the substrate, a plurality of input ground leads with ground leads positioned between adjacent input leads, and a plurality of output ground leads with ground lead positioned between adjacent output leads. All ground leads are ohmically connected with the current paths between adjacent ground leads reduced in length.
    Type: Grant
    Filed: March 17, 1993
    Date of Patent: August 16, 1994
    Assignee: Spectrian, Inc.
    Inventors: David S. Wisherd, Howard D. Bartlow
  • Patent number: 5324987
    Abstract: Differences in thermal expansion properties between integrated circuit chips, especially of gallium arsenide, and the dielectric substrates (especially diamond and aluminum nitride) on which said chips are mounted are accommodated by interposing between the substrate and the chip a base having diamond pedestals in combination with a material of higher coefficient of thermal expansion than the substrate, typically a metal such as copper or tungsten. The base may be integral with a diamond substrate or may be a shim interposed between the substrate and the chip.
    Type: Grant
    Filed: April 14, 1993
    Date of Patent: June 28, 1994
    Assignee: General Electric Company
    Inventors: Charles D. Iacovangelo, Raymond A. Fillion, James F. Burgess
  • Patent number: 5293509
    Abstract: The present invention provides a sintered body of aluminum nitride comprising (i) aluminum nitride as a main component and (ii) at least one component selected from the group consisting of Zr, Hf, V, Nb, Ta, Cr, Mo, W, Fe, Co, Ni, Nd, Ho, Ti and compounds thereof in the total amounts of not greater than 1.0 wt. % and not less than 0.01 wt. % in terms of elements on the basis of sintered body, the sintered body being colored and having a thermal conductivity of at least 150 W/mK. The sintered body is useful for the preparation of circuit boards having printed circuits thereon and highly heat-releasing ceramic packages for semiconductive devices.
    Type: Grant
    Filed: July 6, 1993
    Date of Patent: March 8, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akira Yamakawa, Masaya Miyake, Hitoyuki Sakanoue, Koichi Sogabe
  • Patent number: 5227663
    Abstract: A metallic or ceramic dam structure surrounding a semiconductor die in a semiconductor device assembly is disclosed. The dam structure forms a cavity containing a potting compound encapsulating the die. The dam structure may also be provided with a flat lid portion, enclosing the cavity and forming a flat, exterior, heat-dissipating surface for the semiconductor device assembly. Further, an additional add-on structure, having heat dissipating fins, may be joined to the dam structure, exterior the semiconductor device assembly, to provide additional heat dissipation. The add-on structure is particularly well-suited to applications where air cooling is available.
    Type: Grant
    Filed: March 18, 1992
    Date of Patent: July 13, 1993
    Assignee: LSI Logic Corporation
    Inventors: Sadanand Patil, Adrian Murphy, Keith Newman
  • Patent number: 5168344
    Abstract: Hermetic package designs for HDMI substrates are discussed. The designs for a hermetically sealed, perimeter-leaded package may have the following features:a) a flat monolithic dielectric base, the base having a flat upper surface and a flat lower surface;b) a zone on the upper surface, in which zone the HDMI device would reside;c) a seal ring surrounding the zone;d) a cover adapted to be hermetically sealed to the seal ring, thereby protecting the HDMI device located in the zone;e) a plurality of conductive vias (inner vias) extending from the upper surface inside said zone downwardly toward the lower surface;f) a plurality of perimeter conductive lead pads located on or in the upper surface about the perimeter of the zone inside the seal ring; wherein(1) the perimeter lead pads are electrically connected to the inner vias, and(2) the inner vias are electrically connected to a surface of the base outside the zone.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: December 1, 1992
    Assignee: W. R. Grace & Co. Conn.
    Inventors: Michael R. Ehlert, Jack H. Enloe, Alan L. Kovacs, John W. Lau