Of High Thermal Conductivity Ceramic (e.g., Beo) Patents (Class 257/705)
  • Publication number: 20030020159
    Abstract: The invention relates to a heat-conducting adhesive compound between two workpieces (1, 2). Said compound is provided with a sintered layer (3) that consists of heat-conducting powder, is arranged between the two workpieces and contacts each workpiece in a two-dimensional manner. The inventive compound is also provided with an adhesive (4′) which fills openings (33) on the surface (31) of the layer and adheres to the two workpieces. In a preferred embodiment, the sintered layer consists of silver powder. The sintered layer is produced between the workpieces and said layer is subsequently filled with a liquid adhesive (4) which is then hardened.
    Type: Application
    Filed: August 27, 2002
    Publication date: January 30, 2003
    Inventor: Herbert Schwarzbauer
  • Patent number: 6483186
    Abstract: A monolithic microwave integrated circuit (MMIC) package comprises a MMIC die, a heat sink, an insulation substrate, and a sealing material. The MMIC die has an active region and a peripheral region. The heat sink is located in the active region. A plurality of bonding pads are located in the peripheral region. The insulation substrate has an opening and a plurality of transit ports. The opening is used to contain the heat sink and the transit ports are electrically connected to the bonding pads. The sealing material is filled between the insulation substrate and the MMIC die to cover the whole MMIC die so that the MMIC die is fixed to the insulation substrate and is protected.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: November 19, 2002
    Assignee: Apack Communications Inc.
    Inventors: Tsung-Ying Hsieh, Chin-Lien Hsu, Wen-Rui Hsu
  • Patent number: 6472743
    Abstract: A semiconductor package with a heat dissipating structure is proposed, in which the heat dissipating structure is precisely positioned on a substrate, in a manner that a plurality of solder balls self-align with ball pads formed on the substrate, and support a heat sink to be positioned above a semiconductor chip mounted on the substrate. This therefore makes the heat sink closely abut a molding cavity of an encapsulating mold in a molding process, and prevents resin flash from occurring on the heat sink, so that a surface of the heat sink can be directly exposed to the atmosphere for improving heat dissipating efficiency. Moreover, the solder balls characterized in softness deform in response to a pressure generated by the encapsulating mold during molding. Therefore, the substrate can be protected from being damaged by the pressure, and thus quality of the semiconductor package can be assured.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: October 29, 2002
    Assignee: Siliconware Precision Industries, Co., Ltd.
    Inventors: Chien-Ping Huang, Chi-Chuan Wu, Jui-Yu Chuang, Lien-Chih Chan, Ming-Chih Hsieh
  • Patent number: 6465733
    Abstract: A packaged electronic structure includes an electronic device, and a package to which the electronic device is affixed. At least a portion of the package is made of a composite material of aluminum nitride dispersed in aluminum. The composite material is preferably prepared by mixing powders of the aluminum nitride and aluminum, and thereafter pressing and sintering the mixture.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: October 15, 2002
    Assignee: Hughes Electronics Corp.
    Inventors: M. Akbar Ali, Carl W. Peterson, Hutan Taghavi, Bruce W. Buller
  • Patent number: 6459149
    Abstract: An electronic component includes an electronic component element and a package to house the electronic component element. The package includes a concave area in which the electronic component element is housed, an area for a sealing frame which is located along the periphery of the concave area, and a sealing cover which is mounted on the area for a sealing frame so as to cover the concave area. Connecting electrodes are electrically connected to the electronic component element and a conductive pattern to be used for image recognition is provided on the upper surface of the area for a sealing frame.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: October 1, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazunobu Shimoe, Ryoichi Kita
  • Patent number: 6455925
    Abstract: A transistor package comprises a first layer in which a thermally conductive flange is integrated into a dielectric substrate layer, a transistor attached to the flange, and input and output contacts coupled to the transistor. The transistor package is attached to a circuit board such that its input and output contacts are electrically coupled to associated conductors on the circuit board. In one embodiment, the transistor package further comprises additional dielectric layers, bonded to the bottom layer, in which a top layer forms a lid covering the transistor. The layers intermediate the bottom and top layers have central areas cut away where the layers overlap the transistor, thereby forming an interior chamber in the package. Impedance matching networks may also be provided to couple the transistor input and output terminals to their respective contacts, where the matching networks tune the input and output impedances of the package.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: September 24, 2002
    Assignee: Ericsson Inc.
    Inventor: Steven J. Laureanti
  • Patent number: 6452282
    Abstract: An insulating tape for use in LOC (lead-on-chip) type semiconductor chip packages. With a tripartite structure in which two adhesive layers are provided to both surfaces of a base film, the insulating tape ranges, in coefficient of thermal expansion, from 16.0 to 23.5 ppm/° C. and is very useful in improving the reliability of LOC semiconductor chip packages having lead frames.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: September 17, 2002
    Assignee: Saehan Micronics Incorporation
    Inventors: Jeong Min Kweon, Soon Sik Kim, Kyeong Ho Chang, Kyung Rok Lee
  • Patent number: 6423576
    Abstract: A thermally enhanced package for an integrated circuit, the integrated circuit having a surface with bond pads formed thereon, includes a heat sink structure attached to a central region of the integrated circuit surface inward of the bond pads. The package further includes a substrate attached to the heat sink structure. The heat sink structure includes a heat sink and first, second adhesive layers between the heat sink and the integrated circuit, substrate, respectively. The heat sink enhances heat transfer between the integrated circuit and the substrate. Further, the first, second adhesive layers decouple any difference in thermal expansion between the integrated circuit, the heat sink and the substrate.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: July 23, 2002
    Assignee: Amkor Technology, Inc.
    Inventor: Paul Hoffman
  • Patent number: 6316826
    Abstract: A semiconductor mounting package includes at least one diamond member having a first surface on which at least one semiconductor chip is mounted and a second surface opposite the first surface, and a high thermal conductivity metal member adhered to the second surface of the diamond member.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: November 13, 2001
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiyuki Yamamoto, Takahiro Imai
  • Patent number: 6303974
    Abstract: In a housing of a semiconductor device there are provided a plurality of semiconductor chips captivated in a preformed sub-assembly and arranged to present contact areas for connection to anode and emitter electrodes of the semiconductor housing. Electrically conductive contact pin arrangements project from electrically insulated channels in the preformed sub-assembly, an inward end of each of the pin arrangements being so arranged, when urged into its channel, as to provide an electrical connection to a part of the surface of a semiconductor chip. There is a sheet of electrically conductive material, resting on a base level of an inner surface of the emitter electrode and electrically isolated therefrom by an electrically insulating insert, as a means for distributing an electrical signal and making simultaneous contact with the opposite ends of the pin arrangements.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: October 16, 2001
    Assignee: Westcode Semiconductors Limited
    Inventors: Robert Charles Irons, Kevin Robert Billett, Michael John Evans
  • Patent number: 6297549
    Abstract: This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: October 2, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Michiaki Hiyoshi
  • Patent number: 6261481
    Abstract: An insulating material of high electrically insulating properties and high thermal conductivity is provided wherein the high thermal conductivity is attained by having a liquid crystal resin comprising a polymerization product of a resin composition containing a monomer which has a mesogen group.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: July 17, 2001
    Assignee: Hitachi, LTD
    Inventors: Masaki Akatsuka, Yoshitaka Takezawa, Yuzo Ito
  • Patent number: 6262481
    Abstract: A heat conducting metal is placed under a semiconductor chip and wraps around a substrate of the semiconductor device package to serve as the heat sink for the chip. The metal can wrap around a through-hole in the middle of the substrate, or wrap around the edge of the substrate. A metal plate can be placed between the chip and the heat conducting metal to hold the semiconductor chip.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: July 17, 2001
    Assignee: Harvatek Corporation
    Inventor: Bily Wang
  • Patent number: 6225693
    Abstract: In a semiconductor package for radio frequency, slits arranged like dotted lines, elongated metallic plates, or rectangular dielectric members are provided on a surface for grounding of the package, on which a semiconductor element is mounted, whereby an area for grounding positioned just below the semiconductor element and areas in the surface for grounding of the package being in contact with wires for grounding are arranged with extremely short intervals to thereby substantially reduce components of inductance causing deterioration of radio frequency properties; and disconnections of the wires in the surface for grounding caused by extrusion of a jointing material 6 are prevented.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: May 1, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Katumi Miyawaki
  • Patent number: 6222262
    Abstract: A semiconductor ceramic device includes a semiconductor ceramic sintered body and external electrodes. The semiconductor ceramic sintered body contains a lanthanum cobalt type oxide major component, about 0.1 to 10 mol % on an element conversion basis of an oxide of Cr as a sub-component, and about 0.001 to 0.5 mol % on an element conversion basis of at least one of the oxides of Li, Na, K, Rb, Cs, Be, Mg, Ca, Sr, Ba, Ni, Cu and Zn.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: April 24, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Ueno, Akinori Nakayama, Terunobu Ishikawa, Hideaki Niimi, Yoichi Kawase
  • Patent number: 6215176
    Abstract: A dual leadframe package. A chip including a first surface and a second surface is provided. A gate and a first source/drain region are located on the first surface, and a second source/drain region is located on the second surface. A first lead including a first innerlead and a first outerlead and a second lead including a second innerlead and a second outerlead are provided. The first innerlead is coupled to the first source/drain region, and the second innerlead is coupled to the gate. A conductive plate including a top surface and a bottom surface is provided, and the top surface is coupled to the second source/drain region. A packaging material seals the chip, the first innerlead, the outerlead and a portion of the conductive plate. The bottom surface, the first outerlead and the second outerlead are exposed.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: April 10, 2001
    Assignee: Sitron Precision Co., Ltd.
    Inventor: Chih-Kung Huang
  • Patent number: 6204563
    Abstract: A semiconductor device for mounting on an external substrate includes a semiconductor chip, a high thermal elastic internal substrate and a high elastic liquid resin. The semiconductor chip has bump electrodes formed on its main surface. The high thermal elastic internal substrate includes a conductive pattern on one surface and external electrodes on the other surface. The conductive pattern is electrically connected to the bump electrodes. The external electrodes are electrically connected to the conductive pattern and mounted on the external substrate. The high elastic liquid resin covers the surface of the semiconductor chip, the one surface of the internal substrate and the bump electrodes. The internal substrate has a Young modulus of about 8000 to 15000 kg/mm2, which is larger than a Young modulus of the external substrate.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: March 20, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Noritaka Anzai, Yoshimi Egawa
  • Patent number: 6204554
    Abstract: A surface mount semiconductor package includes washing grooves disposed on a bottom surface of a plastic housing. The package also employs locking elements for locking the plastic housing to a metal pad on which a semiconductor device is mounted, where the locking elements include a cross bar between terminals, slots disposed on the metal pad which include barbs and dove-tail grooves disposed on the metal pad. The metal pad includes a waffled surface for improved coupling to a substrate. The package includes terminals having offset portions for providing spaces for the plastic housing material to fill for improved encapsulation of the terminals. The metal pad extends beyond the lateral edges of the plastic housing for improved heat dissipation and for providing a surface to couple to a heatsink.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: March 20, 2001
    Assignee: International Rectifier Corporation
    Inventors: Peter R. Ewer, Arthur Woodworth
  • Patent number: 6157076
    Abstract: A hermetic thin pack semiconductor device. The semiconductor device has a semiconductor substrate and at least one electrode on the upper surface of the semiconductor substrate. A lid of a ceramic material for the semiconductor device has at least one opening extending through the lid. A first electrically conductive material is located on the interior surface of the at least one opening, a second electrically conductive material is located on at least a portion of the upper surface of the lid, and a third electrically conductive material is located on at least a portion of the lower surface of the lid. A solder material is positioned between the electrode and the third electrically conductive material and positioned on a corresponding portion of the electrode opposite a corresponding opening in the lid.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: December 5, 2000
    Assignee: Intersil Corporation
    Inventors: James Azotea, Victor A. K. Temple
  • Patent number: 6143590
    Abstract: A method of making a semiconductor device including: a ceramic base board formed of AlN; a CPU chip and a CMU chip which are flip-chip bonded on a circuit board which includes the ceramic base board; SRAM chips which are die-bonded to the lower major surface of the circuit board; first heat conductive blocks adhesively attached to the CPU chip and the CMU chip; second heat conductive blocks adhesively attached to the upper major surface of the AlN ceramic base board; a resin package; and a heat sink which, adhesively attached on the upper major surface of the resin package, is in close contact with the first heat conductive blocks and the second heat conductive blocks. The heat generated by the CPU chip and the CMU chip is transferred to the heat sink via the first heat conductive blocks and is radiated from the heat sink.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: November 7, 2000
    Assignee: Fujitsu Limited
    Inventors: Ken'ichi Ohki, Kiyoshi Muratake, Hidetoshi Inoue, Takehisa Tsujimura
  • Patent number: 6143401
    Abstract: An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature T.sub.g greater than 200.degree. C. and a volumetric coefficient of thermal expansion of .ltoreq.75 ppm/.degree.C. A semiconductor device is electrically attached to the laminated substrate.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: November 7, 2000
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: Paul J. Fischer, Joseph Korleski
  • Patent number: 6137174
    Abstract: A package for multiple IC chip module. The IC chip is attached to electric wires on ceramic substrate which has good heat dissipating capability. The bonding pads along the periphery of the ceramic substrate are lead-bonded to a second substrate with printed wiring on at least one side of the surfaces and ball grid array at the bottom surface. Double-sided printed wiring can be used to provide multiple-layered interconnection. The IC chip is separated from the second substrate by a resin to cushion the stress due to difference in thermal expansion coefficients of the IC chip and the second substrate.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: October 24, 2000
    Assignee: ChipMOS Technologies Inc.
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng
  • Patent number: 6111314
    Abstract: The present invention relates generally to a new method for improving the reliability of cooling designs using thermal paste to cool chips in semiconductor modules and structure thereof. More particularly, the invention encompasses a structure and a method that uses surface chemistry modification of the inside of the thermal cooling caps where it contacts thermal paste. The internal surface of the cap is modified by embedding particles that have the same chemical composition as one or more of the solids used in the thermal paste. The particles may be embedded in the cap by casting, grit blasting, or pressing the particles permanently into the surface.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: August 29, 2000
    Assignee: International Business Machines Corporation
    Inventors: David L. Edwards, Patrick A. Coico, Sushumna Iruvanti, Frank L. Pompeo, Raed A. Sherif, Hilton T. Toy
  • Patent number: 6104090
    Abstract: An integrated circuit heat transfer element (6,30) is made by selecting thermally conductive fibers having aspect ratios of length to diameter of more than 1, selecting a resin and combining the fibers and the resin to create a formable resin/fiber compound. The resin/fiber compound is formed into a composite material in part by applying pressure to the formable resin/fiber compound, which aligns the fibers, and when cured creates a thermally anisotropic composite material to maximize heat conduction along the aligned fibers. The thermally anisotropic composite material has a coefficient of thermal expansion (CTE) of less than about 10.times.10.sup.-6 cm/cm/.degree. C. The composite material has a thermal conductivity in the direction of the carbon fibers of at least 50 W/m.degree. K. The IC device is preferably secured to the heat transfer element using a thermally conductive adhesive.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: August 15, 2000
    Assignee: Bryte Technologies, Inc.
    Inventors: Scott M. Unger, Guy T. Riddle
  • Patent number: 6091146
    Abstract: A reworkable multi-chip module contains a large multi-chip module package (2) with an opening at the top to permit access to an internal region for semiconductor devices, the opening being at least four square inches area with the length or width dimension being at least two inches. The opening is sealed with a stiff closure (1) of sufficient rigidity to withstand at least one atmosphere of differential pressure without significant deflection, is removable in a single piece and may be reinstalled. The closure includes a panel of electrically non-conductive material (3) and a metal flange (5) borders the periphery of the panel to support the panel on the top of the module package.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: July 18, 2000
    Assignee: TRW Inc.
    Inventors: Ryan S. Berkely, Steven Park, Mary C. Massey, Steven F. VanLiew
  • Patent number: 6087721
    Abstract: A bipolar transistor (3) is provided with a first main surface (4) in contact with a conductive mounting surface (2), and with an opposed second main surface (12) having connection pads (5, 6, 40) for an emitter, base, and collector. The lateral dimensions of the conductive mounting surface (2) are practically equal to the dimensions of the first main surface (4) of the transistor (3), and may thus be relatively small. The high-frequency properties of the transistor (3) are strongly determined by the size of the conductive mounting surface (2), which through an insulating substrate (1) forms a parasitic capacitance with a conductive ground surface (18), which capacitance is connected to the transistor (3). This parasitic capacitance is very important especially for high-frequency applications. Furthermore, the bonding wires (E, B) for the connection pads of emitter and base are shorter than in the prior art because they need not pass over a relatively large conductive mounting surface (2).
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: July 11, 2000
    Assignee: U.S. Philips Corporation
    Inventors: Atef Akhnoukh, Petrus M. A. W. Moors
  • Patent number: 6078097
    Abstract: In a lead frame, leads are formed on a surface of protective insulation film having a device hole. Protruding electrodes (solder balls) are formed on the surface of the leads opposite the surface closer to the protective insulation film. A reinforcement plate is also formed on the rear surface of the protective insulation film.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: June 20, 2000
    Assignee: Sony Corporation
    Inventor: Kenji Ohsawa
  • Patent number: 6072240
    Abstract: A semiconductor device which improves heat radiation performance and realizes size reduction and enables heat to be radiated swiftly from both of the principal surfaces of a semiconductor chip even when the semiconductor chip has a construction vulnerable to stresses. It comprises several IGBT chips each having a collector electrode on one principal surface and an emitter electrode and a gate electrode on the other principal surface and two high thermal conductivity insulating substrates sandwiching these IGBT chips and having electrode patterns for bonding to the electrodes of the IGBT chips disposed on their sandwiching surfaces, the electrodes of the IGBT chips and the electrode patterns of the high thermal conductivity insulating substrates being bonded by brazing.
    Type: Grant
    Filed: October 16, 1998
    Date of Patent: June 6, 2000
    Assignee: Denso Corporation
    Inventors: Tomonori Kimura, Norihito Tokura, Fumio Ohara, Masahito Mizukoshi
  • Patent number: 6054762
    Abstract: A paste of active metallic brazing material is applied to the entire surface of each side of aluminum nitride or alumina ceramic substrate 1; circuit forming copper plate 3 having a thickness of 0.3 mm is placed in contact with one surface of the substrate and a heat dissipating copper plate 4 having a thickness of 0.25 mm placed in contact with the other surface; the individual members are compressed together and heated at 850.degree. C.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: April 25, 2000
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Masami Sakuraba, Masami Kimura, Junji Nakamura, Masaya Takahara
  • Patent number: 6018197
    Abstract: A wired ceramic board has on a main surface of a ceramic substrate thereof a plurality of bonding pads each of which has a projection having a solderable outer surface and positioned inside an outer periphery of each bonding pad when observed in a plan view. To each bonding pad is bonded a solder ball by using solder which is lower in melting point than the solder ball. The ceramic board and a resinous printed board are placed one upon another in such a manner that their bonding pads are aligned with each other. The bonding pads are soldered together with low melting point solder. The projection of each bonding pad is embedded in or surrounded by a mass of low melting point solder and joined with the mass of solder to constitute an integral unit while serving as a core of the unit.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: January 25, 2000
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Hajime Saiki, Kozo Yamasaki
  • Patent number: 6002168
    Abstract: A microelectronic component for mounting a rigid substrate, such as a hybrid circuit to a rigid support substrate, such as a printed circuit board. The microelectronic component includes a rigid interposer which may have a chip mounted on its first surface; a pattern of contacts on the rigid interposer; a flexible interposer overlying the second surface of the rigid interposer; a pattern of terminals on the flexible interposer; flexible leads; and solder coated copper balls mounted on the flexible interposer. The microelectronic component may have a socket assembly mounted on the first surface of the rigid interposer. The microelectronic component may be mounted on a rigid support substrate.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: December 14, 1999
    Assignee: Tessera, Inc.
    Inventors: Pieter H. Bellaar, Thomas H. DiStefano, Joseph Fjelstad, Christopher M. Pickett, John W. Smith
  • Patent number: 5998043
    Abstract: A highly reliable member for a semiconductor device, in which a high melting point metallizing layer, which consists mainly of a high melting point metal such as W and/or Mo, and an intervening metal layer, which has a melting point of not greater than 1,000.degree. C. and consists mainly of at least one selected from among Ni, Cu and Fe, are provided on an AlN substrate material in this order on the AlN substrate material, and a conductor layer consisting mainly of copper is directly bonded to the intervening metal layer without intervention of a solder material layer. A semiconductor element or the like is mounted on the member for a semiconductor device, thereby fabricating a semiconductor device. The high melting point metallizing layer is formed on an aluminum nitride substrate by post-fire or co-fire matallization.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: December 7, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazutaka Sasaki, Hirohiko Nakata, Akira Sasame, Mitsunori Kobayashi
  • Patent number: 5973398
    Abstract: A semiconductor device and fabrication method are presented which employ a thermally conductive substrate having an outer layer of palladium. The substrate may be made of, for example, a metal such as copper. The substrate does not itself include layers of signal traces or bonding pads which function as device terminals, but provides a stiff backing for support of a flexible circuit which includes signal traces and bonding pads. An adhesive layer bonds the flexible circuit to the substrate. The outer layer of palladium has a desired surface roughness and chemical properties which improve the adhesion of the adhesive layer to the substrate. The substrate has opposed, substantially planar upper and underside surfaces. In one embodiment, the underside surface of the substrate has a die cavity, and the flexible circuit includes a set of conductors bonded to one side of a sheet of dielectric material (e.g., polyimide film).
    Type: Grant
    Filed: November 4, 1997
    Date of Patent: October 26, 1999
    Assignee: LSI Logic Corporation
    Inventors: Larry L. Jacobsen, Mohammad Eslamy
  • Patent number: 5945735
    Abstract: The present invention relates generally to a new process for hermetically sealing of a high thermally conductive substrate, such as, an aluminum nitride substrate, using a low thermally conductive interposer and structure thereof. More particularly, the invention encompasses a hermetic cap which is secured to an aluminum nitride substrate using the novel thermal interposer. The novel thermal interposer basically comprises of layers of relatively high thermal conductive metallic materials sandwiching a core layer of low thermal conductive metallic material.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: August 31, 1999
    Assignee: International Business Machines Corporation
    Inventors: Laertis Economikos, Lester Wynn Herron, Mario J. Interrante
  • Patent number: 5909058
    Abstract: A thin type semiconductor package having a low thermal resistance and a low electric resistance is disclosed, that comprises a nitride ceramic supporting substrate having a first main surface and a second main surface, the nitride ceramic supporting substrate having via-holes that pass through from the first main surface to the second main surface, a resin film having a wiring layer, the resin film being bonded to the first main surface of the supporting substrate, the wiring layer being electrically connected to an edge portion of the via-holes on the first main surface, the resin film having an opening region, a semiconductor chip directly mounted on the first main surface of the nitride ceramic supporting substrate, disposed at the opening region of the resin film, and electrically connected to the wiring layer of the resin film, and external connection terminals disposed on the edge portion of the via-holes of the second main surface.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: June 1, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Yano, Hironori Asai, Kaoru Koiwa, Nobuo Iwase
  • Patent number: 5907185
    Abstract: This invention provides a package for complex semiconductor devices and a ceramic terminal block useful for the package. For example, the package might contain a semiconductor laser diode and a Peltier device for cooling the laser diode. A ceramic terminal block has metallized electrode patterns formed thereon which extend inside and outside the package. Grooves are formed in some of the metallized electrode patterns for the leads of the Peltier device. Inward extending leads are fixed on the grooves of the electrode patterns for the Peltier leads. The leads of the Peltier device are soldered to the inward leads.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: May 25, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Nobuyoshi Tatoh
  • Patent number: 5905304
    Abstract: A surface mount semiconductor package includes washing grooves disposed on a bottom surface of a plastic housing. The package also employs locking elements for locking the plastic housing to a metal pad on which a semiconductor device is mounted, where the locking elements include a cross bar between terminals, slots disposed on the metal pad which include barbs and dove-tail grooves disposed on the metal pad. The metal pad includes a waffled surface for improved coupling to a substrate. The package includes terminals having offset portions for providing spaces for the plastic housing material to fill for improved encapsulation of the terminals. The metal pad extends beyond the lateral edges of the plastic housing for improved heat dissipation and for providing a surface to couple to a heatsink.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: May 18, 1999
    Assignee: International Rectifier Corporation
    Inventors: Peter R. Ewer, Arthur Woodworth
  • Patent number: 5900312
    Abstract: A package for mounting an integrated circuit chip includes a body having at least a first region and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region approximately matches the CTE of the integrated circuit chip mounted on the package, and the second region approximates the CTE of the printed wiring board to which the package is mounted.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: May 4, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: Mark F. Sylvester
  • Patent number: 5895972
    Abstract: An apparatus and method that permits the removal of heat from the back side surface of an integrated circuit semiconductor substrate while performing optical based testing through or at the back side surface of the semiconductor substrate.In one embodiment, the present invention includes a semiconductor device having an infrared transparent heat slug attached to the back side surface of the device. Heat is removed from the semiconductor device through an infrared transparent heat slug that is then thermally cooled by a conventional cooling technique.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: April 20, 1999
    Assignee: Intel Corporation
    Inventor: Mario J. Paniccia
  • Patent number: 5894166
    Abstract: To mount a semiconductor i.c. die on a support substrate the upper surface of the die is provided with electrically conductive bumps all of which are the same height. The bumps are provided on the ground connection pads on the upper surface of the die. The conductive pads on the die including the ground connection pads are connected to corresponding contacts on the upper surface of the substrate on which the die is mounted. Additionally, a thermally conductive, electrically conductive slug overlies the die and is mounted on and bonded to the bumps. The slug provides required heat removal from the die and also provides necessary ground connection to circuitry within the die.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: April 13, 1999
    Assignee: Northern Telecom Limited
    Inventor: Robert Surridge
  • Patent number: 5892279
    Abstract: A packaging for high-power devices such as Insulated Gate Bipolar Transistors includes a direct bonded copper substrate (DBC), such as beryllium oxide (BeO), soldered directly to a heat generating surface of the high-power device. The direct bonded copper substrate (DBC) is, in turn, soldered directly to a liquid cooled heatsink (HS). The packaging improves the thermal management of the heat generated by the high-power device, and is applicable for use in a switching circuit for a 3-phase electric traction motor (M). The assembly also provides for improved wirebonding design in order to use each high-power device to its fullest.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: April 6, 1999
    Assignee: Northrop Grumman Corporation
    Inventor: Ngon B. Nguyen
  • Patent number: 5886408
    Abstract: A semiconductor device including: a ceramic base board formed of A1N; a CPU chip and a CMU chip which are flip-chip bonded on a circuit board which includes the ceramic base board; SRAM chips which are die-bonded to the lower major surface of the circuit board; first heat conductive blocks adhesively attached to the CPU chip and the CMU chip; second heat conductive blocks adhesively attached to the upper major surface of the A1N ceramic base board; a resin package; and a heat sink which, adhesively attached on the upper major surface of the resin package, is in close contact with the first heat conductive blocks and the second heat conductive blocks. The heat generated by the CPU chip and the CMU chip is transferred to the heat sink via the first heat conductive blocks and is radiated from the heat sink. The heat generated by the SRAM chips is transferred to the heat sink via the A1N ceramic base board and the second heat conductive blocks and is radiated from the heat sink.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: March 23, 1999
    Assignee: Fujitsu Limited
    Inventors: Ken'ichi Ohki, Kiyoshi Muratake, Hidetoshi Inoue, Takehisa Tsujimura
  • Patent number: 5869890
    Abstract: A Ceramic Bonding Copper (CBC) substrate used in semiconductor modules includes a ceramic plate having foil-shaped copper plates bonded to the ceramic plate by the direct copper bonding method. A circuit pattern is formed on one of the copper plates. The ceramic plate is fabricated by sintering at high temperature an alumina powder compact containing zirconia and one or more of the following additives: yttria, calcia, magnesia, and ceria. The flexural strength and the thermal conductivity of the alumnina ceramic plate of the invention are remarkably improved, facilitating a reduction in the thickness of the ceramic plate. The reduction in thickness of the CBC substrate further improves the ability of the semiconductor device to radiate heat and therefore increases the current carrying capability of the semiconductor device.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: February 9, 1999
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masaharu Nishiura, Akira Morozumi, Tomio Shimizu, Katsumi Yamada, Shigemasa Saito
  • Patent number: 5844319
    Abstract: A microelectronic assembly (10) includes an integrated circuit component (14) attached to a polymeric substrate (12) by a plurality of unencapsulated solder bump interconnections (16). A collar (18) is affixed to the polymeric substrate (12) about the integrated circuit component (14) and is formed of an inorganic material having a coefficient of thermal expansion less than that of the substrate (12). The collar (18) constrains thermal expansion of the polymeric substrate (12) in the die attach region (22), thereby lessening any deleterious effects caused by a mismatch in the thermal expansion of the polymeric substrate (12) and the integrated circuit component (14).
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: December 1, 1998
    Assignee: Motorola Corporation
    Inventors: Danniel Roman Gamota, George Amos Carson, Sean Xin Wu, Brian J. Bullock
  • Patent number: 5838063
    Abstract: A lid for a chip/package system includes a body sized to fit over an integrated circuit chip and being connectable to a package. The body has at least two regions exhibiting different coefficients of thermal expansion, with one CTE matching that of the chip and the other matching that of the package.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: November 17, 1998
    Assignee: W. L. Gore & Associates
    Inventor: Mark F. Sylvester
  • Patent number: 5834840
    Abstract: An electronic device package is provided, consisting of reaction bonded silicon nitride structural and dielectric components and conductor, resistor, and capacitor elements positioned with the package structural components. The package consists of a ceramic package base characterized by a dielectric constant less than 6, of reaction bonded silicon nitride, or a heat spreader material. An electrical conductor is positioned on, embedded in, or attached to the package base for making electrical contact to an electronic device supported on the base and in preferred embodiments, a resistor is attached to the package base. The invention also provides package sidewalls connected to the package base, preferably of reaction bonded silicon nitride, and at least one electrical conductor extending to an outside surface of the package sidewalls for making electrical contact to an electronic device supported by the package base.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: November 10, 1998
    Assignees: Massachusetts Institute of Technology, Charles Stark Draper Laboratory, Inc.
    Inventors: William L. Robbins, John S. Haggerty, Dennis D. Rathman, William D. Goodhue, George B. Kenney, Annamarie Lightfoot, R. Allen Murphy, Wendell E. Rhine, Julia Sigalovsky
  • Patent number: 5819402
    Abstract: The present invention relates generally to a new apparatus and method for customized cooling of chips. More particularly, the invention encompasses an apparatus and a method that provides customized cooling of a MCM (Multi-Chip Module) by varying the depth of thermal compound filled gap or the blind hole that is above each chip.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: October 13, 1998
    Assignee: International Business Machines Corporation
    Inventors: David Linn Edwards, Mark Gerard Courtney, Albert Joseph Fahey, Gregory Scott Hopper, Sushumna Iruvanti, Charles Frederick Jones, Gaetano Paolo Messina, Raed A. Sherif
  • Patent number: 5821617
    Abstract: A surface mount package for use with large area silicon device. The package uses a pressed ceramic frame and solid metal pads which are closely matched for coefficient of thermal expansion (CTE) to each other and to the silicon die. The package is specifically designed for large area die (greater than 0.0625 inches squared) and for high temperature eutectic alloy bonding. All materials of the package are CTE matched to each other and to silicon within 10%.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: October 13, 1998
    Assignee: Microsemi Corporation
    Inventors: Tracy Autry, Fernando Lynch, Dan Tulbure
  • Patent number: 5818105
    Abstract: A plastic covered semiconductor device that enables to simplify the structure and fabrication to reduce the assembly cost of the device and to reduce the thickness or height of the device. This device contains a substrate having a first surface and a second surface opposite to the first surface, a semiconductor chip mounted on or over the first surface, lead fingers joined to the first surface, interconnecting conductors electrically interconnecting the semiconductor chip with the corresponding lead fingers, respectively, and a plastic covering material formed to cover the first surface. Each lead finger is made of an inner part bonded to the first surface of the substrate and an outer part protruding the covering material. The covering material confines the semiconductor chip, the interconnecting conductors and the inner parts of the lead fingers. The second surface of the substrate is exposed from the covering material.
    Type: Grant
    Filed: July 21, 1995
    Date of Patent: October 6, 1998
    Assignee: NEC Corporation
    Inventor: Tsunenobu Kouda
  • Patent number: 5808358
    Abstract: A method for soldering a first component having a metal surface to a second component having a metal surface includes holding the metal surface of the first component in a position above a placement area on the metal surface of the second component to establish a gap between the surfaces. The method further includes reflowing solder within the gap.A structure including a thermally conductive baseplate, an electrical insulator attached to the baseplate, and a metallic shield mounted on the insulator. The structure also includes an integrated power device having a power-dissipating electronic device, and a first metal layer connected to the shield through a solder joint. A substrate includes an aperture, and the integrated power device is mounted with the power-dissipating device sitting within the aperture. The substrate also includes a conductive run electrically connected to a second metal layer of the integrated power device.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: September 15, 1998
    Assignee: VLT Corporation
    Inventors: Patrizio Vinciarelli, Robert E. Belland, George J. Ead, Fred M. Finnemore, Lance L. Andrus