Of High Thermal Conductivity Ceramic (e.g., Beo) Patents (Class 257/705)
  • Patent number: 6891263
    Abstract: The present invention provides a ceramic substrate which can keep a sufficiently large breakdown voltage even if the pore diameter of its maximum pore is 50 ?m or less to be larger than that of conventional ceramic substrates, can give a large fracture toughness value because of the presence of pores, can resist thermal impact, and can give a small warp amount at high temperature. The ceramic substrate of the present invention is a ceramic substrate for a semiconductor-producing/examining device having a conductor formed on a surface of the ceramic substrate or inside the ceramic substrate, wherein: the substrate is made of a non-oxide ceramic containing oxygen; and the pore diameter of the maximum pore thereof is 50 ?m or less.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: May 10, 2005
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasuji Hiramatsu, Yasutaka Ito
  • Patent number: 6888236
    Abstract: A ceramic substrate for a semiconductor producing/examining device which has high fracture toughness value, excellent thermal shock resistivity, high thermal conductivity and an excellent temperature rising and falling properties, can be used as a hot plate, an electrostatic chuck, a wafer prober and the like. A ceramic substrate, for a semiconductor producing/examining device, having a conductor formed inside or on the surface thereof has been sintered such that a fractured section thereof exhibits intergranular fracture.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: May 3, 2005
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasuji Hiramatsu, Yasutaka Ito, Atsushi Ozaki
  • Patent number: 6888231
    Abstract: A semiconductor device includes a semiconductor chip, an external connection electrode connected to the chip and a resin package for covering the chip. The resin package includes a mounting surface which faces a supporting substrate. The electrode includes a thick portion and a thin portion. The thick portion is partially exposed to the outside at the mounting surface of the package.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: May 3, 2005
    Assignee: Rohm Co., Ltd.
    Inventor: Masahide Maeda
  • Patent number: 6858929
    Abstract: The invention provides a semiconductor package having a substrate, a top surface and at least one semiconductor device attached to the top surface of the substrate. A cover is secured to the substrate creating a space between the cover and the substrate, with the semiconductor device residing within the space. The cover includes an inner chamber that is defined by an upper wall and a lower wall of the cover. The cavity contains a two-phase vaporizable liquid and a wick. Advantageously, the wick on the lower wall includes at least one recess that forms a thinned wall adjacent to a high heat generation portion of the semiconductor device. In one embodiment, the wick on the lower wall includes at least one channel that communicates with at least one of the recesses.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: February 22, 2005
    Assignee: Thermal Corp.
    Inventors: Jon Zuo, Donald M. Ernst
  • Patent number: 6856076
    Abstract: A plasma display device which improves the adhesion rate of a thermal conductive medium. A chassis base is disposed substantially parallel to a plasma display panel. A thermally conductive medium is disposed between the plasma display panel and the chassis base and is closely adhered to both the plasma display panel and the chassis base. An adhesive pad is interposed between the plasma display panel and the chassis base along the edge of the thermally conductive medium and is adhered to both the plasma display panel and the chassis base. The thermally conductive medium includes a plurality of thermally conductive particles of high thermal conductivity.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: February 15, 2005
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Ki-Jung Kim, Ki-Yun Joung, Tae-Kyoung Kang
  • Patent number: 6856015
    Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; at least one chip mounted on the top surface of the substrate and electrically connected to the substrate; a heat sink attached to the top surface of the substrate by an adhesive material applied therebetween; and a plurality of solder balls implanted on the bottom surface of the substrate. The heat sink has a flat portion and a support portion connected to the flat portion. The support portion has at least one recess portion facing toward the top surface of the substrate and at least one burr formed on an interior surface of the recess portion such that the adhesive material can fill the recess portion and submerge the burr to provide an anchoring effect to firmly secure the heat sink in position on the substrate.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: February 15, 2005
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Cheng-Hsu Hsiao, Shih-Kuang Chiu
  • Patent number: 6853088
    Abstract: A semiconductor module and a method for its fabrication are described. The semiconductor module has at least one semiconductor component that is disposed directly on a substrate body. The substrate body has an insulating ceramic provided with a metal layer. At least one connection conductor is joined to the metal layer by welding, in particular laser microwelding.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: February 8, 2005
    Assignee: EUPEC GmbH
    Inventors: Gottfried Ferber, Reimund Pelmer
  • Patent number: 6849941
    Abstract: A heat sink and heat spreader assembly including a solid member of a conductive material and a layer of a low melting alloy having phase change properties bonded to at least one surface of the solid member such that a welded joint is formed there between possessing a thickness of from 0.0001 to 0.020 inches and having a composition consisting essentially of said low melting alloy with the welded joint having an exposed relatively flat surface suitable for direct attachment to an electronic heat source or heat sink respectively.
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: February 1, 2005
    Assignee: Thermagon, Inc.
    Inventors: Richard Hill, Jason Strader
  • Patent number: 6849938
    Abstract: An object of the present invention is to provide a ceramic substrate for a semiconductor producing/examining device, capable of controlling the temperature of a resistance heating element, thereby suitably controlling the temperature of a semiconductor wafer placed on a ceramic substrate or the like and evenly heating the semiconductor wafer. The ceramic substrate for a semiconductor producing/examining device according to the present invention comprises at least a resistance heating element formed on a surface thereof or inside thereof, wherein a region: where a semiconductor wafer is directly placed; or where a semiconductor wafer is placed apart from the surface thereof while keeping a given distance, exists inside a surface region corresponding to the region where said resistance heating element is formed.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: February 1, 2005
    Assignee: IBIDEN Co., Ltd.
    Inventor: Yasutaka Ito
  • Patent number: 6836014
    Abstract: Method and apparatus for optically testing (e.g., using a laser beam) an operating integrated circuit (device under test—DUT) that actively control the operating temperature of the DUT. This is chiefly useful with flip-chip packaged ICs. The temperature of the DUT varies with its operating power consumption, and this fluctuation in temperature adversely affects the results obtained during optical probing or other optical testing. Furthermore, the DUT may be damaged if its temperature exceeds design limits. The temperature of the DUT is controlled by thermally contacting the exposed backside surface of the DUT die to a diamond film heat conductor, an associated heat sink structure, and at least one thermoelectric device. The thermoelectric device is controlled by a temperature sensor proximal to the DUT. By controlling the amount and direction of the electrical current supplied to the thermoelectric device in response to the sensed temperature, the temperature of the DUT is maintained.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: December 28, 2004
    Assignee: Credence Systems Corporation
    Inventors: Dean M. Hunt, Don Haga
  • Patent number: 6825555
    Abstract: An object of the present invention is to provide a hot plate which is superior in thermal conductivity, is superior in temperature-rising/dropping property, particularly in temperature-dropping property, and has high cooling thermal efficiency at the time of cooling. The hot plate of the present invention is a hotplate comprising: a ceramic substrate; and a resistance heating element formed on the surface of said ceramic substrate or inside said ceramic substrate, wherein said ceramic substrate has a leakage quantity of 10−7 Pa·m3/sec (He) or less by measurement with a helium leakage detector.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: November 30, 2004
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasuji Hiramatsu, Yasutaka Ito
  • Patent number: 6818979
    Abstract: A high-frequency semiconductor device is provided with a ceramic substrate, an element group including semiconductor elements and passive components mounted onto a bottom portion of the ceramic substrate, and a composite resin material layer formed on the bottom portion of the ceramic substrate so as to bury the element group. The composite resin material layer is formed by a composite resin material including an epoxy resin and an inorganic filler material, and has a flat bottom surface on which electrodes for connecting to the outside are formed. As packaging of a structure in which the receiving system and the transmitting system are formed in a single unit, such as an RF module, the high-frequency semiconductor device achieves a small size, a high mounting density, and excellent heat release properties.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: November 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Takehara, Noriyuki Yoshikawa, Kunihiko Kanazawa, Seiichi Nakatani
  • Patent number: 6815810
    Abstract: A high-frequency semiconductor device is provided with a ceramic substrate, an element group including semiconductor elements and passive components mounted onto a bottom portion of the ceramic substrate, and a composite resin material layer formed on the bottom portion of the ceramic substrate so as to bury the element group. The composite resin material layer is formed by a composite resin material including an epoxy resin and an inorganic filler material, and has a flat bottom surface on which electrodes for connecting to the outside are formed. As packaging of a structure in which the receiving system and the transmitting system are formed in a single unit, such as an RF module, the high-frequency semiconductor device achieves a small size, a high mounting density, and excellent heat release properties.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: November 9, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Takehara, Noriyuki Yoshikawa, Kunihiko Kanazawa, Seiichi Nakatani
  • Publication number: 20040207072
    Abstract: It is an object of the present invention to provide a ceramic substrate for a semiconductor producing/examining device which has high fracture toughness value, excellent thermal shock resistivity, high thermal conductivity and an excellent temperature rising and falling properties, and is preferable as a hot plate, an electrostatic chuck, a wafer prober and the like. A ceramic substrate, for a semiconductor producing/examining device, having a conductor formed inside thereof or on the surface thereof of the present invention is the ceramic substrate, wherein said ceramic substrate has been sintered such that a fractured section thereof exhibits intergranular fracture.
    Type: Application
    Filed: January 20, 2004
    Publication date: October 21, 2004
    Applicant: IBIDEN CO., LTD.
    Inventors: Yasuji Hiramatsu, Yasutaka Ito, Atsushi Ozaki
  • Patent number: 6798060
    Abstract: Embodiments of the present invention are directed to packaged power semiconductor devices and direct-bonded metal substrates thereof. In one embodiment, a method for manufacturing a power semiconductor device comprises inserting a substrate assembly into a furnace having a plurality of process zones. The substrate assembly includes a first aluminum layer and a second aluminum layer that are electrically isolated from each other by a dielectric layer. The method further comprises providing the substrate assembly successively into each of the plurality of process zones to bond the first and second aluminum layers to the dielectric layer and obtain a direct bonded aluminum (DAB) substrate, attaching a semiconductor die to the first aluminum layer of the DAB substrate, and forming an enclosure around the semiconductor die and the DAB substrate while exposing a substantial portion of the second aluminum layer for enhanced heat dissipation.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: September 28, 2004
    Assignee: IXYS Corporation
    Inventor: Gerhard Strauch
  • Patent number: 6794747
    Abstract: The present invention provides a semiconductor device comprising as a core substrate a high thermo conductive ceramic substrate having circuit patterns on opposed surfaces. The high thermo conductive ceramic substrate has on one surface a first circuit board of at least one layer having a first cavity structure, and on the other surface a second circuit board of at least one layer having a second cavity structure. A first active element is mounted on the circuit pattern on the high thermo conductive ceramic substrate within the first cavity, a second active element is mounted on the circuit pattern on the high thermo conductive ceramic substrate within the second cavity, an external electrode is integrated with the surface of the second circuit board, and the first circuit board surface is equipped with a cap or sealed with resin.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: September 21, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Takehara, Kunihiko Kanazawa, Noriyuki Yoshikawa
  • Patent number: 6791164
    Abstract: A stereolithographically fabricated package that surrounds at least a portion of a semiconductor die so as to substantially hermetically seal the same. The package may be fabricated from thermoplastic glass, other types of glass, ceramics, or metals. Stereolithographic processes are used to fabricate at least a portion of the substantially hermetic package around the semiconductor dice of assemblies including carrier substrates or leads or around bare or minimally packaged semiconductor dice, including on dice that have yet to be singulated from a wafer. As at least a portion of the substantially hermetic package is stereolithographically fabricated, that portion may include a series of superimposed, contiguous, mutually adhered layers of a suitable hermetic material. The layers can be fabricated by consolidated selected regions of a layer of unconsolidated particulate or powdered material, or by defining an object layer from a sheet of material.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Warren M. Farnworth
  • Patent number: 6791179
    Abstract: A monolithic semiconducting ceramic electronic component includes barium titanate-based semiconducting ceramic layers and internal electrode layers alternately deposited, and external electrodes electrically connected to the internal electrode layers. The semiconducting ceramic layers contain ceramic particles having an average particle size of about 1 &mgr;m or less and the average number of ceramic particles per layer in the direction perpendicular to the semiconductor layers is about 10 or more. The internal electrode layers are preferably composed of a nickel-based metal.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: September 14, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Mitsutoshi Kawamoto
  • Patent number: 6791180
    Abstract: In a ceramic circuit board having a ceramic substrate and a metal circuit plate bonded to one surface of the ceramic substrate, assuming that the warpage of the ceramic circuit board is a difference in height between the center and edge of the metal circuit plate and is positive (+) when the circuit board warps so as to be concave on the side of the metal circuit plate, the warpage of the ceramic circuit board is in the range of from −0.1 mm to +0.3 mm when the ceramic circuit board is heated to 350° C., and in the range of from +0.05 mm to +0.6 mm when the temperature of the ceramic circuit board is returned to a room temperature after the ceramic circuit board is heated to 350° C. The initial warpage of the ceramic circuit board is in the range of from +0.05 mm to +0.6 mm.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: September 14, 2004
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Yukihiro Kitamura, Takayuki Takahashi, Mitsuru Ohta, Yuji Ogawa
  • Patent number: 6787884
    Abstract: A circuit component package of the present invention includes a mounting member including a substrate and a wiring pattern provided on the substrate, a circuit component including a component body and an external electrode provided at an end of the component body, the circuit component being arranged on the mounting member, and a conductive material that electrically connects the external electrode with the wiring pattern. In the circuit component, the component body is shaped so that a first portion of the component body on which the external electrode is provided is thinner than a second portion of the component body, the second portion being a portion on which the external electrode is not provided, and further, the external electrode is arranged in a region on a side on which the component body is positioned with respect to a reference plane containing a predetermined surface of the component body.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: September 7, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hirano, Seiichi Nakatani, Hiroyuki Handa, Tsunenori Yoshida, Yoshihisa Yamashita, Hiroyuki Ishitomi
  • Patent number: 6784551
    Abstract: An electronic device has a semiconductor chip and a passive component, whose electrical values can be varied. The semiconductor chip is electrically conductively connected to a rewiring structure that, together with the semiconductor chip and with the passive component, is enclosed by a housing made of plastic. A method for producing the electronic device is also described.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: August 31, 2004
    Assignee: Infineon Technologies AG
    Inventors: Albert Auburger, Bernd Stadler, Stefan Paulus, Horst Theuss
  • Patent number: 6783867
    Abstract: A highly reliable member for a semiconductor device, in which a high melting point metallizing layer, which consists mainly of a high melting point metal such as W and/or Mo, and an intervening metal layer, which has a melting point of not greater than 1,000° C. and consists mainly of at least one selected from among Ni, Cu and Fe, are provided on an AlN substrate material in this order on the AlN substrate material, and a conductor layer consisting mainly of copper is directly bonded to the intervening metal layer without intervention of a solder material layer. A semiconductor element or the like is mounted on the member for a semiconductor device, thereby fabricating a semiconductor device. The high melting point metallizing layer is formed on an aluminum nitride substrate by post-fire or co-fire metallization.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: August 31, 2004
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazutaka Sasaki, Hirohiko Nakata, Akira Sasame, Mitsunori Kobayashi
  • Patent number: 6784540
    Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: August 31, 2004
    Assignee: International Rectifier Corp.
    Inventor: Charles S. Cardwell
  • Patent number: 6780678
    Abstract: Optical systems for cooling optoelectronic elements are provided. A representative optical system includes a substrate and a first optoelectronic element supported by the substrate. Additionally, a first channel is formed in the substrate and a first heat transfer fluid is arranged in the first channel. The first heat transfer fluid is thermally coupled with the first optoelectronic element so that at least a quantity of heat produced by the first optoelectronic element is dissipated by the first heat transfer fluid. Methods and other systems also are provided.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: August 24, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Jonathan Simon, Ken A. Nishimura
  • Patent number: 6759740
    Abstract: A composite ceramic board comprising an insulating board of insulating layers of alumina ceramics and dielectric layers of ceramics having a dielectric constant smaller than that of said insulating layers which are fired as a unitary structure, and metallized wirings of a low-resistance conductor such as of Au, Ag, Cu or Pl formed on the surfaces and inside thereof, and a method of producing the same. The composite ceramic board not only has a large strength and a high thermal conductivity but also exhibits excellent high-frequency characteristics and is suited for use as a high-frequency wiring board. The invention further provides an optical/electronic-mounted circuit substrate using the above board, and a mounted board having the circuit substrate of the invention connected to an electronic circuit formed on a mother board.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: July 6, 2004
    Assignee: Kyocera Corporation
    Inventors: Masamitsu Onitani, Takeshi Matsui, Shigeki Yamada
  • Patent number: 6756668
    Abstract: A semiconductor package and a method for forming the same are provided. The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A thermal interface material (TIM) is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: June 29, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joong-Hyun Baek, Ho-Jeong Moon, Dong-Kil Shin, Yun-Hyeok Im
  • Patent number: 6720620
    Abstract: A semiconductor device is formed from a semiconductor on insulator substrate, with the insulator or dielectric layer being formed from a polymer precursor to ceramic. The polymer precursor to ceramic may be SiC, diamond, or diamond-like carbon. The resulting device has improved thermal properties, smoothness, dielectric properties, ease of processing, and performance. A method of making the semiconductor device is also disclosed.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: April 13, 2004
    Assignee: Cenymer Corporation
    Inventors: Charles Partee, Scott Joray
  • Patent number: 6697399
    Abstract: A bottom plate (4a) of a box-shaped package (4) is made of a metal. Portions of the package (4) (peripheral wall (4b) and cover plate (4c)) other than the bottom plate (4a) are made of a resin or a ceramic that is more economical than the metal. The material cost of the package (4) can thus be reduced in comparison with the case where the package (4) is made of the metal as a whole. A Peltier module (5) is fixed to the bottom plate (4a). A base (6) is fixed over the Peltier module (5), and a semiconductor laser chip (2) is disposed on this base (6). Heat from the semiconductor laser chip (2) and from the Peltier module (5) can be efficiently radiated through the bottom plate (4a) made of the metal, and deterioration of heat radiation performance can be prevented.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: February 24, 2004
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Toshio Kimura, Takashi Shigematsu, Shinichiro Iizuka, Takeshi Aikiyo
  • Patent number: 6690087
    Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: February 10, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takatoshi Kobayashi, Tadashi Miyasaka, Katsumi Yamada, Akira Morozumi
  • Patent number: 6680527
    Abstract: A monolithic semiconducting ceramic electronic component includes barium titanate-based semiconducting ceramic layers and internal electrode layers alternately deposited, and external electrodes electrically connected to the internal electrode layers. The semiconducting ceramic layers contain ceramic particles having an average particle size of about 1 &mgr;m or less and the average number of ceramic particles per layer in the direction perpendicular to the semiconductor layers is about 10 or more. The internal electrode layers are preferably composed of a nickel-based metal.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: January 20, 2004
    Assignee: Murata Manufacturing Co. Ltd.
    Inventor: Mitsutoshi Kawamoto
  • Publication number: 20040004281
    Abstract: A semiconductor package with a heat sink is provided, wherein a substrate is formed with a metal core layer and at least an opening that penetrates through the substrate. At least a semiconductor chip is mounted on the substrate, with bond pads formed on the semiconductor chip being exposed to the opening, so as to allow the semiconductor chip to be electrically connected to the substrate by a plurality of gold wires that are bonded to the bond pads and formed through the opening. The metal core layer of the substrate provides a grounding plane to improve electrical quality of the semiconductor package, and acts as a heat sink to enhance heat-dissipating efficiency of the semiconductor package. Moreover, an encapsulant for encapsulating the semiconductor chip contains a plurality of thermally conductive metal particles to further facilitate dissipation of heat produced from the semiconductor chip.
    Type: Application
    Filed: October 4, 2002
    Publication date: January 8, 2004
    Inventors: Jin-Chuan Bai, Cheng-Hui Lee
  • Patent number: 6674128
    Abstract: A semiconductor-on-insulator (SOI) device includes a thermoelectric cooler on a back side of the device. The thermoelectric cooler is formed on a thinned portion of a deep bulk semiconductor layer of the SOI device. The thermoelectric device includes a plurality of pairs of opposite conductivity semiconductor material blocks formed on a metal layer deposited on the thinned portion. The thinning of the thinned portion may be accomplished in multiple etching steps of the deep silicon layer, such as a fast etching down to an etch stop and a slower, more controlled etch to the desired thickness for the thinned portion.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: January 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Philip A. Fisher
  • Publication number: 20040000709
    Abstract: An electronic package includes a multi-layer substrate module that includes electrically parallel vias to carry an electrical data signal between two nodes. For example, the vias may be coupled between nodes of different metallization layers in or on the substrate module. Alternatively, the vias may be coupled between a node of one of the metallization layers and a signal transmission line that feeds or receives data signals or an interconnection that connects the multi-layer module to a next higher level of the assembly, such as a printed circuit board. In other implementations, the vias may be coupled between a data signal transmission line and an interconnection to the next-higher level of the assembly.
    Type: Application
    Filed: June 26, 2002
    Publication date: January 1, 2004
    Inventor: Javier Delacruz
  • Patent number: 6670705
    Abstract: A semiconductor device comprises at least one first semiconductor layer (1-4) and a second layer (8) applied on at least a surface portion of the first layer for protecting the device. The protecting layer is of a second material having a larger energy gap between the valence band and the conduction band than a first material forming said first layer. The second material has at least in one portion of said protecting layer a nano-crystalline and amorphous structure by being composed of crystalline gains with a size less than 100 nm and a resistivity at room temperature exceeding 1×1010 &OHgr;cm.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: December 30, 2003
    Assignee: Acreo AB
    Inventors: Christopher Harris, Mietek Bakowski, Jan Szmidt
  • Patent number: 6667548
    Abstract: A semiconductor chip is shown containing an integral heat spreading layer that more effectively transmits heat from the die to ambient as a result of spreading the heat out on the die over a larger cross sectional area. Local hot spots are minimized which allows the semiconductor chip to operate at a higher frequency for a given upper threshold temperature. Also shown is a method of manufacturing such a semiconductor chip, and the associated method of cooling a semiconductor chip.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: Michael O'Connor, Kevin J. Haley, Biswajit Sur
  • Patent number: 6639311
    Abstract: A multilayer ceramic electronic component includes an electronic component body a notch formed in a side surface of the electronic component body, and a joining electrode formed by dividing a joining via hole conductor is formed at a portion of an inside surface defining the notch. A cover that is mounted to the electronic component body has a leg, with the leg of the cover being positioned inside the notch. By joining the leg to the joining electrode, the cover is secured to the electronic component body. The multilayer ceramic electronic component includes an LGA (land grid array) type external terminal electrode. The multilayer ceramic electronic component makes it possible to mount a cover for covering a mounted component without increasing the planar dimensions of the electronic component and without decreasing an area for mounting a component to be mounted.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: October 28, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Norio Sakai, Isao Kato, Mitsuyoshi Nishide
  • Patent number: 6627987
    Abstract: A sealed ceramic package for a semiconductor device and a method of fabricating the same are disclosed. In one embodiment, a ceramic substrate has a set of cavities each having an opening at a substrate top surface. A semiconductor die is disposed within each cavity, and is electrically connected through the substrate to input/output terminals of the substrate. The substrate has a metal film on the top surface thereof around the opening of the respective the cavities. A metal lid panel, covering the cavity openings, is soldered to the metal film by reflowing a layer of solder disposed over a lid panel bottom surface, thereby sealing the die in each cavity. Subsequently, individual packages are singulated from the ceramic substrate.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: September 30, 2003
    Assignee: Amkor Technology, Inc.
    Inventors: Thomas P. Glenn, Roy D. Hollaway, Steven Webster
  • Patent number: 6621158
    Abstract: A die has a part that is sealed with a cap. The seal can be hermetic or non-hermetic. If hermetic, a layer of glass or metal is formed in the surface of the die, and the cap has a layer of glass or metal at a peripheral area so that, when heated, the layers form a hermetic seal. A non-hermetic seal can be formed by bonding a cap with a patterned adhesive. The cap, which can be silicon or can be a metal paddle, is electrically coupled to a fixed voltage to shield the part of the die.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: September 16, 2003
    Assignee: Analog Devices, Inc.
    Inventors: John R. Martin, Carl M. Roberts, Jr.
  • Patent number: 6613443
    Abstract: The present invention provides a silicon nitride ceramic substrate composed of a silicon nitride sintered body in which maximum size of pore existing in grain boundary phase of the sintered body is 0.3 &mgr;m or less, and having a thermal conductivity of 50 W/mK or more and a three point bending strength of 500 MPa or more, wherein a leak current is 1000 nA or less when an alternative voltage of 1.5 kV-100 Hz is applied to a portion between front and back surfaces of the silicon nitride sintered body under conditions of a temperature of 25° C. and a relative humidity of 70%. According to the above structure of the present invention, there can be provided a silicon nitride ceramic substrate capable of effectively suppressing a leak current generation when the above substrate is assembled into various power modules and circuit boards, and capable of greatly improving insulating property and operative reliability of power modules in which output power and capacity are greatly increased.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: September 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michiyasu Komatsu, Haruhiko Yamaguchi, Takayuki Naba, Hideki Yamaguchi
  • Patent number: 6600197
    Abstract: In forming a pair of impurity regions in an active layer, an intrinsic or substantially intrinsic region having a double-sided comb shape is also formed by using a proper mask. The intrinsic or substantially intrinsic region is composed of a portion that effectively functions as a channel forming region and portions in which a channel is not formed and which function as heat sinks. The heat dissipation effect is improved because the heat sinks are formed by the same material as the channel forming region.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: July 29, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Setsuo Nakajima, Takeshi Fukunaga
  • Publication number: 20030111723
    Abstract: A ceramic biomolecule imaging chip includes a ceramic body having a planar imaging surface. The planar imaging surface is highly polished within tolerances of plus or minus 1 microinch. This ceramic chip is compatible with fluorescence laser scanning devices. It is preferred that the ceramic body be 99.6% alumina oxide in order to also be compatible with non-fluorescent detection systems.
    Type: Application
    Filed: October 1, 2002
    Publication date: June 19, 2003
    Applicant: Royce Technologies, Inc.
    Inventor: Fariborz Rahbar-Dehghan
  • Publication number: 20030089975
    Abstract: It is an object of the present invention to provide a ceramic substrate for a semiconductor producing/examining device which has high fracture toughness value, excellent thermal shock resistivity, high thermal conductivity and an excellent temperature rising and falling properties, and is preferable as a hot plate, an electrostatic chuck, a wafer prober and the like. A ceramic substrate, for a semiconductor producing/examining device, having a conductor formed inside thereof or on the surface thereof of the present invention is the ceramic substrate, wherein said ceramic substrate has been sintered such that a fractured section thereof exhibits intergranular fracture.
    Type: Application
    Filed: January 10, 2002
    Publication date: May 15, 2003
    Inventors: Yasuji Hiramatsu, Yasutaka Ito, Atsushi Ozaki
  • Patent number: 6559533
    Abstract: The high-frequency package according to the present invention has a base plate made of copper; a ceramic frame having a space for accommodating a circuit device and mounted on the base plate; and a pattern of circuits developed on the ceramic frame. The base plate and the ceramic frame, and the ceramic frame and the patterned circuits, are both joined together by a DBC technique. According to the present invention, the high-frequency package can be fabricated by a simpler procedure.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: May 6, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumio Yamamoto
  • Publication number: 20030081385
    Abstract: A heat radiating structure for an electronic device, for cooling an electronic part by transferring the heat generated in the electronic part to a heat spreader has a grading layer, which is located between the electronic part and the heat spreader and having a coefficient of thermal expansion varied such that it is substantially equal or approximate at its portion on the electronic part side to the coefficient of thermal expansion of the electronic part and such that it is substantially equal or approximate at its portion on the heat spreader side to the coefficient of thermal expansion of the heat spreader.
    Type: Application
    Filed: September 30, 2002
    Publication date: May 1, 2003
    Applicant: FUJIKURA LTD
    Inventors: Masataka Mochizuki, Yasuhiro Iijima
  • Patent number: 6552395
    Abstract: In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate, involving the steps of providing a first silicon substrate; forming a beryllium oxide layer over the first silicon substrate, the beryllium oxide layer having one of a first thickness from about 100 Å to about 900 Å and a second thickness from about 1,500 Å to about 3,000 Å; forming a first insulation layer over the beryllium oxide layer to provide a first structure; providing a second structure comprising a second silicon layer and a second insulation layer; bonding the first structure and the second structure together so that the first insulation layer is adjacent the second insulation layer; and removing a portion of the second silicon layer thereby providing the silicon-on-insulator substrate.
    Type: Grant
    Filed: January 3, 2000
    Date of Patent: April 22, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Matthew S. Buynoski
  • Patent number: 6544638
    Abstract: An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature Tg greater than 200° C. and a volumetric coefficient of thermal expansion of ≦75 ppm/° C. A semiconductor device is electrically attached to the laminated substrate.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: April 8, 2003
    Assignee: Gore Enterprise Holdings, Inc.
    Inventors: Paul J. Fischer, Joseph E. Korleski
  • Patent number: 6534857
    Abstract: A high power transistor structure comprised of a plurality of field effect transistors fabricated in parallel on a common semiconductor chip and wherein the gate electrodes of the field effect devices are in the form of parallel finger elements having a variable pitch between the fingers which decreases uniformly or non-uniformly from a central portion of the cell to opposite outer end portions thereof.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: March 18, 2003
    Assignee: Northrop Grumman Corporation
    Inventor: Alfred W. Morse
  • Patent number: 6534860
    Abstract: A thermal transfer plate (TTP) includes a thermally conductive plate, at least one footpad and at least one reference protrusion. The footpad includes a spring zone and a standoff member. In an implementation, the reference protrusion contacts a top surface of a substrate. In another implementation, the reference protrusion contacts a top surface of an integrated circuit. Both implementations permit the thickness of the gap between the integrated circuit and the TTP to be optimized for efficient transfer of heat from an integrated circuit.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: March 18, 2003
    Assignee: Intel Corporation
    Inventor: Leonard Turner
  • Patent number: 6525420
    Abstract: The invention provides a semiconductor package having a substrate, a top surface and at least one semiconductor device attached to the top surface of the substrate. A cover is secured to the substrate creating a space between the cover and the substrate, with the semiconductor device residing within the space. The cover includes an inner chamber that is defined by an upper wall and a lower wall of the cover. The cavity contains a two-phase vaporizable liquid and a wick. Advantageously, the wick on the lower wall includes at least one recess that forms a thinned wall adjacent to a high heat generation portion of the semiconductor device. In one embodiment, the wick on the lower wall includes at least one channel that communicates with at least one of the recesses.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: February 25, 2003
    Assignee: Thermal Corp.
    Inventors: Jon Zuo, Donald M. Ernst
  • Publication number: 20030034554
    Abstract: A composite ceramic board comprising an insulating board of insulating layers of alumina ceramics and dielectric layers of ceramics having a dielectric constant smaller than at of said insulating layers which are fired as a unitary structure, and metallized wirings of a low-resistance conductor such as of Au, Ag, Cu or Pt formed on the surfaces and inside thereof, and a method of producing the same. The composite ceramic board not only has a large strength and a high thermal conductivity but also exhibits excellent high-frequency chararteristics and is suited for use as a high-frequency wiring board. The invention further provides an optical/electronic-mounted circuit substrate using the above board, and a mounted board having the circuit substrate of the invention connected to an electronic circuit formed on a mother board.
    Type: Application
    Filed: March 29, 2002
    Publication date: February 20, 2003
    Applicant: KYOCERA CORPORATION
    Inventors: Masamitsu Onitani, Takeshi Matsui, Shigeki Yamada