Abstract: Various embodiments of a compact sensor module are disclosed herein. The sensor module can include a stiffener and a sensor substrate having a mounting segment and a first wing segment extending from the mounting segment. The first wing segment may be folded around an edge of the stiffener. A sensor die may be mounted on the mounting segment of the sensor substrate. A processor substrate may be coupled to the sensor substrate. A processor die may be mounted on the processor substrate and may be in electrical communication with the sensor die.

Abstract: In a manufacturing method of a package carrier, a substrate including a first metal layer, a second metal layer having a top surface and a bottom surface opposite to each other, and an insulating layer between the first and second metal layers is provided. The second metal layer has a greater thickness than the first metal layer. A first opening passing through the first metal layer and the insulating layer and exposing a portion of the top surface of the second metal layer is formed. The first metal layer is patterned to form a patterned conductive layer. Second openings are formed on the bottom surface of the second metal layer. The second metal layer is divided into thermal conductive blocks by the second openings that do not connect the first opening. A surface passivation layer is formed on the patterned conductive layer and the exposed portion of the top surface.

Abstract: The present invention provides an electric circuit device in which it is possible to achieve simultaneously the improvement of cooling performance and reduction in operating loss due to line inductance. The above object can be attained by constructing multiple plate-like conductors so that each of these conductors electrically connected to multiple semiconductor chips is also thermally connected to both chip surfaces of each such semiconductor chip to release heat from the chip surfaces of each semiconductor chip, and so that among the above conductors, a DC positive-polarity plate-like conductor and a DC negative-polarity plate-like conductor are opposed to each other at the respective conductor surfaces.

Abstract: A multi-chip module (MCM) structure comprises more than one semiconductor chip lying in a horizontal plane, the MCM having individual chip contact patches on the chips and a flexible heat sink having lateral compliance and extending in a plane in the MCM and secured in a heat exchange relation to the chips through the contact patches. The MCM has a mismatch between the coefficient of thermal expansion of the heat sink and the MCM and also has chip tilt and chip height mismatches. The flexible heat sink with lateral compliance minimizes or eliminates shear stress and shear strain developed in the horizontal direction at the interface between the heat sink and the chip contact patches by allowing for horizontal expansion and contraction of the heat sink relative to the MCM without moving the individual chip contact patches in a horizontal direction.

Abstract: Micro-plasma is generated at the tip of a micro-spring by applying a positive voltage to the spring's anchor portion and a negative voltage to an electrode maintained a fixed gap distance from the spring's tip portion. By generating a sufficiently large voltage potential (i.e., as determined by Peek's Law), current crowding at the tip portion of the micro-spring creates an electrical field that sufficiently ionizes neutral molecules in a portion of the air-filled region surrounding the tip portion to generate a micro-plasma event. Ionic wind air currents are generated by producing multiple micro-plasma events using micro-springs disposed in a pattern to produce a pressure differential that causes air movement over the micro-springs. Ionic wind cooling is produced by generating such ionic wind air currents, for example, in the gap region between an IC die and a base substrate disposed in a flip-chip arrangement.

Abstract: A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate. Moreover, the heat sink has a thickness of 500 ?m to 2 mm, and may be formed to be thicker than the semiconductor substrate. By using the heat sink to reinforce the substrate, a thickness of the semiconductor substrate can be reduced to, for example, about 50 ?m. As a result, a thickness of the entire semiconductor device can be reduced.

Abstract: Magnetic fluid cooling devices and power electronic devices are disclosed. In one embodiment, a magnetic fluid cooling device includes a magnetic field generating device, a magnetic fluid chamber assembly, and a heat sink device. The magnetic field generating device includes a plurality of magnetic regions having alternating magnetic directions such that magnetic flux generated by the magnetic field generating device is enhanced on a first side of the magnetic field generating device and inhibited on a second side of the magnetic field generating device. The magnetic fluid chamber assembly defines a magnetic fluid chamber configured to receive magnetic fluid. The heat sink device includes a plurality of extending fins, and is thermally coupled to the magnetic fluid chamber assembly. Power electronic devices are also disclosed, wherein the magnetic fluid chamber may be configured as opened or closed.

Abstract: A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact.

Abstract: A semiconductor module includes an insulating substrate (200) that is made of AlN and that has a first plane (201) and a second plane (202) both of which face mutually opposite directions, a first conductor layer (210) formed on the first plane (201), a second conductor layer (220) formed on the second plane (202), a semiconductor device (300) bonded to the first conductor layer (210) with a first solder layer (510) interposed therebetween, and a heat dissipation plate (400) that is formed in a rectangular shape when viewed planarly and that is bonded to the second conductor layer (220) with a second solder layer (520) interposed therebetween, and, in this semiconductor module, the heat dissipation plate (400) is deformed so as to become convex in a direction in which the second plane (202) is pointed when viewed from a width direction thereof.

Abstract: An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The integrated circuit having circuit blocks, that operate at different operating voltages and voltage regulator modules die bonded to the second bond pads of the integrated circuit. The voltage regulator modules converting a power supply voltage to the operating voltage of a respective circuit block and supply the respective operating voltage to the circuit block via the second bond pads.

Abstract: A semiconductor module may include a heat-transferring part connecting at least one of a control device, a buffer semiconductor device, and a memory device to a connector. The heat-transferring part may be configured to have a thermal conductivity higher than the substrate. Accordingly, during the operation of the semiconductor module, the connector can have a temperature lower than the devices.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a conductive connector over the package carrier; forming an encapsulation over the integrated circuit, the encapsulation having a recess exposing the conductive connector; and mounting a heat slug over the encapsulation, the heat slug having an opening with an opening width greater than a recess width of the recess, the opening exposing a portion of a top surface of the encapsulation.

Abstract: A composite structure 10 of a resin-diamagnetic material, including a diamagnetic material layer 12 and a resin layer 14 is obtained by a method including disposing particles of a diamagnetic material 22 and a resin 24 in a mold 30, applying a magnetic field to the diamagnetic material 22 disposed in the mold 30, and moving the diamagnetic material 22 in a direction away from at least a part of an inner surface of the mold 30, and then curing the resin 24 in the mold 30 thereby to produce a resin-diamagnetic material composite structure.

Abstract: A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a package stack assembly, having a contact pad, on the base substrate; applying an encapsulation having a cavity with a tapered side directly over the package stack assembly, the contact pad exposed in the cavity; attaching a recessed circuitry unit in the cavity and on the contact pad, a chamber of the cavity formed by the recessed circuitry unit and the tapered side of the cavity; and mounting a thermal structure over the recessed circuitry unit, the cavity, and the encapsulation.

Abstract: A device with an external surface, the device including: a substrate including first mono-crystal transistors; a second layer including second mono-crystal transistors, the second mono-crystal transistors overlaying the first mono-crystal transistors; and a plurality of thermal conduction paths from a plurality of the second layer locations to the external surface, wherein at least one of the thermal conduction paths includes an electrically nonconductive contact.

Abstract: An illumination device (1) having comprising at least one support element (4) and at least one light-emitting diode (5) arranged on the support element (4), characterized in that wherein at least one of the plurality of components (2, 3, 4, 7, 10) of the illumination device (1) intended for heat dissipation from the light-emitting diode (5), in particular the support element (4), is provided at least in part with an electrically insulating layer (6, 11) having a high thermal conductivity, formed at least in part from a carbon compound, in particular from amorphous carbon, in particular tetrahedral amorphous carbon.

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. The upper card includes one of a photosensor, light emitting element, radio frequency (RF) antenna, and radio frequency emitter. The lower card includes an area array input/output.

Abstract: Disclosed herein is a power module package including: a body member having a polyhedral shape and made of a metal material; a semiconductor device mounted on the body member; and a block member formed at an edge region of the body member and made of a metal material.

Abstract: Carbon nanotube material is used in an integrated circuit substrate. According to an example embodiment, an integrated circuit arrangement (100) includes a substrate (110) with a carbon nanotube structure (120) therein. The carbon nanotube structure is arranged in one or more of a variety of manners to provide structural support and/or thermal conductivity. In some instances, the carbon nanotube structure is arranged to provide substantially all structural support for an integrated circuit arrangement. In other instances, the carbon nanotube structure is arranged to dissipate heat throughout the substrate. In still other instances, the carbon nanotube structure is arranged to remove heat from selected portions of the carbon nanotube substrate.

Abstract: A three dimensional (3D) integrated circuit (IC) structure having improved power and thermal management is described. The 3D IC structure includes at least first and second dies. Each of the first and second dies has at least one power through silicon via (TSV) and one signal TSV. The at least one power and signal TSVs of the first die are connected to the at least one power and signal TSVs of the second die, respectively. The 3D IC structure also includes one or more peripheral TSV structures disposed adjacent to one or more sides of the first and/or the second die. The peripheral TSV structures supply at least power and/or signals.

Abstract: In a semiconductor device including semiconductor modules, it is possible to average the temperatures of the semiconductor modules. At least two semiconductor modules, wherein a plurality of semiconductor circuits, on which are mounted one or more semiconductor chips having a gate terminal and gate resistors connected to the gate terminals, are disposed in parallel, are disposed above a cooling body so that an array direction of the semiconductor circuits is a direction intersecting a refrigerant flow. At least one temperature detecting resistor is disposed in each semiconductor module, a gate signal is supplied to a gate signal input terminal of one semiconductor module of the at least two semiconductor modules via the temperature detecting resistor of the other semiconductor module, and a gate signal is supplied to a gate signal input terminal of the other semiconductor module via the temperature detecting resistor of the one semiconductor module.

Abstract: An interconnection component includes a substrate, and an active through-substrate via (TSV) penetrating through the substrate. Active metal connections are formed over the substrate and electrically connected to the active TSV. At least one of a dummy pad and a dummy solder bump are formed at surfaces of the interconnection component. The dummy pad is over the substrate and electrically connected to the active TSV and the active metal connections. The dummy solder bump is under the substrate and electrically connected to the active metal connections. The dummy pad and the dummy solder bump are open ended.

Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.

Abstract: A power semiconductor circuit device and a method for manufacturing the same, both of which are provided with: a base board on which at least a power semiconductor element is mounted; a resin which molds the base board and the power semiconductor element in a state where partial surfaces of the base board, including a base board surface opposite to a surface on which the power semiconductor element is mounted, are exposed; and a heat dissipating fin joined to the base board by a pressing force. A groove is formed in the base board at a portion to be joined to the heat dissipating fin, and the heat dissipating fin is joined by caulking to the groove.

Abstract: A power module includes: a sealing body including a semiconductor element having a plurality of electrode surfaces, a first conductor plate connected to one electrode surface of the semiconductor element via solder, and a sealing material for sealing the semiconductor element and the first conductor plate, the sealing body having at least a first surface and a second surface on the opposite side of the first surface; and a case for housing the sealing body. The case is configured by a first heat radiation plate opposed to the first surface of the sealing body, a second heat radiation plate opposed to the second surface of the sealing body, and an intermediate member that connects the first heat radiation plate and the second heat radiation plate. The intermediate member has a first thin section having thickness smaller than the thickness of the first heat radiation plate, more easily elastically deformed than the first heat radiation plate, and formed to surround the first heat radiation plate.

Abstract: A circuit board is provided with a plurality of arms and a heat radiation plate. The insulating substrate of the each of the arms includes: a passive element region to which a passive element is connected; an active element region to which an active element is connected; and a wiring region on which wiring lines of the element group are laid. In the each of the arms, the passive element region, the active element region and the wiring region align in a lengthwise direction of the insulating substrate, and the passive element region and the wiring region are arranged on both sides of the active element region which is located centrally.

Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has a package substrate, an integrated circuit die attached to the package substrate, and a package level heat dissipation device, such as an integrated heat spreader, attached to the package substrate encapsulating the integrated circuit die. The package level heat dissipation device has a top side with a ridge formed on top of a perimeter of the top side, and a bottom side that couples to the integrated circuit die.

Abstract: A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.

Abstract: A power converter including: a plurality of semiconductor devices forming a power conversion circuit; a base section to which the plurality of semiconductor devices are attached; and radiating fins dissipating heat generated from the semiconductor devices into outside air, in the power converter in which the direction of the flow of a refrigerant flowing into the radiating fins changes depending on the operation status of the power conversion circuit, the shape of each radiating fin changes in such a way that the cross-sectional area of a channel of the refrigerant on the outflow side becomes smaller than the cross-sectional area of the channel of the refrigerant on the inflow side in the radiating fins depending on the direction of the flow of the refrigerant.

Abstract: A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a first radiator member arranged on and thermally coupled to the semiconductor element, and a second radiator member arranged on and thermally coupled to the first radiator member. The second radiator member includes projections which project out toward the first radiator member. The projections are formed on a circumference of a concentric circle with respect to a center point of the second radiator member. The first radiator member includes grooves in which the projections are movable. The grooves are formed on a circumference of a concentric circle with respect to a center point of the first radiator member. The projections are fitted to terminating ends of the grooves with the center point of the first radiator member and the center point of the second radiator member coincided.

Abstract: A semiconductor power module includes an active element and a passive element serving as semiconductor elements each having a first electrode on a front surface and a second electrode on a back surface thereof, a heat pipe having a first region defined as arrangement parts of the active element and the passive element on its one end side and electrically connected to one of the first and second electrodes of the active element and the passive element arranged in the first region, a cooling fin arranged in a second region defined on the other end side of the heat pipe, and a heat pipe provided to sandwich the active element, the passive element, and the cooling fin arranged on the heat pipe along with the heat pipe and electrically connected to the other of the first and second electrodes of the active element and passive element.

Abstract: A heat sink includes a first adhesive layer, and a heat dissipation layer disposed on the first adhesive layer, and has ventilation ports that extend therethrough including through the first adhesive layer and the heat dissipation layer. The heat sink forms an outermost part of a semiconductor package. Thus, when the heat sink is bonded via its adhesive layer to underlying structure during a manufacturing process, the ventilation ports allow air to pass therethrough. As a result, air is not trapped in the form of bubbles between the heat sink and the underlying structure.

Abstract: A heat spreader for an integrated circuit has a base portion and a top portion. The base portion is attachable to a surface of the integrated circuit, and has at least one channel extending therethrough. The top portion that is larger than the base portion such that the heat spreader is generally T-shaped in cross-section. The top portion has a hole at its center that extends from a top surface of the top portion to the at least one channel of the base portion. Mold compound is injected through the hole and out through the channels.

Abstract: The present invention relates to a semiconductor device and a method of manufacture thereof, particularly, to a semiconductor device including a vertical type gate and a method of forming the same. According to the present invention, a semiconductor device includes a vertical pillar which is protruded from a semiconductor substrate, has a vertical channel, and has a first width; an insulating layer which has a second width smaller than the first width, provided in both sides of the vertical pillar which is adjacent in a first direction; and a nitride film provided in a side wall of the insulating layer.

Abstract: One or more heating elements are disposed on a semiconductor substrate proximate a temperature sensitive circuit disposed on the substrate (e.g., bandgap circuit, oscillator). The heater element(s) can be controlled to heat the substrate and elevate the temperature of the circuit to one or more temperature points. One or more temperature measurements can be made at each of the one or more temperature points for calibrating one or more reference values of the circuit (e.g., bandgap voltage).

Abstract: Disclosed herein is a method of manufacturing a bonded substrate, including the steps of: forming a first bonding layer on a surface on one side of a semiconductor substrate; forming a second bonding layer on a surface on one side of a support substrate; adhering the first bonding layer and the second bonding layer to each other; a heat treatment for bonding the first bonding layer and the second bonding layer to each other; and thinning the semiconductor substrate from a surface on the other side of the semiconductor substrate to form a semiconductor layer.

Abstract: An assembly includes an integrated circuit die coupled to another component of the assembly with an alkali silicate glass material. The alkali silicate material may include particles for modifying the thermal, mechanical, and/or electrical characteristics of the material.

Abstract: A heatsink may include an area in thermal contact with a semiconductor microchip surface and a first trench of a first depth. The first trench may be substantially continuous around the area. A first substance, such as ferrite, may be positioned in the first trench to attenuate electromagnetic interference. A second trench having a second depth may be formed around and further from the area than the first trench. A second substance may be positioned in the second trench.

Abstract: A semiconductor device includes a package and a cooler. The semiconductor package includes a semiconductor element, a metal member, and a molding member for encapsulating the semiconductor element and the metal member. The metal member has a metal portion thermally connected to the semiconductor element, an insulating layer on the metal portion, and a conducting layer on the insulating layer. The conducting layer is at least partially exposed outside the molding member and serves as a radiation surface for radiating heat of the semiconductor element. The cooler has a coolant passage through which a coolant circulates to cool the conducting layer. The conducting layer and the cooler are electrically connected together.

Abstract: To provide a mounting structure of a semiconductor device/electronic component that suppresses temperature rise of a semiconductor device and/or an electronic component having large power consumption due to heat generation thereof, resulting in stable operation. The mounting comprises an interposer 10; a semiconductor device 11 mounted on the surface 10a of the interposer 10; and a cover 12 that forms an inner space S along with the interposer 10; wherein the cover 12 is closely adhered and fixed on the surface 10a of the interposer 10 to so as to include the semiconductor device 11. The cover 12 has an inlet 13 for introducing a heat-absorbing fluid L from outside, and an outlet 14 for discharging the fluid L from the inner space S to outside. The inner space S is a closed space excluding the inlet 13 and the outlet 14.

Abstract: A semiconductor chip includes a semiconductor substrate including a first surface and a second surface, an integrated circuit (IC) on the first surface of the semiconductor substrate, and a heat radiation portion on the second surface of the semiconductor substrate. The heat radiation portion includes heat radiation patterns in a direction perpendicular to the second surface, and a heat radiation layer on upper portions of the heat radiation patterns. The heat radiation patterns include a plurality of recesses and a plurality of protrusions and the heat radiation layer includes a metal material and has a flat upper surface.

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

Abstract: An LED module includes a plurality of lighting sources each including a substrate, a first and second lead frames arranged on the substrate, an LED chip electrically connected to the first and the second lead frames, and an encapsulation covering the LED chip. The first lead frame of each of the lighting sources connects with the second lead frame of an adjacent lighting source electrically and mechanically.

Abstract: To reduce the thermal stresses that may be caused by a difference in thermal expansion coefficients between a molded casing and an active side of a semiconductor device embedded in the molded casing, and thus reduce the number of corresponding failures caused by the thermal stresses, the active side of the semiconductor device is arranged face-down, towards a substrate supporting the semiconductor device. The semiconductor device includes a through via that electrically connects the active side of the semiconductor device to a passive side of the semiconductor device. A wire bond electrically connects the passive side of the semiconductor device to the substrate. To increase the dissipation of heat generated in the semiconductor device, a thermally conductive slug may be disposed in the substrate, and the active side of the semiconductor device may be attached to the thermally conductive slug.

Abstract: In a manufacturing method of a package carrier, a substrate including a first metal layer, a second metal layer having a top surface and a bottom surface opposite to each other, and an insulating layer between the first and second metal layers is provided. The second metal layer has a greater thickness than the first metal layer. A first opening passing through the first metal layer and the insulating layer and exposing a portion of the top surface of the second metal layer is formed. The first metal layer is patterned to form a patterned conductive layer. Second openings are formed on the bottom surface of the second metal layer. The second metal layer is divided into thermal conductive blocks by the second openings that do not connect the first opening. A surface passivation layer is formed on the patterned conductive layer and the exposed portion of the top surface.

Abstract: A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate.

Abstract: A method and apparatus for mounting microelectronic chips to a thermal heat sink. The chips are arranged in a desired configuration with their active faces all facing a common direction and with their active faces defining a common planar surface for all of said chips. A metallic material is applied to the chip, preferably by electroplating to backsides of the chips, the metallic material being electro-formed thereon and making void-free contact with the backsides of the chips.

Abstract: An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound.