Abstract: A method of manufacturing an integrated circuit having a substrate comprising a plurality of components and a metallization stack over the components, the metallization stack comprising a first sensing element and a second sensing element adjacent to the first sensing element.

Abstract: An electronic device including a printed circuit board (PCB) including a thermal conduction plane and at least one heat generating component mounted on the PCB and connected to the thermal conduction plane. A frame is connected to the PCB so as to define a first thermally conductive path between at least a portion of the frame and the at least one heat generating component. The electronic device further includes at least one thermally conductive layer between the frame and the at least one heat generating component so as to define a second thermally conductive path between at least a portion of the frame and the at least one heat generating component.

Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

Abstract: Disclosed is a luminaire, comprising a front convective heat sink, a rear convective heat sink, and a removable thin printed circuit board. The front convective heat sink has at least one optical aperture. The removable thin printed circuit board has an electrically-insulated back surface and a selectively electrically-insulated front surface. The front surface has exposed electrical contacts in at least one area corresponding to the at least one optical aperture. The removable thin printed circuit board is sandwiched between the front and rear convective heat sinks with a compressive force.

Abstract: A semiconductor device includes an insulation layer, a first semiconductor element and a second semiconductor element which are disposed within the insulation layer, a frame which has higher thermal conductivity than the insulation layer and surrounds the first semiconductor element and the second semiconductor element via the insulation layer, and a wiring layer which is disposed over the insulation layer and includes an electrode which electrically connects the first semiconductor element and the second semiconductor element.

Abstract: A housing for integrated devices that includes an air-release mechanism is disclosed. This is achieved, in various embodiments, by forming a vent hole in a package substrate, and arranging a package lid over the package substrate. The vent hole allows air to be released from within the cavity package, thereby ensuring that the package lid remains stably affixed to the package substrate despite increased temperatures during processing. The vent hole may be sealed upon mounting the package onto a mounting substrate.

Abstract: An integrated circuit package strip employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.

Abstract: A thermal interface material facilitates heat transfer between an integrated circuit device and a thermally conductive device. According to an example embodiment, a thermal interface material includes carbon nanotube material that enhances the thermal conductivity thereof The interface material flows between an integrated circuit device and a thermally conductive device. The carbon nanotube material conducts heat from the integrated circuit device to the thermally conductive device.

Abstract: An apparatus includes a base plate including a plurality of depressions, and a power electronics printed circuit board including a plurality traces and a plurality of high voltage components. The plurality of high voltage components is located at a plurality of locations corresponding to the plurality of depressions in the base plate. A plurality of fasteners secures the printed circuit board to the base plate with the plurality of high voltage components received at the corresponding plurality of depressions. A thermally conductive and electrically isolating interface between the base plate and the printed circuit board is made of a gap filler material conforming to the base plate and to the plurality of depressions in the base plate, and conforming to the printed circuit board and to the plurality of high voltage components.

Abstract: A LED module with separate heat-dissipation and electrical conduction paths is disclosed, having a metal substrate; a plastic layer, including one or more hollow regions, and attached to the metal substrate; one or more conducting elements attached to the plastic layer; one or more LED chips positioned in the one or more hollow regions of the plastic layer and directly attached to the metal substrate; and a plurality of conducting wires for electrically connecting the one or more conducting elements and the one or more LED chips; wherein inner sides of the one or more hollow regions include one or more inclined surfaces each having an included angle with an upper surface of the metal substrate, and the included angle is between 90˜180 degrees.

Abstract: Embodiments of the present disclosure describe techniques and configurations for paste thermal interface materials (TIMs) and their use in integrated circuit (IC) packages. In some embodiments, an IC package includes an IC component, a heat spreader, and a paste TIM disposed between the die and the heat spreader. The paste TIM may include particles of a metal material distributed through a matrix material, and may have a bond line thickness, after curing, of between approximately 20 microns and approximately 100 microns. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe techniques and configurations for molded heat spreaders. In some embodiments, a heat spreader includes a first insert having a first face and a first side, the first face positioned to form a bottom surface of a first cavity, and a second insert having a second face and a second side, the second face positioned to form a bottom surface of a second cavity. The second cavity may have a depth that is different from a depth of the first cavity. The heat spreader may further include a molding material disposed between the first and second inserts and coupled with the first side and the second side, the molding material forming at least a portion of a side wall of the first cavity and at least a portion of a side wall of the second cavity. Other embodiments may be described and/or claimed.

Abstract: A lead frame for assembling a semiconductor device has a die pad surrounded by lead fingers. Each of the lead fingers has a proximal end close to but spaced from an edge of the die pad and a distal end farther from the die pad. A semiconductor die is attached to a surface of the die pad. The die has die bonding pads on its upper surface that are electrically connected to the proximal ends of the lead fingers with bond wires. An encapsulation material covers the bond wires, semiconductor die and the proximal ends of the lead fingers. Prior to assembly, hot spots of the die are determined and the lead fingers closest to the hot spots are selected to project closer to the die than the other lead fingers. These longer lead fingers assist in dissipating the heat at the die hot spot.

Abstract: A packaged semiconductor device includes a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.

Abstract: An insulating body incorporates at least one integrated circuit chip and includes a mounting surface for mounting to a board and a free surface opposite the mounting surface. A heatsink is attached to the insulating body at the free surface. The heatsink includes at least one stabilizing element. The stabilizing element includes an attachment portion extending at least partially transversely to the free surface beyond a peripheral boundary of the free surface when considered in plan view. The attachment portion has a binding end bound to the free surface and a free end opposite the binding end. The stabilizing element also has a mounting portion extending from the free end of the attachment portion at least up to a plane of the mounting surface.

Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and conductive layer formed over the substrate. A first encapsulant is deposited over the substrate outside a die attach area of the substrate. The first encapsulant surrounds each die attach area over the substrate and the die attach area is devoid of the first encapsulant. A channel connecting adjacent die attach areas is also devoid of the first encapsulant. A first semiconductor die is mounted over the substrate within the die attach area after forming the first encapsulant. A second semiconductor die is mounted over the first die within the die attach area. An underfill material can be deposited under the first and second die. A second encapsulant is deposited over the first and second die and first encapsulant. The first encapsulant reduces warpage of the substrate during die mounting.

Abstract: Various stress relief structures are provided for effectively reducing thermal stress on a semiconductor chip in a chip package. Trenches on a metal substrate are created in groups in two-dimension, where each trench is opened from top or bottom surface of the metal substrate and in various shapes. The metal substrate is partitioned into many smaller substrates depending on the number of trench groups and partitions, and is attached to a semiconductor chip for stress relief. In an alternative embodiment, a plurality of cylindrical metal structures are used together with a metal substrate in a chip package for the purpose of heat removal and thermal stress relief on a semiconductor chip. In another alternative embodiment, a metal foam is used together with a semiconductor chip to create a chip package. In another alternative embodiment, a semiconductor chip is sandwiched between a heat sink and a circuit board by solder bumps directly with underfill on the circuit board.

Abstract: According to one embodiment, a semiconductor module has a substrate, two nonvolatile memories disposed on a first surface of the substrate, a controller to control the nonvolatile memories, disposed on the first surface of the substrate and between the two nonvolatile memories, and a plurality of terminals that are electrically connected to the two nonvolatile memories and to the controller, disposed on a second surface of the substrate.

Abstract: A power train assembly is provided. The power train assembly includes a component package including a first transistor having a first gate, a first drain, and a first source, a second transistor having a second gate, a second drain, and a second source, and a thermal pad configured to dissipate heat generated in the component package, wherein the thermal pad is electrically coupled to the first source and the second drain. The power train assembly further includes a printed circuit board (PCB) electrically coupled to the component package, and an electrical component electrically coupled directly to the thermal pad, wherein the electrical component is external to the component package.

Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.

Abstract: The present disclosure is directed to a device that includes a first substrate having a first plurality of hollow pillars on the first substrate and a first plurality of channels in the first substrate coupled to the first plurality of hollow pillars. The device includes a second substrate attached to the first substrate, the second substrate having a second plurality of hollow pillars on the second substrate and a second plurality of channels in the second substrate coupled to the second plurality of hollow pillars, the first plurality of hollow pillars being coupled to the second plurality of hollow pillars to allow a fluid medium to move through the substrate to cool the first substrate and the second substrate.

Abstract: A system and method for manufacturing an electric device package are disclosed. An embodiment comprises a carrier, a component disposed on the carrier, the component having a first component contact pad, and a first electrical connection between the first component contact pad and a first carrier contact pad, wherein the first electrical connection comprises a first hollow space, the first hollow space comprising a first liquid.

Abstract: An object is to provide a semiconductor device having a plate electrode adapted to a plurality of chips, capable of being produced at low cost, and having high heat cycle property. A semiconductor device according to the present invention includes a plurality of semiconductor chips formed on a substrate, and a plate electrode connecting electrodes of the plurality of semiconductor chips. The plate electrode has half-cut portions formed by half-pressing and the raised sides of the half-cut portions are bonded with the electrodes of the semiconductor chips.

Abstract: A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.

Abstract: An apparatus for cooling a semiconductor element is provided. The apparatus can include an electron emitter configured to emit electrons such that at least some of the emitted electrons become attached to air particulates and an air accelerator configured to generate an electric field that accelerates the air particulates toward the air accelerator to create an air flow over at least a portion of the semiconductor element. The air flow carries heat away from the at least a portion of the semiconductor element.

Abstract: A semiconductor device is formed by molding using a resin with a semiconductor element and one or two heat dissipating plates contained therein, said one or two heat dissipating plates being disposed to face one surface or both the surfaces of the semiconductor element. An intermediate layer is formed by spraying a metal powder to the semiconductor element and to one of or both of the heat dissipating plates using a cold spray method, and the semiconductor element and the heat dissipating plate are bonded together using a solder with the intermediate layer therebetween.

Abstract: Integrated circuit packaging devices and methods are disclosed. An embodiment package lid is formed from a single piece of material. The lid includes a planar rectangular main body having a bottom surface, and a leg disposed at each corner of the main body and within a perimeter of the main body. Each leg has a wall projecting downwardly from the main body and a non-planar bottom surface disposed at a bottom of the wall. The non-planar bottom surface of the leg faces a same direction as the main body bottom surface.

Abstract: According to an exemplary embodiment, a power semiconductor package includes a power module having a plurality of power devices. Each of the plurality of power devices can be a power switch. The power semiconductor package also includes a double-sided heat sink with a top side in contact with a plurality of power device top surfaces and a bottom side in contact with a bottom surface of the power module. The power semiconductor package can include at least one fastening clamp pressing the top side and the bottom side of the double-sided heat sink into the power module. The double-sided heat sink can also include a water-cooling element.

Abstract: A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.

Abstract: A method for enhancing internal layer-layer thermal interface performance and a chip stack of semiconductor chips using the method. The method includes adding a thermosetting polymer to the thermal interface material, dispersing a plurality of nanofibers into the thermal interface material, and un-crosslinking the thermosetting polymer in the thermal interface material. The method further includes extruding the thermal interface material through a die to orient the conductive axis of the nanofibers and polymer chains in the desired direction, and re-crosslinking the thermosetting polymer in the thermal interface material. The chip stack includes a first chip with circuitry on a first side, a second chip coupled to the first chip by a grid of connectors, and a thermal interface material pad between the chips. The thermal interface includes nanofibers and a polymer that allows for optimal alignment of the nanofibers and polymer chains.

Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.

Abstract: A method of assembling a semiconductor chip device is provided that includes providing a circuit board including a surface with an aperture. A portion of a first heat spreader is positioned in the aperture. A stack is positioned on the first heat spreader. The stack includes a first semiconductor chip positioned on the first heat spreader and a substrate that has a first side coupled to the first semiconductor chip.

Abstract: An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material.

Abstract: Terminal assembly portions, lying on a front surface side of a case, are aligned in a left-right direction in a portion raised from a bottom of the case so that opening faces of the terminal assembly portions are positioned above circuit formation regions. Wiring terminal plates are led out into the terminal assembly portions, and disposed adjacent to each other. After each wiring terminal plate is connected by a laser welding to one end of one external connection terminal plate formed integrally with a cover, these welded portions are sealed with a second mold resin portion made of gel or an insulating resin such as epoxy. By so doing, even when the terminal junction area and distance between terminal junctions in the terminal assembly portions are small, it is possible to increase the joint strength of the terminals, and also secure withstand voltage.

Abstract: A lithium battery includes a cathode, an anode including a component made of silicon, a separator element disposed between the cathode and the anode, an electrolyte, and a substrate. The anode is disposed over the substrate or the anode is integrally formed with the substrate.

Abstract: Certain embodiments provide a semiconductor device including a first substrate, a circuit element, a second substrate, a metal layer, and a radiation plate. The circuit element is formed on a front surface of the first substrate and has an electrode. The second substrate has a first face, and is laminated on the first substrate so that the first face of the second substrate faces a front surface of the first substrate. The second substrate has a via hole arranged on the electrode. The metal layer is formed inside of the via hole. The radiation plate is formed on a second face of the second substrate, and is connected to the metal layer.

Abstract: An integrated circuit chip package is described. The integrated circuit package comprises a substrate, a chip attached to the substrate, and a heat spreader mounted over the chip for sealing the chip therein. The heat spreader includes a thermally-conductive element having a side opposed to the top of the chip for transmitting heat away from the chip to the heat spreader, and a compliant element having a first portion attached to and positioned around the periphery of the thermally-conductive element and a second portion affixed to a surface of the substrate.

Abstract: A method of forming a heat-dissipating structure for semiconductor circuits is provided. First and second semiconductor integrated circuit (IC) chips are provided, where the first and second semiconductor chips each have first and second opposing sides, wherein the first and second semiconductor IC chips are configured to be fixedly attached to a top surface of a substantially planar circuit board along their respective first sides. The respective second opposing sides of each of the first and second semiconductor IC chips are coupled to first and second respective portions of a sacrificial thermal spreader material, the sacrificial thermal spreader material comprising a material that is thermally conductive. The first and second portions of the sacrificial thermal spreader material are planarized to substantially equalize a respective first height of the first semiconductor chip and a respective second height of the second semiconductor chip.

Abstract: An electronic component package and a manufacturing method thereof are disclosed. The electronic component package manufacturing method, which includes mounting an electronic component in one surface of a first insulation layer; bonding a heat sink to the one surface of the first insulation layer, corresponding to the electronic component, to cover the electronic component, the heat sink being formed with a cavity; charging the cavity with an adhesive; and forming a circuit pattern in the other surface of the first insulation layer, can prevent a void from being generated in the adhesive, make the handling stable and make the size small by allowing the heat sink formed with the cavity to cover the electronic component before the pattern build-up and supplying the adhesive through one side of the cavity while providing negative pressure through the other side.

Abstract: Provided is a stacked semiconductor device (50) in which a semiconductor package (5) is stacked via connection terminals (8) on a semiconductor package (1), including a heat dissipating member (10) which is disposed between the semiconductor packages (1, 5), is brought into thermal contact with both of the packages (1, 5), and hangs over whole outer peripheral portions of the package (5). Such a structure causes heat generated from the package (5) to be released by heat dissipation into air above the package (5), heat dissipation into the air below the semiconductor package (5), heat transfer via the heat dissipating member (10) and a semiconductor element (3) to a first wiring substrate (2), heat transfer via the connection terminals (8) to the first wiring substrate (2), and heat dissipation via the heat dissipating member (10) into the air, thereby enhancing a temperature reduction effect of the semiconductor element.

Abstract: A method and structures are provided for implementing enhanced thermal conductivity between a lid and heat sink for stacked modules. A chip lid and lateral heat distributor includes cooperating features for implementing enhanced thermal conductivity. The chip lid includes a groove along an inner side wall including a flat wall surface and a curved edge surface. The lateral heat distributor includes a mating edge portion received within the groove. The mating edge portion includes a bent arm for engaging the curved edge surface groove and a flat portion. The lateral heat distributor is assembled into place with the chip lid, the mating edge portion of the lateral heat distributor bends and snaps into the groove of the chip lid. The bent arm portion presses on the curved surface of the groove, and provides an upward force to push the flat portion against the flat wall surface of the groove.

Abstract: A driver assembly with an efficient mechanism for transferring heat away from an integrated circuit (IC) chip via a heat transfer member and conductive pattern lines formed on a substrate. The IC chip is mounted on connectors and is placed above the substrate. The IC chip operatively communicates with the display panel via at least a subset of the conductive pattern lines and a subset of the connectors. A heat transfer member is formed on the substrate and is configured to transfer heat generated by the integrated circuit to a component having a lower temperature than the IC chip. A heat transfer element is placed between the IC chip and the heat transfer member to transfer the heat generated by the IC chip to the heat transfer member.

Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

Abstract: An electrical equipment casing includes a circuit board on which many electrical parts are mounted and a heat sink to which the circuit board is fixed. The heat sink is provided with a reactor housing dent that opens in a surface on which the circuit board is placed and radiator fins that reach a bottom portion of the reactor housing dent on a surface opposite to the surface on which the circuit board is placed at a position surrounding an outer circumference of the reactor housing dent. The reactor is housed in the reactor housing dent and a terminal thereof is electrically connected to the circuit board. This structure of the electrical equipment casing can contribute to an achievement of both of a size reduction of the overall casing and enhanced heat dissipation of the reactor.

Abstract: The invention relates to an electronic chip, comprising: a semiconductor substrate (6) having an active area (8) formed by at least one P doped region and at least one N doped region which form one or more P-N junctions through which most of the useful current flows when said electronic chip is in a conductive state, and at least one channel (44) through which a heat transport coolant can flow, the channel(s) passing through at least said P or N doped region of the active area. Each channel (44) is rectilinear and passes through the substrate (6) in a direction which is collinear with a direction F to the nearest ±45°, where the direction F is perpendicular to the plane of the substrate.

Abstract: A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed.

Abstract: In a stacked semiconductor device, a Peltier element may be incorporated as a distributed element so as to provide active heat transfer from a high power device into a low power device, thereby achieving superior temperature control in stacked device configurations. For example, a CPU and a dynamic RAM device may be provided as a stacked configuration, wherein waste heat of the CPU may be efficiently distributed into the low power memory device.

Abstract: A system and a method of self-cooling a semiconductor package are described. A cell is formed, which contains a thermally conductive and electrically insulative material, sandwiched between a first thermally conductive plate and a second thermally conductive plate. A plurality of integrated circuits are formed by combinatorial processing. The plurality of integrated circuits are interconnected into a semiconductor integrated circuit package. The cell is thermally bonded to the semiconductor integrated circuit package. The first thermally conductive plate is electrically connected to the semiconductor integrated circuit package. A current is supplied to the second thermally conductive plate by an electrical lead from a supply voltage. Power is provided in series to the semiconductor integrated circuit package and through the cell.

Abstract: An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir.

Abstract: A packaged semiconductor device includes a package substrate, a semiconductor die on the package substrate, an encapsulant over the semiconductor die and package substrate, and a heat spreader having a pedestal portion and an outer portion surrounding the pedestal portion. The encapsulant includes an opening within a perimeter of the semiconductor die. The bottom surface of the pedestal portion of the heat spreader faces the top surface of the semiconductor die, wherein a first portion of the opening and at least a portion of the encapsulant is between the bottom surface of the pedestal portion and the semiconductor die.