Abstract: Multichip integrated circuit modules having crossed bonding wires are disclosed together with methods of making the same. The integrated circuit dies of the multi-chip modules are affixed to a suitable die supporting substrate. The dies are then electrically coupled to each other and/or to associated lead traces by wire bonding the dies, with at least two of the bonding wires being crossed. The integrated circuit dies, the bonding wires, and at least a portion of the lead traces are enclosed in a package. In one embodiment, the bonding wires used in the wire bonding step are precoated with an insulating material. In another embodiment, the insulating layers are formed on the bonding wires after the wire bonding step to prevent shorting between the wires. The insulating layers may be formed in a variety of manners. By way of example, the wires can be oxidized, or they may be coated with a protective material.

Abstract: An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure.

Abstract: A method and apparatus for achieving a hermetically sealed ceramic integrated circuit package having good thermal conductivity for efficiently transferring heat from an integrated circuit chip die contained therein. Use of an ultra-thin integrated circuit chip die, thin ceramic housing layers and external lead frame allow an ultra-thin overall package that may be used singularly or further densely packaged into a three dimensional multi-package array and still meet the critical performance and reliability requirements for both military and aerospace applications.

Abstract: An electronic module (10) for removing heat from a semiconductor die (41) and a method of making the electronic module (10). The electronic module (10) has a baseplate (11) mated with an isolation structure (23). The isolation structure (23) has three portions: a first portion is bonded to the top surface (12) of the baseplate (11), a second portion is bonded to the bottom surface (13) of the baseplate (11), and a third portion is bonded to a side (14) of the baseplate (11). A semiconductor die (41) is bonded to the first portion of the isolation structure (23) and another semiconductor die (41) is bonded to the second portion of the isolation structure (23). The baseplate (11) has a cavity (20) through which a fluid flows and transports heat away from each semiconductor die (41).

Abstract: A high-frequency, high-power, semiconductor device chip is impedance matched to an off-chip impedance by a matching network including a dielectric element located on a substrate ground plane portion adjacent to the device to be matched. A thin film dielectric layer is formed over the dielectric element, the semiconductor device and the surrounding substrate. A patterned metal matching circuit is disposed over the dielectric layer and is in electrical contact with an electrode of the high-frequency, high-power, semiconductor device. An impedance matching network is formed by the patterned metal circuit, the dielectric element, the dielectric layer and the underlying grounded substrate. The matching characteristics of the network can be tailored by selecting suitable dielectric materials for the dielectric element and by altering design of the patterned metal circuit.

Abstract: An apparatus for containing and supporting electronic components includes a first housing portion having a first support, and a second housing portion having a second support. The apparatus further includes an elastomeric isolating member being secured between the first support and the second support so as to position the isolating member within the apparatus. Moreover, the apparatus further includes a base upon which electronic components are mounted, the base being attached to the elastomeric isolating member.

Abstract: A plastic-molded-type semiconductor device is provided wherein two semiconductor chips, having main surfaces on which electrodes and circuits are formed, are arranged to face each other. A lead frame is placed between these two semiconductor chips and electrically connected to their electrodes, and a plastic package is formed by plastic-sealing the above components. To provide for secure and convenient electrical connections between the electrodes on the semiconductor chips and the lead frame, wiring patterns are provided on the main surfaces of the semiconductor chips through the intermediation of insulating films. With this structure, it is possible for two large-sized semiconductor chips having electrodes in their middle sections to be encased in a single, relatively thin package.

Abstract: A memory cube comprising a plurality of memory chips, each having a plurality of data storage devices, is provided with an auxiliary chip having inactive line termination circuits and the auxiliary chip or chips are formed as part of the memory cube structure and disposed among the memory chips on an interleave basis. The auxiliary circuit chips are provided with external terminals connected to memory input leads, control leads and data write leads, in close proximity to the termination point of the leads. A decoupling capacitor, integrated in the auxiliary circuit chip, is connected to the power bus in the memory cube structure and eliminates extraneous noise problems occurring with discrete capacitors external to the cube. A heating resistor is provided on the auxiliary circuit chip to maintain the cube structure at a near constant temperature. Temperature sensing diodes are incorporated in the auxiliary chip to provide an accurate mechanism for sensing the temperature internal to the cube.

Abstract: An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure.

Abstract: An electric packaging arrangement for isolated circuits is described. A lead frame is formed with at least one off-centered tie bar connected between one of the circuits on the lead frame's internal lead and an external handling side rail. The tie bar is off-centered by a specified distance from the longitudinal center line of the package. The external side rail is used to support and align the lead frame during manufacturing. To meet safety requirements, such as the UL-1950 requirements, electrical components in a primary circuit and a secondary circuit are attached and electrically coupled to the lead frame in a manner such that the smallest internal distance between internal circuits is at least a predefined distance. The external distance between the tie bar, connected to the secondary circuit, and the closest primary circuit pin is set to meet external circuit component spacing requirements for isolated circuits.

Abstract: A package for housing integrated circuit chips that provides EMF shielding and thermal protection, while conforming to an industry recognized package outline, is provided. This EMF shielding and thermal protection is achieved by providing an electrically conductive heat sink that provides heat dissipation and that, together with a separate electrically conductive layer, also acts as an EMF shield. The heat sink contains a recess and is positioned against the conductive layer with the recess facing the conductive layer. The integrated circuit (IC) resides inside the cavity formed by the heat sink and conductive layer and is protected from EMF by the heat sink and conductive layer. The heat sink, electrically conductive layer and IC are then encapsulated in an electrically insulating molding compound that is molded to an industry recognized package outline. Additional ICs can be housed in this package by attaching them to the side of the electrically conductive layer opposite the heat sink.

Abstract: A semiconductor device includes at least a first semiconductor chip and a second semiconductor chip each having a first surface and a second surface. The second surface of the first semiconductor chip confronts the first surface of the second semiconductor chip. Additionally, the semiconductor device includes a plurality of leads having inner portions and outer portions, where the inner portions of the leads are electrically coupled to selected portions on one of the first and second surfaces of each of the first and second semiconductor chips. An insulator is interposed between the second surface of the first semiconductor chip and the first surface of the second semiconductor chip at portions other than the selected portions. Further, a resin package encapsulates the first and second semiconductor chips so that the outer portions of the leads project outside the resin package.

Abstract: A hybrid semiconductor device which comprises a semiconductor substrate having electrical devices therein with a plurality of spaced apart relatively rigid standoffs of electrically insulating material disposed over the substrate. Each of the standoffs has a substantially planar exposed surface remote from the substrate. A first layer of electrically insulating material more resilient than the standoffs is disposed over the substrate and between the standoffs and has an upper surface coplanar with the planar exposed surfaces of the standoffs. A semiconductor superstrate is secured to the first layer of electrically insulating material, the superstrate containing electrical devices. A connection connects the electrical devices contained in the superstrate to the electrical devices in the substrate.

Abstract: A semiconductor rectifying module has a metal base, a dielectric heat conducting spacer arranged on the metal base and rectifying elements of anode and cathode groups arranged with their cathodes and anodes on the spacer, the rectifying elements being composed of a semiconductor with at least two layers having alternating conductivity types, each of the rectifying elements being surrounded by its side surface by a side layer of a first type conductivity semiconductor material while an original material is a second type conductivity semiconductor material, and being provided with an upper closed separating groove with an external part bordering at least the side layer.

Abstract: A semiconductor device includes lead frames (21) respectively having first main surfaces and second main surfaces opposite to each other, bonding being able to be performed on the first and second main surfaces, a first semiconductor chip (22) arranged on first main surface sides of the lead frames, first tape leads (23) electrically connecting the first main surfaces of the lead frames to the first semiconductor chip, a second semiconductor chip (24) arranged on second main surface sides of the lead frames, and second tape leads (25) electrically connecting the second main surfaces of the lead frames to the second semiconductor.

Abstract: A high density interconnect (HDI) structure having a dielectric multi-layer interconnect structure on a substrate is fabricated by forming a chip well, placing a chip in the well, and connecting the chip to the interconnect structure. Additionally, temperature sensitive chips or devices may be located beneath the dielectric multi-layer interconnect structure. A spacer die may be located in the substrate while the interconnect structure is fabricated and removed after a chip well aligned with the spacer die is formed, in order to accommodate a chip thickness which is greater than the dielectric multi-layer interconnect structure thickness.

Abstract: Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. A PIN diode region 14 of the first conductivity type is then implanted in the substrate 10 at the first surface and spaced from the HBT subcollector region 12. Next, an i-layer 16 is grown over the first surface. Next, an HBT base/PIN diode layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12 and the PIN diode region 14. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base/PIN diode layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base/PIN diode layer 22.

Abstract: A semiconductor element module is adapted to be mounted on a main body by insertion in a predetermined direction.

Abstract: A semiconductor integrated circuit of the laminated type having a large circuit capacity includes an upper silicon tip and a lower silicon tip as essential components and a layer of electrical insulative material is interposed between the upper silicon tip and the lower silicon tip both of which are electrically connected to each other via a number of lead wires extending therebetween. An assembly of the upper silicon tip, the electrical insulative material layer and the lower silicon tip is fixedly mounted on a base board, and the foregoing assembly is then covered with a cap.

Abstract: An improved high-frequency high-power transistor includes a transistor chip and capacitors forming an RF shunting internal matching circuit. The capacitors are connected with RF shunting wires to a collector pad to which the transistor chip is die-bonded. The wires have the same lengths and are disposed symmetrically relative to input and output leads of transistor cells within said transistor chip so that they uniformly influence the transistor cells.

Abstract: An apparatus for containing and supporting electronic components includes a first housing portion having a first support, and a second housing portion having a second support. The apparatus further includes an elastomeric isolating member being secured between the first support and the second support so as to position the isolating member within the apparatus. Moreover, the apparatus further includes a base upon which electronic components are mounted, the base being attached to the elastomeric isolating member.

Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal.

Abstract: A lead frame, used for constructing a multi-core optical module or the like, includes a frame portion, a plurality of substrate portions on which electronic circuit elements are to be mounted, and a support portion for securing the plurality of substrate portions to the frame portion. The support portion has a plurality of separated end portions connected to the respective substrate portions at the position where a molded resin member is covered, and at least two of the plurality of end portions are combined into one body to be connected to the frame portion at the point where the molded resin member is not covered.

Abstract: A cooling member for an integrated circuit, the member having a recess therein for receiving the integrated circuit and contacting a portion of exterior surfaces of the integrated circuit and a portion of metal leads extending from the integrated circuit; in one aspect, such a member with a plurality of such recesses for accommodating a plurality of such integrated circuits; and in one aspect, such a system including a metal heat sink.

Abstract: An electrical apparatus having a first substrate, a first metallic layer, a semiconductor device, a second metallic layer, and a metallic interconnecting structure is described. The first substrate is of a semiconductor material and has an upper region and a lower region. The substrate provides an electrical path between the upper region and the lower region. The first metallic layer is coupled to the lower region of the substrate. The first metallic layer provides a first external electrical connection. The semiconductor device has an upper region and a lower region. The second metallic layer is coupled to the lower region of the semiconductor device. The second metallic layer provides a second external electrical connection. The metallic interconnecting structure electrically couples the upper region of the first substrate to the upper region of the semiconductor device. A bridge apparatus is also described. In addition, a method of fabricating an electrical apparatus is described.

Abstract: A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip having high aspect ratio metallized trenches therein extending from a first surface to a second surface thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate. Next the integrated circuit device is affixed to a carrier such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches. Specific details of the fabrication method and the resultant multichip package are set forth.