Abstract: A semiconductor device that be able to be manufactured in same equipment dose not depend on a number of semiconductor chips which are mounted on the semiconductor device.The semiconductor device can be prepared by a method comprising a step of mounting a semiconductor chip 2 having a first electrode and a second electrode on both sides on a common substrate 20 having N chip areas 8 having a first wiring area 9a and a second wiring area 9a insulated from the first wiring area 9a and separating areas 7 separating adjacent chip areas 8, a step of connecting the first wiring area 9a and first electrode, a step of mounting semiconductor chips 2 on the chip mounting areas 8 of the common substrate 9, a step of connecting the second wiring area 9b and the second electrode of semiconductor chip 2 electrically, and a step of removing extra area 8b which is chip area 8 having no semiconductor chip 2.

Abstract: An enclosure is formed on a substrate of a semiconductor device surrounding a bonding pad, such that a groove is formed between the enclosure and the bonding pad. An insulating film is formed over the substrate, including the enclosure and the groove. The groove and the film prevent moisture and contaminants from seeping into the semiconductor device.

Abstract: A power MOSFET die and a logic and protection circuit die are mounted on a common lead frame pad, such as a TO220 lead frame pad. The logic and protection circuit die includes a MOSFET that is connected in parallel with the power MOSFET but which is smaller than the power MOSFET and which dissipates power at a predetermined fraction of that of the power MOSFET. The logic and protection circuit die also includes a temperature sensor that is in close proximity to the MOSFET and determines the temperature of the MOSFET. The die also includes another temperature sensor that is located distant from the MOSFET to determine the temperature of the lead frame. The temperature of the power MOSFET can be determined from the temperature measured by these two sensors and from the ratio of the power dissipated by the two MOSFETs.

Abstract: A polymer stud grid array for microwave circuits is proposed which includes an injection-molded, three-dimensional substrate that is fabricated from an electrically insulating polymer. The substrate includes a plurality of polymer studs which are arranged over the underside of the substrate and which are integrally formed with the substrate during the injection-molding process. Signal connections are formed on the studs which include an end surface that is capable of being soldered. Potential connections are formed on at least one of the studs. The potential connection also includes an end surface that is capable of being soldered. Striplines are also constructed which connect the studs to the microwave circuit. Each stripline includes a first structured metal layer disposed on the underside of the substrate, a dielectric layer disposed on the first metal layer and a second structured metal layer disposed on top of the dielectric layer.

Abstract: A method of making a stacked microelectronic assembly such as a semiconductor chip assembly and its resulting structure includes providing a flexible substrate having a plurality of attachment sites and conductive terminals and including a wiring layer with leads extending to the attachment sites. The method includes assembling a plurality of microelectronic elements to the attachment sites and electrically interconnecting the microelectronic elements and the leads so that the electrically connected microelectronic elements are movable relative to the flexible substrate. The flexible substrate is then folded so as to stack at least some of the microelectronic elements in substantially vertical alignment with one another to provide a stacked assembly with the conductive terminals exposed at the bottom end of the stack. The stacked assembly is held in place using a thermally conductive adhesive and/or a mechanical element.

Abstract: A semiconductor device comprises a signal pin mounted on a base plate by adhesive. Parasitic capacitance exists between the pin and the base plate in the region of adhesive and may deleteriously affect the operation of circuitry in chip connected to pin by a bond wire. A bond wire connecting pin to the base plate has an inductance which forms a parallel resonant circuit with the parasitic capacitance, so that, at the resonant frequency, signals on pin at substantially the same frequency pass to or from the chip substantially unattenuated by the parasitic capacitance. Alternatively, the inductances of the signal pin and the bond wires may be such that, at the frequency of signals on the signal pin, an impedance transformation is provided between the input to the signal pin and the end of the first bond wire where it connects to the chip.

Abstract: A semiconductor device, such as an integrated circuit die, includes a plurality of bond pads on an active surface thereof electrically connected to internal circuitry of the semiconductor device, and a plurality of jumper pads on the active surface which are electrically isolated from internal circuitry of the die. The jumper pads effectively provide stepping stones for wire bonds to be made across the active surface between bond pads. The jumper pads may be formed directly on the semiconductor device or on a non-conductive support structure that is attached to the semiconductor device.

Abstract: Apparatus, and an associated method, shields separate component portions of an electronic device housed at a housing from electromagnetic interference generated during operation of the electronic device. Assembly of the apparatus which shields such component portions from one another is effectuated by lowering the component portions in a single in-line direction thereby to facilitate automated assembly.

Abstract: A pin-less retainer for mounting a press-pack device, which includes circumscribing fins for preventing arc formation between terminal faces thereof, onto the rods of a clamping mechanism used to stack a plurality of such devices and heat sinks together. The retainer is constructed out of a semi-flexible sheet having two mirrored sections, each section having a void therein and at least two extending tabs. The voids are sized such that the retainer may be press-fitted into interstices between the fins, and the tabs are shaped and sized to suspend the press-pack device from the rods and axially align the press-pack device with other elements of the stack. The retainer, being a pin-less mount, facilitates the easy and rapid removal of a press-pack device from a stack without having to completely disassemble it.

Abstract: A pressure assembled power module is provided with first and second die, the first and second die being stacked atop one another and sandwiched between first and second conductive sheets, where the die are separated by a relatively flat central conductive lead. Integral to the central conductive lead are spring elements which bias the die against both the conductive sheets and the central conductive lead. Consequently, electrical and thermal interconnections are achieved between semiconductor devices and between the semiconductor devices and a heat sink or substrate.

Abstract: Electrically conductive lamina are attached by an electrically insulating, thermally conductive adhesive and/or solder to one or more semiconductor devices such as chips and extend beyond the periphery of the chip or chips to form heat sink fins. Electrical connections may be made between such chips through holes (e.g. by a wire or plated through hole) in the electrically conductive lamina lined with an insulating material such as the electrically insulating adhesive to provide a structurally robust assembly. Surface pads and connections may overlie patterns of insulator on the lamina. A further lamina can be wrapped around lateral sides of the assembly to provide further heat sink area and mechanical protection for other heat sink fins. A graphite/carbon fiber composite matrix material is preferred for the lamina and the coefficient of thermal expansion of such materials may be matched to that of the semiconductor material attached thereto.

Abstract: A system and method for forming semiconductor devices on more than one surface of a chip is disclosed. A bed is formed with separate portions which connect to a first circuit on a first semiconductor face of a semiconductor chip. A second circuit resides on the opposite face of the semiconductor chip. Providing two circuits on separate faces of a semiconductor chip allows for savings of physical area of the chip. By providing a face-to-face contact with a first circuit, heat generated by the first circuit may be drawn away by the bed. Accordingly, smaller semiconductor chips may be realized without excessive heat generation.

Abstract: A heterojunction bipolar transistor has a mesa including collector 604, base 603, and emitter 602 layers. The mesa has first and second sidewalls 606. An improved heat dissipation structure comprises a layer of electrically insulative and thermally conductive material 607 disposed on one of the sidewalls. A thermal path metal 600 is electrically connected to the emitter 602 and is disposed on the layer of electrically insulative and thermally conductive material 607. The thermal path metal 600 extends from the emitter 602 to the substrate 608 providing for efficient dissipation of heat that is generated by the HBT device.

Abstract: An apparatus and method for evenly applying an atomized adhesive for bonding a die to a leadframe are disclosed. In one embodiment, the apparatus includes a hood in communication with an air supply and a vacuum plenum that encompass a semiconductor device component located in a target area during adhesive application so that the adhesive is selectively applied to specific portions of the leadframe or other semiconductor device component and adhesive is not allowed outside the system. A mask or stencil may be employed for further prevention of adhesive application to undesired areas. An air purge may be employed to direct the adhesive mist toward the component to be coated. In another embodiment, a fine adhesive spray is directed against the surface of the workpiece to be coated, selected areas being masked to prevent coating. Wafers may be coated as well as leadframes.

Abstract: An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provides controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to create multiple vertically stacked isolated devices. Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation modes.

Abstract: An electronic device includes one or more GaAs integrated circuits having a plurality of mutually independent field-effect transistors formed on a GaAs base-member; and one or more high-dielectric-constant base-members including a passive element on a surface thereof or therein.

Abstract: A lead frame 24 comprising an inner lead 22 and outer lead 23 is sealingly filled from a through-hole into a package 21. A CCD chip 27 is inserted from an inlet 26 into the package 21. An electrode pad 28 is connected to the inner lead 22 via a bump 29 to complete an optical positioning and an electrical connection, then the positions of these components are fixed by glue. As a result, a solid-state image sensing apparatus can be manufactured at a low cost, and an accurate positioning can be realized. Thus, the solid-state image sensing apparatus can be employed to a video camera of high quality picture to reproduce vivid colors and fine pictures.

Abstract: A circuit module includes at least one high temperature semiconductor chip having chip pads; a substrate having substrate metallization, the chip pads and the substrate metallization being substantially planar; and a deposited flexible pattern of electrical conductors capable of withstanding high temperatures and coupling selected chip pads and portions of the substrate metallization. The deposited flexible pattern of electrical conductors includes a plurality of integral interconnect segments, at least one of the integral interconnect segments including first and second leg portions and a shelf portion with the shelf portion being spaced apart from the at least one semiconductor chip and substrate and being coupled by the first leg portion to a selected chip pad and by the second leg portion to one of another selected chip pad or a selected portion of the substrate metallization.

Abstract: On a surface of a semiconductor substrate within a device forming region, a MOS transistor including a gate electrode, gate oxide film and source.cndot.drain is formed. An insulating layer is formed on the surface of the semiconductor substrate. In an opening of the insulating layer above the source.cndot.drain, a tungsten plug is formed. At a dicing line portion, the insulating layer has a trench portion. The trench portion is formed to surround the device forming region. A tungsten street having a top surface continuous to the top surface of the insulating layer is formed in the trench. By this semiconductor device, short-circuit between bonding pads and the like can be prevented, and the reliability can be improved.

Abstract: An inverter device includes plural modules, each module being formed by a series circuit having a parallel circuit of a switching device and a first diode, and a parallel circuit of a second switching device and a second diode, allowing a reduced size, high reliability, high frequency switching and low noise. Each of the semiconductor modules includes a plurality of switching device chips and at least one diode chip formed on a metal substrate. Electrode plates are provided in locations of the module adjacent to the switching device chips and the diode chips to facilitate connection of the electrodes of the respective chips to one another and to the outside of the module.

Abstract: The present invention provides a printed wiring board on which a bear chip is bonded in face-down. The printed wiring board has wiring patterns extending over the printed wiring board, wherein a plurality of wirings are provided which extend radially and outwardly from a center area of the printed wiring board, and wherein each of the wirings comprises at least a bear chip mounting pad region for contacting bumps of the bear chip, at least an external wiring pad region for connecting to an external wiring, and at least a covered region being covered by at least an insulation layer and the covered region separating between the bear chip mounting pad region and the external wiring pad region and a sealing material is filled within a space defined between the printed wiring board and the bear chip.

Abstract: An electronic module includes multiple stacked bare IC chips ("a stack") and a sensor assembly that is mechanically coupled to an end surface of the stack. Electrical connection between the sensor assembly and the stack is provided by a metallization layer disposed on a side-surface of the stack. Specifically, wiring of the sensor assembly extends to an edge surface thereof corresponding to the side-surface of the stack where it electrically connects to the side-surface wiring. The IC chips of the stack are similarly electrically connected to the side-surface wiring. Multiple sensors (e.g., CCD arrays) may be electrically and mechanically coupled to multiple surfaces of the stack for providing a, e.g., multi-view imaging module. Multiple electrical and mechanical options exist for the connection of sensors to stacks within electronic modules.

Abstract: The invention relates to a printed circuit board having chips attached to the PCB. One or more of the chips has a planar collar mounted around the chip. The collar has a top and bottom planar surface without any projections. The collar extends laterally away from the edge of the chip to protect the leads electrically connecting the chip to the circuit board.

Abstract: An electronic product with a standby power source includes a main power circuit for receiving a commercial AC through a power switch and generating a main power source by full-wave rectifying the AC through a diode bridge, and a standby power circuit for receiving the AC and generating the standby power source by full-wave rectifying the AC through another diode bridge, the standby power circuit and the main power circuit being formed on one printed circuit board, and the standby power circuit having an additional ground pattern isolated from a ground pattern of the main power circuit.

Abstract: A semiconductor device comprises at least two semiconductor elements connected together at a connecting region of the semiconductor elements. At least one joint chip is adhered to the connection region of the semiconductor elements for connecting the semiconductor elements together. The joint chip has a trapezoidal cross-section defining a first surface and a second surface wider than the first surface. The second surface of the joint chip is adhered to the connection region of the semiconductor elements.

Abstract: A microwave circuit package includes a metallic base plate on which are mounted a plurality of monolithic microwave integrated circuits (MMICs) and a spacer, made of a dielectric material, separating the MMICs from each other, and the MMICs and spacer are sealed in the package. The provision of the spacer substantially reduces the volume of the interior space of the package. A dielectric substrate having generally the same height as substrates of the MMICs may also be mounted on the metallic base plate, and a strip conductor may be provided on the dielectric substrate so as to form a microstrip line thereon.

Abstract: A method and device for interconnecting stacked semiconducting plates, in which each of the plates has an integrated circuit. The semiconducting plates (P) are stacked and made solid with each other. In one embodiment, their connecting contacts are connected by a wire (F) to any one of the faces of the stack except one (B), which is to be in contact with a printed circuit. Connections of the plates together and with the printed circuit is made on the faces (F.sub.V, F.sub.S, F.sub.L) of the stack.

Abstract: In a high-power semiconductor module (10), in which a plurality of first submodules (13, 14, 16, 17) are arranged in an electrically insulated manner in a common housing (12) and on a common cold plate (11) and are interconnected with one another, the first submodules (13, 14, 16, 17) each ?lacuna! individual controllable power semiconductor switches (13a), short-circuit-proof operation in conjunction with relatively high switching frequencies is made possible, with a relatively low current-carrying capacity and an increased withstand voltage, by virtue of the fact that the first submodules (13, 14, 16, 17) are connected in series within the module for the purpose of increasing the withstand voltage.

Abstract: A hermetically sealed ceramic integrated circuit package and method for achieving same, the package including an internal lead frame attached to an integrated circuit die in a lead-on-chip configuration, an external lead frame attached to the package exterior in a lead-on-package configuration and a high temperature adhesive layer which attaches the internal lead frame to the integrated circuit die.

Abstract: A stacked chip package comprising an upper part including an upper semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; an upper lead frame having leads extending over the active surface of the upper semiconductor chip and which are electrically interconnected to the electrode bonding pads of the semiconductor chip; a lower part including a lower semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; a lower lead frame having inner leads extending over the active surface of the lower semiconductor chip which are electrically interconnected to the electrode bonding pads of the lower semiconductor chip, and outer leads for electrical interconnecting the stacked chip package to an external circuit device.

Abstract: An electrical apparatus having a first substrate, a first metallic layer, a semiconductor device, a second metallic layer, and a metallic interconnecting structure is described. The first substrate is of a semiconductor material and has an upper region and a lower region. The substrate provides an electrical path between the upper region and the lower region. The first metallic layer is coupled to the lower region of the substrate. The first metallic layer provides a first external electrical connection. The semiconductor device has an upper region and a lower region. The second metallic layer is coupled to the lower region of the semiconductor device. The second metallic layer provides a second external electrical connection. The metallic interconnecting structure electrically couples the upper region of the first substrate to the upper region of the semiconductor device. A bridge apparatus is also described. In addition, a method of fabricating an electrical apparatus is described.

Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Abstract: A semiconductor module includes a ceramic substrate for mounting plural semiconductor chips. Even if cracks and cleavages are formed in the ceramic substrate, further damages, such as lowering dielectric or insulation strength is prevented. The semiconductor module includes IGBTs arranged on one ceramic substrate soldered to a metal base plate, and the upper surface of the ceramic substrate is divided into zones. On each zone, a copper foil with one IGBT is mounted. A snap line is formed between the zones to localize the cracks and cleavages formed by bending stress to the snap line. The copper foils on the zones are connected to each other by a conductor bridge disposed over the snap line.

Abstract: A semiconductor device is disclosed which employs transfer molding to simplify a resin sealing step, reduces fabrication costs without using expensive elements, and has an improved efficiency of dissipation of heat generated by a power device and an improved product rating. The power device (101) and a control device (102) are placed in predetermined positions on horizontally positioned lead frames (103a, 103b), respectively. An insulating layer (105) of epoxy resin or the like is formed on a major surface of a heat sink (104), and a circuit pattern layer (106) formed on a major surface of the insulating layer (105) is shaped to conform to a predetermined circuit pattern. The lead frames (103a, 103b) are disposed on the circuit pattern layer (106).

Abstract: An electronic module includes multiple stacked bare IC chips ("a stack") and a sensor assembly that is mechanically coupled to an end surface of the stack. Electrical connection between the sensor assembly and the stack is provided by a metallization layer disposed on a side-surface of the stack. Specifically, wiring of the sensor assembly extends to an edge surface thereof corresponding to the side-surface of the stack where it electrically connects to the side-surface wiring. The IC chips of the stack are similarly electrically connected to the side-surface wiring. Multiple sensors (e.g., CCD arrays) may be electrically and mechanically coupled to multiple surfaces of the stack for providing a, e.g., multi-view imaging module. Multiple electrical and mechanical options exist for the connection of sensors to stacks within electronic modules.

Abstract: A protective cap is deposited over the top and sides of an air bridge structure located on an integrated circuit chip. The protective cap provides mechanical strength during the application of a high density interconnect structure over the chips, to prevent deformation of the sensitive (air bridge) structure, and also to prevent any contamination from intruding under the air bridge. More importantly, the protective cap does not impede the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure. Furthermore, the protective cap allows additional area for metallization to provide alternate circuits for coupling, power or ground planes, etc.

Abstract: A microwave/millimeter wave circuit structure supports discrete circuit elements by flip-chip mounting to an interconnection network on a low cost non-ceramic and non-semiconductor dielectric substrate, preferably Duroid. The necessary precise alignment of the circuit elements with contact pads on the substrate network required for the high operating frequencies is facilitated by oxidizing the interconnection network, but providing the contact pads from a non-oxidizable material to establish a preferential solder bump wetting for the pads. Alternately, the contact bumps on the flip-chips can be precisely positioned through corresponding openings in a passivation layer over the interconnection network. For thin circuit substrates that are too soft for successful flip-chip mounting, stiffening substrates are laminated to the circuit substrates.

Abstract: In a power semiconductor module (10), in which a plurality of individual controllable power semiconductors in the form of semiconductor chips (13, 15, 16) are arranged alongside one another and electrically connected on a common module substrate (11), electrical connection to the surroundings with an appreciable reduction in the required surface area of the module or substrate is achieved by virtue of the fact that the control connections (23-25) of a plurality of the controllable power semiconductors are brought together on a second plane which is vertically offset with respect to the plane of the module substrate (11).

Abstract: A method in which several high voltage chips may be packaged within a single, typically low voltage plastic package. The high voltage chips are packaged to remain electrically isolated from each other to avoid undesirable side effects such as arcing between the chips but able to share electronic data and communicate with each other electronically through their input and ouput nodes. Due to the unique packaging method, the typically low voltage plastic packaging can be made to withstand operating voltages up to 35 times greater than previously attained by such low voltage plastic packaging.

Abstract: A package for relatively high power transistors including heat conducting mounting flange having a relatively large "footprint" relative to the area covered by at least one active chip supported thereby and comprised of a plurality of bipolar silicon-carbide transistors. The transistors are located on a dielectric substrate brazed to the flange. A plurality of screw mounting holes, preferably eight in number, are included in the mounting flange adjacent the outer edge of the dielectric substrate so as to surround the chip. Mounting screws in the eight mounting holes together with a relatively large flange/ground plane interface significantly improves heat dissipation for the heat generated by the silicon carbide transistors by promoting radial heat spreading through the heat conductive metal flange.

Abstract: A bus pattern for an integrated circuit package. The package has a first conductive bus and a second conductive bus that are located on a bond shelf. The first conductive bus has a plurality of interconnected tab portions that are separated by a plurality of non-conductive slots. The second conductive bus has a plurality of interconnected tab portions that are located within the non-conductive slots of the first bus. The tab portions of each bus are wire bonded to a plurality of die pads located on an integrated circuit that is mounted to the package.

Abstract: A multi-chip module including a multi-layer substrate and a patterned metallization layer formed on each layer of the substrate. A multi-tiered cavity is formed with an integrated circuit (IC) mounting surface at the bottom of the multi-tiered cavity. A plurality of ICs are mounted on the IC mounting surface of the cavity. A first set of wire bonds extends from at least one IC to the exposed portions of patterned metallization of at least two tiers of the multi-tiered cavity. A second set of wire bonds extends from the at least one IC to bond pads of an adjacent IC. A third set of wire bonds extends from the at least one IC to bond pads of the adjacent IC such that the third set of wire bonds has a higher loop height than the second set of wire bonds.

Abstract: In a semiconductor device comprising a semiconductor chip on which semiconductor elements are formed, the semiconductor device further comprises a thermal resistance detector for detecting an increase of thermal resistance of a heat radiating path which is provided to radiate the heat generated in the semiconductor device during operation, and a thermal resistance detection result output circuit for outputting a result of a detection by the thermal resistance detector to an output of the semiconductor device. The semiconductor device can detect at the early stage the increase of the thermal resistance of the heat radiating path, and the deterioration of the semiconductor device due to the crack in the solder layer bonding the chip mounting insulation substrate and heat sink during the operation of the device.

Abstract: A highly dense electronic module for installation into a computer or other electronic device comprises at least one wafer or wafer section and means for connection with the electronic device. With an embodiment comprising plural wafer sections, the wafer sections are mechanically joined and electrically coupled.

Abstract: A method of manufacturing a semiconductor device having a stud and interconnect in a dual damascene structure uses selective deposition. The method includes forming a trench including a first opening portion and a second opening portion in a dielectric layer, forming a first adhesion layer on a surface exposed by the first opening portion, forming a second adhesion layer on a surface exposed by the second opening portion, and selectively depositing a conductive material on the first adhesion layer and the second adhesion layer, wherein growth of the conductive material on the second adhesion layer starts after growth of the conductive material on the first adhesion layer has started. The first and second adhesion layers are of different materials.

Abstract: It is an object of the present invention to obtain a power semiconductor device with small size and high reliability in power semiconductor devices having integral structure of case and external connection terminals. A dummy pad (42) having no electric connection with other parts is provided and a terminal end of a connecting wire (46) connecting by sequentially bonding an exposed surface of a connection electrode (43) and a bonding pad (41) of a semiconductor element (40) is bonded thereto. The semiconductor device can be miniaturized without deteriorating electric characteristics and reliability of the semiconductor elements.

Abstract: A stacked semiconductor multi-package including a plurality of individual semiconductor chip packages stacked over one another. The individual packages have a substrate provided with a plurality of bonding pads, electrode pads electrically connected to the bonding pads through wires, and chips attached to upper and lower surfaces of the substrate. A paddles lead frame is provided onto which the individual packages are attached to upper and lower surfaces thereof, and variants thereof. For these packages, since individual packages are mounted on upper and lower surfaces of a single printed circuit board or lead frame, the mounting density can be significantly increased and their production can be simplified.

Abstract: An input-output wiring for the power circuit and a ground layer are formed on a metal substrate of a power hybrid integrated circuit apparatus. A plurality of windows are opened at predetermined positions of a circuit substrate to which electronic parts such as an IC driver, a chip resistor etc. are connected. Ceramic chips are soldered on the exposed surface of the metal substrate in the windows, and the power semiconductor elements are connected through metal bridges on the ceramic chips. Connection between lower electrode of adjoining power semiconductor elements or between lower part of the power semiconductor element and an input/output wiring is made by means of a part of the metal bridge.

Abstract: In order to maintain parasitic inductances of main electrodes at low levels also during operation of a semiconductor device, upright portions of main electrode plates serving as paths of main currents are sealed in a side wall portion of a resin case, whereby the main electrode plates are fixed to the case while being maintained in parallel with each other. Further, lower end portions are opposed in parallel with each other through a flat insulating spacer. Thus, parasitic inductances caused in the main electrode plates are suppressed. Further, the lower end portions are not fixed to a circuit board but electrically connected to a power transistor through wires. Therefore, no deformation of the main electrodes is brought by thermal deformation of the circuit board following heat generation of the transistor, whereby the parallelism of the main electrode plates is maintained also during the operation of the device.

Abstract: A multi-chip packaging arrangement that contemplates stacking discrete components over film based components is disclosed. The multi-chip package includes a substrate having one or more film based components formed thereon. A discrete component is mounted on the substrate over the film based component such that it is electrically isolated from the film based component. One or more die components are also mounted on the substrate and a plurality of leads are provided for electrically connecting the multi-chip package to external circuitry. Wiring traces formed on the substrate are provided to electrically connect various ones of the components and the leads. A packaging material is provided to encapsulate the components and the wiring traces and leaves a portion of the leads exposed to facilitate electrically connecting the multi-chip package to external circuitry. Methods of making such multi-chip packages are also disclosed.