Abstract: A heat sink dissipater includes a retaining device and a heat dissipater. A plurality of fins and a plurality of pads or recesses are integrally formed on the top surface of the heat dissipater. A plurality of resilient legs extend inward from the sides of the retaining device. Retaining edges are also formed on two sides of the retaining device. The resilient legs fall into the gaps between the fins when the retaining device is positioned on the heat dissipater to secure a CPU assembly. In an orientation, the legs are placed on the pads or recesses of the heat dissipater and in an orthogonal orientation, the legs are placed directly on the top surface of the heat dissipater. Therefore, CPU assemblies of different thickness can be accommodated by rotating the retaining device or the heat dissipater 90 degrees.

Abstract: Apparatus and methods for manufacturing low-resistant substrate contacts in integrated circuits are disclosed. The contacts are low resistive conducting plugs and are located outside the areas of active components. The substrate is connected from the top portion in order to obtain a low resistance. Multiple metal plugs electrically interconnect the substrate of the integrated circuit with the top portion of the integrated circuit.

Abstract: A system and method for maintaining desired circuit component attributes is shown. According to a preferred embodiment, a high frequency circuit component, such as a MMIC, is retained in a circuit using a degradeable material, such as silver filled epoxy, wherein a portion of the degradeable material remains exposed. A protective coating of resin is applied to the exposed portion of the degradeable material by preferably depositing a predetermined amount of protective material, such as an epoxy resin, a void near the exposed portion of the degradeable material. The protective material preferably migrates to fully cover the exposed portion of the degradeable material without covering the circuit component. Accordingly, the circuit component is protected from substantial changes in operation characteristics due to the protective material and likewise is protected from changes in operation characteristics due to degradation of the degradeable material resulting from exposure.

Abstract: To provide a semiconductor device with a three-dimensional mounting module using a flexible circuit substrate which is easy to assemble a three-dimensional structure and is excellent in the workability in repair work (or re-work). [MEANS FOR SOLUTION] A flexible circuit substrate 11 has mounting regions 111, 112 and 113 on which electronic components 121, 122 and 123 are mainly mounted, respectively, and other electronic components 124 and 125 are also mounted. The flexible circuit substrate 11 is structured in such a manner that the mounting regions 111˜113 are folded on top of the other over the base region 110 in a predetermined order (f1˜f3). An integrated spacer 13 has thick regions 131 and thin regions 132, and is superposed and affixed to the flexible circuit substrate 11 as indicated by arrows with broken lines, and supports the electronic components 121˜125 stacked in layers.

Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to depositing a plurality of blocks onto a substrate and is coupled to a flexible layer having interconnect deposited thereon. Another embodiment of the invention relates to forming a display along a length of a flexible layer wherein a slurry containing a plurality of elements with circuit elements thereon washes over the flexible layer and slides into recessed regions or holes found in the flexible layer. Interconnect is then deposited thereon. In another embodiment, interconnect is placed on the flexible layer followed by a slurry containing a plurality of elements.

Abstract: The present invention relates to a capsule (1) for at least one high power transistor chip (17) for high frequencies, comprising an electrically and thermally conductive flange (10), at least two electrically insulating substrates (15), and at least two electrical connections (16), and a cover member, where the high power transistor chip (17) is arranged on the flange (10). The high power transistor chip (17) and the electrically insulating substrates (15) are arranged on the flange (10). The electrical connections (16) are arranged on electrically insulating substrates (15) and the electrically insulating substrates (15) are connected to the flange (10) and open and separate from the high power transistor chip (17).

Abstract: An electrode wiring structure is disclosed which realizes a smaller semiconductor apparatus as a power semiconductor module with the current path set as shortest as possible. The semiconductor apparatus includes: a plurality of semiconductor devices mounted in one array or more on a substrate; a main current electrode mounted along the array(s) of the semiconductor devices, and commonly connected to each of the plurality of semiconductor devices through the substrate by being connected to the substrate through a plurality of wires; an insulated base mounted on the main current electrode, and covering the connection area of the wires connecting the main current electrode; and a drive electrode mounted on the base, and commonly connected to each of the semiconductor devices.

Abstract: Control electrode wirings which are led out from control electrodes over a number of chips built in a flat package and insulating members which are provided in order to insulate the control electrode wirings from main electrode wirings are also given function of positioning of the respective semiconductor chips in the flat package. Further, a one-piece control electrode wiring net is housed in the common electrodes of the package and the electrodes which are led out from the control electrodes of the respective semiconductor chips are connected to the net to simplify the processing of a large number of gate signal wirings.

Abstract: A plurality of MOS transistors are arranged on the top surface of a conductor substrate which is a drain electrode. The drain contact of each MOS transistor is connected to the conductor substrate. The source contact of each MOS transistor is connected to the output conductor path which is a source electrode through a bonding wire. The gate contact of each MOS transistor is connected to a drive signal conductor path which is a gate electrode through a bonding wire. The source contacts of the MOS transistors are interconnected through a bridge electrode and a bonding wire.

Abstract: A method of manufacturing a small, thin card-type storage device is capable of easily manufacturing a frame for the storage device from a variety of resin materials without molding a very thin recessed bottom of the supporter. The method prepares a card-type support frame member from resin and a sheet material, cuts the sheet material into the size of the support frame member, to form a support sheet, bonds the support sheet to a bottom surface of the support frame member, to form a frame, and fits a memory module to be fixed in an opening of the support frame member in the frame, thereby completing the card-type storage device.

Abstract: A semiconductor integrated circuit disclosed herein are characterized in that: (a) each chip is reduced in size by having electrode pads formed in a plurality of rows, the small-size chip being used to form a small ordinary package; (b) frame wires inside the package are used to interconnect electrode pads and electrode bumps in different manners so that chips are furnished in common, whereby a small-size mirror package is formed; (c) frame wires on one side are arranged to pass alternately between contiguous electrode pads and/or between contiguous frame wires on the other side in order to further reduce common chips in size, whereby electrode pads are formed in a larger number of rows; (d) a substrate is sandwiched by the CSPs thus obtained so as to at least double packaging density; and (e) switches or fuses are provided in layered connection wires inside the chip so that after package fabrication, the manner of interconnecting the internal circuits of the chip and the electrode pads thereof may be changed

Abstract: A multichip semiconductor package, and method of making is provided that has a plurality of semiconductor chips fabricated in electrical isolation one from another integrally on a singular coextensive substrate useful for numerous and varied semiconductor chip applications. The semiconductor chips, instead of being singulated into a plurality of single-chip packages, are kept as integrally formed together and are thereafter electrically connected together so as to form a larger circuit. Encapsulated follows so as to form a single, multichip package. Common signals of the plurality of semiconductor chips are bussed together in electrical common across the substrate to a common electrode suitable for electrically providing the signal to another, external circuit, such as a PWB. The common bussing is achieved by conductive leads disposed across the substrate in pair sets having an extended portion that accommodates the common electrode in contact therewith.

Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench.

Abstract: The present invention provides a standard cell which can reduce an effective cell size and improve an integration degree of a semiconductor integrated circuit. The standard cell includes a plurality of MOS transistors formed on a semiconductor substrate. Then, a plurality of standard cells are adjacent to each other in upper, lower, left and right directions, and constitute the semiconductor integrated circuit. The present invention is intended to reduce the effective cell size in such a way that a source region of a MOS transistor connected to a power supply voltage or a ground voltage is shared between cells adjacent to each other. Also, even if the source region is not shared, a source region of one cell in the cells adjacent to each other is arranged in an empty space region of the other cell in such a way that it bestrides between the cells adjacent to each other.

Abstract: A chip mounting assembly includes a dielectric substrate having at least one integrated circuit (I/C) chip mounted thereon. An electrically conductive cover plate is in contact with all the chips with an electrically non-conducting thermally conducting adhesive. A stiffener member is provided which is mounted on the substrate and laterally spaced from the integrated circuit chip. At least one electrically conductive ground pad is formed on the substrate. The stiffener has at least one through opening therein and electrically conductive adhesive extending through each opening and contacting the cover plate and each ground pad.

Abstract: An encapsulant molding technique used in chip-on-board encapsulation wherein an oxidizable metal layer is patterned on a substrate and the oxidizable metal layer is oxidized to facilitate removal of unwanted encapsulant material. The oxidizable metal layer which adheres to the substrate is applied over a specific portion of the substrate. The oxidizable metal layer is oxidized to form a metal oxide layer which does not adhere to encapsulant materials.

Abstract: A semiconductor configuration includes at least one semiconductor chip having a first chip side, a second chip side, and connections passing through the at least one semiconductor chip, active structures on the first chip side and the second chip side, the connections electrically connecting the active structures to one another, a support having a first support side, a second support side, plated-through holes, and non-conducting regions running alternately with regular spacings from the first support side to the second support side, the plated-through holes spaced apart from one another to define a hole spacing distance between the holes, contact connections connecting the second chip side to the first support side, the contact connections spaced apart from one another to define a connection spacing distance between the contact connections, and the hole spacing distance being smaller than the connection spacing distance.

Abstract: The invention provides a method for permanently physically and electrically attaching the electrically conductive contacts of a first component in a RFID device, such as a smart card or smart inlay, to the electrically conductive contacts of a second component of the device. Attachment is made between the first and second components of the device by co-depositing metal and electrically conductive hard particles upon the conductive contacts of either the first or second components and using a non-conductive adhesive to provide permanent bond between the components and their conductive contacts. Components of an RFID device may include, for example, a memory chip, a microprocessor chip, a transceiver, or other discrete or integrated circuit device, a chip carrier, a chip module, and a conductive area, e.g., an antenna.

Abstract: A package is provided for surface mounting a semiconductor device to a board such that a first pad of the semiconductor device is operatively connected to a second pad on the board. The package includes a paddle having a front side and a back side with the front side being mated to the semiconductor device and at least partially enclosed in an encapsulant material and the backside being substantially exposed. In addition, the package has a region of the paddle that is at least partially isolated by the encapsulant material and aligned with the second pad an interconnect connected to the first pad of the semiconductor device and bonded to the region such that a conductive path is formed with the first pad, the region and the second pad when the backside is mated with the board.

Abstract: Providing a semiconductor module comprising a plurality of semiconductor elements, in which wiring lengths of the semiconductor elements juxtaposed to each other are approximately the same. A semiconductor module comprising a lower layer substrate and an upper layer substrate, in which a first and a second electrode pads formed in a front surface of the lower layer substrate are connected with a first and a second wires by a first and a second bridge wires disposed in a back surface of the upper layer substrate.

Abstract: In a multilayer logic device or processor device with a plurality of individually matrix-addressable stacked thin layers of an active material, the active material in each layer is provided between a first electrode set and a second electrode set wherein the electrodes in the first set realize the columns and the electrodes in the second set the rows in an orthogonal array. The intersections between the electrodes in the array define logic cells in the layer of active material, and the stacked layers of active material are provided on a common supporting substrate. A separation layer with determined electrical or thermal properties is provided between each layer of active material.

Abstract: A microwave-frequency microcircuit assembly includes an integrated circuit structure having a circuit ground. A support structure includes a grounded metallic carrier, and a dielectric substrate having a top surface, a bottom surface contacting the carrier, and a capacitor via extending through the dielectric substrate. A metallization on the top surface of the substrate includes an input metallization trace to the integrated circuit structure, an output metallization trace from the integrated circuit structure, and a substrate ground plane upon which the integrated circuit structure is affixed. A thin-film capacitor resides in the capacitor via and is electrically connected between the substrate ground plane and the carrier. An electrical resistor is connected between the circuit ground of the integrated circuit structure and the carrier to self-bias the integrated circuit structure.

Abstract: Apparatus and methods of packaging and testing die. In one embodiment, a stacked die package includes a packaging substrate having a first surface with a recess disposed therein and a plurality of conductive leads coupled thereto, a first die attached to the packaging substrate within the recess and having a plurality of first bond pads electrically coupled to at least some of the conductive leads, and a second die attached to the first die and having a plurality of second bond pads that are electrically coupled to at least some of the conductive leads. When the stacked die package is engaged with, for example, a circuit board, the first surface of the packaging substrate is proximate the circuit board so that the packaging substrate at least partially encloses and protects the first and second die. The properties and dimensions of the packaging substrate are tailored to optimize the operational environment of the die, including improving thermal dissipation and enhancing performance of the die.

Abstract: A packaging technique for electronic devices includes wafer fabrication of contacts that wrap down the inside surface of a substrate post. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. A trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold beam wire extends from a connection point within the circuit into the trench. Unless an insulative substrate is used, the wire runs over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back planed to form the bottom surface of the post. Then it is selectively back etched, to expose the bottom surface of the wire, to form the inside surface of the post, and to form the bottom surface of the finished device. A solderable lead wire runs from the exposed gold wire, down the inside surface of the post, and across its bottom.

Abstract: A power semiconductor device includes upper and lower dice that have source, drain and gate contacts, a first metal sheet sandwiched by the upper and lower dice and having source and gate terminals connected to the source and gate contacts of the upper and lower dice, and upper and lower second metal sheets sandwiching assembly of the upper and lower dice and the first metal sheet and respectively having drain terminals that are connected to the drain contacts of the upper and lower dice and that are coupled to each other.

Abstract: In a semiconductor device, an insulating substrate has a plurality of through holes. A plurality of conductive posts are buried in the through-holes. The conductive posts are classified to at least one first conductive post and a pair of second conductive posts. A semiconductor element has at least one surface electrode at a surface side. The surface electrode is connected to the first conductive post by a face-down method. A metal block is formed to a square-arch shape in a cross sectional view and has a ceiling portion and both end portions. A back surface of the semiconductor element is secured to the ceiling portion while the both end portions are secured to the second conductive posts. A sealing-resin seals the semiconductor element.

Abstract: A plurality of semiconductor chips with the same structure are stacked to construct a multichip semiconductor device. In each of the semiconductor chips, an optional circuit is formed. In the optional circuit, fuses corresponding to the stacked-stage number of each chip are formed and the fuses are selectively cut off so as to permit each chip to individually receive a chip control signal.

Abstract: A package for semiconductor devices is encapsulated in an insulating resin. Multiple conductive leads project from one side of the package. Alternating leads are provided with an insulating coating which projects along a portion of their length. Leads which are not insulated are bent so as to displace them from the plane of the coated leads and space them further away from the coated leads. The bent leads are displaced a sufficient distance to provide a separation in air consistent with spacing standards for high voltage devices.

Abstract: The present invention relates to integrated circuit devices for use in such civilian equipments as an electronic equipment, electrical equipment, communication equipment and measuring and controlling equipment, and its object is to provide an integrated circuit device which has an excellent heat radiating characteristic.

Abstract: An apparatus package for high temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Abstract: A method of manufacturing a small, thin card-type storage device is capable of easily manufacturing a frame for the storage device from a variety of resin materials without molding a very thin recessed bottom of the supporter. The method prepares a card-type support frame member from resin and a sheet material, cuts the sheet material into the size of the support frame member, to form a support sheet, bonds the support sheet to a bottom surface of the support frame member, to form a frame, and fits a memory module to be fixed in an opening of the support frame member in the frame, thereby completing the card-type storage device.

Abstract: A semiconductor device includes a main circuit part having a semiconductor device formed on an electrode plate of a lead frame and a control circuit part having protective functions, which is integrally molded by a resin mold part into an integral mold structure.

Abstract: A semiconductor package includes a plurality of semiconductor devices disposed in an array surrounding a central electrode structure carried by a package support member. The package is capable of withstanding high voltages and currents and includes a heat exchanger integral therewith.

Abstract: A multi-chip module (MCM) integrated circuit package structure is proposed, which can be used to pack a plurality of semiconductor chips of different functions while nonetheless allowing the overall package size to be as small as some existing types of integrated circuit packages, such as the SO (Small Outline) and QFP (Quad Flat Package) types, so that it can be manufactured using the existing fabrication equipment. The proposed MCM integrated circuit package structure is characterized in the use of a substrate having a centrally-located opening, and at least one semiconductor chip is mounted on the front surface of the substrate and a semiconductor chip of a central-pad type having a plurality of centrally-located bonding pads is mounted on the back surface of the substrate with the centrally-located bonding pads being exposed through the opening. This arrangement allows the overall package size to be made very compact and also allows the wiring to the central-pad type semiconductor chip to be shortened.

Abstract: A multi-chip module may be formed by wire bonding a first chip within a cavity in a multi-chip carrier. A second die may be positioned over the first die, elevated therefrom, using bump bonding. In some embodiments, only a single cavity is utilized and in other embodiments, multiple cavities may be utilized, one of which mounts a first chip and the other of which mounts a second chip. In some embodiments, the second chip may be a composite of two dice coupled back-to-back so that the lowermost die may be bump bonded to the carrier and the uppermost die, facing upwardly away from the carrier, may be wire bonded thereto.

Abstract: A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array, or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

Abstract: An electrical contact, preferably made from a gold-plated, beryllium-copper flat stock which allows radio-frequency signal to pass with low noise, is provided within a housing. The electrical contact has two arms for contact with two external circuits. The electrical contact further has a pivot for allowing the electrical contact to adjust within the housing. The housing supports the electrical contact and is provided with a pivot point, such as a non-conducting rubber tip, for meeting the pivot of the electrical contact. The housing combined with one or more of the electrical contacts results in a testing port especially suited for providing high frequency communication between an electrical testing fixture and a device under test, such as a high-frequency hybrid integrated circuit.

Abstract: A circuit module includes at least one high temperature semiconductor chip having chip pads; a substrate having substrate metallization, the chip pads and the substrate metallization being substantially planar; and a deposited flexible pattern of electrical conductors capable of withstanding high temperatures and coupling selected chip pads and portions of the substrate metallization. The deposited flexible pattern of electrical conductors includes a plurality of integral interconnect segments, at least one of the integral interconnect segments including first and second leg portions and a shelf portion with the shelf portion being spaced apart from the at least one semiconductor chip and substrate and being coupled by the first leg portion to a selected chip pad and by the second leg portion to a selected portion of the substrate metallization.

Abstract: A stacked microelectronic assembly and its resulting structure includes a flexible substrate having a plurality of attachment sites, test contacts and conductive terminals, and including a wiring layer with leads extending to the attachment sites. The assembly includes a plurality of microelectronic elements assembled to the attachment sites and electrically interconnecting the microelectronic elements and the leads. The flexible substrate is folded so as to stack at least some of the microelectronic elements in substantially vertical alignment with one another to provide a stacked assembly with the conductive terminals exposed at the bottom end of the stack and the test contacts exposed at the top end of the stack. The assembly may be made using a dam and or a spacer to facilitate the folding process.

Abstract: A flat, thin decoupling capacitor is disposed inside an integrated circuit device in a coplanar relationship with a semiconductor chip and a bonding element. When connected to the power and ground plane of a device substrate or in a leadframe device, the decoupling capacitor is positioned close to the semiconductor chip to substantially reduce ground bounce and crosstalk from the semiconductor chip. When the decoupling capacitor is positioned to locate the semiconductor chip between itself and the device substrate or leadframe device, the decoupling capacitor shields electromagnetic interference from the semiconductor chip.

Abstract: A semiconductor device includes the first through third semiconductor devices which are stacked on a substrate and the first through third wires for connecting the semiconductor elements and the substrate. The first wires serve to connect electrodes of the first semiconductor element positioned uppermost and electrodes of the second semiconductor element. The second wires serve to connect the electrodes of the second semiconductor element and electrodes of the third semiconductor element. The third wires serve to connect the electrodes of the third semiconductor element and bonding pads of the substrate. Between the first wires and the electrodes of the second semiconductor element and between the second wires and the electrodes of the third semiconductor element, stud bumps are provided so as to form space therebetween, thereby avoiding short-circuits therebetween.

Abstract: A wire bonding method includes aligning the face of a capillary along a first direction to make a first wire bond at a first bond point. The capillary face is realigned to a second direction to make a second wire bond at a second bond point. The realignment may be achieved by a system including an wire bonding capillary having an indicator located thereon. A detector detects a signal from the indicator. The signal corresponds to a rotational alignment of the capillary and, therefore, to a direction of alignment of the capillary face. A first signal indicates a first alignment of the capillary face and a second signal indicates a second alignment of the capillary face. The signals may each have a relative signal strength which indicates rotational an offset of the capillary face from a given direction.

Abstract: An integrated circuit package includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin. The size of the non-wired pin is minimized, or the non-wired pin is eliminated, in order to increase the lead pin spacing. The increase in lead pin spacing prevents electrostatic discharge failure in an integrated circuit package due to electrostatic stressing of the non-wired pin.

Abstract: An image taking element has a plurality of pins on one side thereof and a substrate is provided with a plurality of pads which are to be brought into electrical contact with the pins. The side of the image taking element is bonded to the substrate with each pin opposed to one of the pads by way of an anisotropic conductive adhesive layer which exhibits electrical conductivity only in a direction substantially perpendicular to the side of the image taking element.

Abstract: A thin, small-outline semiconductor package, and a thermally enhanced leadframe for use in it, comprise a plurality of electrically conductive leads held together in a spaced, planar relationship about a central opening defined by the leads, and a thick, plate-like heat sink made of an electrically and thermally conductive metal attached to the leads such that it is centered within the opening and parallel to the plane of the leads. The heat sink has a lower surface exposed through the outer surface of a molded resin envelope encapsulating the package for the efficient dissipation of heat therefrom, and an upper surface having a recess formed into it. The recess has a planar floor with a semiconductor die attached to it, and defines a grounding ring around the periphery of the upper surface of the heat sink immediately adjacent to the edges of the die for the down-bonding of grounding wires from the die and the leads.

Abstract: An inductor includes a semiconductor substrate, pairs of pads formed on the semiconductor substrate at predetermined intervals with the pads in a pair spaced apart a predetermined distance, bonding wires connect the pads constituting the corresponding pairs of pads, and metal lines connect pads among the pairs to other pads to form a current path for the inductor. Since the inductor uses bonding wire which has low resistance and can reduce the contact area with chips, the inductor has few parasitic components and a high quality factor in nearly all frequency regions.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have a PECVD SiO2 layer formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, an insulating PECVD SiO2 layer is formed on the bonding wires to prevent short-circuits with adjacent wires. An SiO2 layer is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A process for making a semiconductor device and the resulting device having standardized die-to-substrate bonding locations are herein disclosed. The semiconductor die provides a standardized ball grid or other array of a particular size, pitch and pattern such that as the size, configuration or bond pad arrangement of the die changes, a standard substrate (the term including leadframes) having a similarly standardized array of terminals or trace ends can be employed to form a semiconductor device. It is also contemplated that dies having markedly different circuitry but a common array pattern may be employed with the same substrate or other carrier.

Abstract: An integrated circuit and associated method for reducing total signal propagation delay as well as power consumption and thermal dissipation. The integrated circuit comprises a plurality of active layers coupled together in close proximity. In order to produce the integrated circuit, at least two active layers are removed from their respective substrate after integrated circuit processing. Some of the methods that may be used include Silicon on Insulator ("SOI") and epitaxial etch stop ("EES") processes. After removal of the active layers, at least one via is implemented on a bottom surface of each active layer in order to establish a mechanical and electrical connection between the via and its associated metal interconnects. Thereafter, the active layers are coupled together by ultrasonic welding or through nitride lamination using Titanium Nitride for conductive regions and Silicon Nitride for insulative regions.

Abstract: An apparatus and method for evenly applying an atomized adhesive for bonding a die to a leadframe are disclosed. In one embodiment, the apparatus includes a hood in communication with an air supply and a vacuum plenum that encompass a semiconductor device component located in a target area during adhesive application so that the adhesive is selectively applied to specific portions of the leadframe or other semiconductor device component and adhesive is not allowed outside the system. A mask or stencil may be employed for further prevention of adhesive application to undesired areas. An air purge may be employed to direct the adhesive mist toward the component to be coated. In another embodiment, a fine adhesive spray is directed against the surface of the workpiece to be coated, selected areas being masked to prevent coating. Wafers may be coated, as well as leadframes.