With Electrical Isolation Means Patents (Class 257/725)
  • Patent number: 6979894
    Abstract: The present integrated chip package provides a low cost package that is suitable for high density semiconductors that have high power dissipation. The integrated chip package includes at least one semiconductor chip having a first surface and a second surface. The first surface of the semiconductor chip is electrically coupled to an intermediate substrate via conductive bumps. The intermediate substrate is also electrically coupled to a package substrate via a plurality of bonding wires. The second surface of the semiconductor chip is thermally coupled to a heat sink to increase the power dissipation capacity of the integrated chip package.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: December 27, 2005
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 6975024
    Abstract: In a manufacturing method of a hybrid integrated circuit device of the invention, transfer molding is carried put by positioning a curved surface formed in a back surface of the substrate on a lower mold die side and a burr formed in a main surface of the substrate on an upper mold die side. This utilizes the curved surface to inject thermosetting resin in an arrow direction to pour the thermosetting resin through a below of the substrate. There are no broken fragments of burr in a thermosetting resin at the below of the substrate. As a result, a required minimum resin thickness is secured at the below of the substrate, thus realizing a hybrid integrated circuit device having a high voltage resistance, an excellent heat dissipation property and a high product quality.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: December 13, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuhiro Koike, Hidefumi Saito, Katsumi Okawa, Junichi Iimura
  • Patent number: 6972482
    Abstract: An electronic package is provided and its method of construction. A microelectronic die is mounted to a flexible substrate. A mold cap is injection-molded over the die. The mold cap has a curved convex edge surface around which the flexible substrate wraps. Folding of the flexible substrate is controlled by the edge surface to reduce defects, ensure consistent form factor from one package to the next, and allow for the inclusion of a relatively resilient ground plane.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: December 6, 2005
    Assignee: Intel Corporation
    Inventor: José R. Salta, III
  • Patent number: 6965170
    Abstract: The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip, through the core to the bottom surface where signals exit the carrier to the printed wiring board. This fanning out is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip thereby increasing the density of circuits escaping the footprint area.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: November 15, 2005
    Assignee: International Business Machines Corporation
    Inventor: Irving Memis
  • Patent number: 6963134
    Abstract: A highly reliable semiconductor device less susceptible to external noise is provided. The semiconductor device has a signal output chip and a substrate. The signal output chip has one or more semiconductors and outputs a predetermined signal. The substrate has a circuit formed thereon and is electrically connected to the signal output chip. A potential of the substrate is fixed to a certain level.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: November 8, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Otani
  • Patent number: 6963131
    Abstract: The present invention relates to an integrated circuit system with at least one integrated circuit, a cooling body to dissipate the heat generated by the integrated circuit and a latent heat storage module having a latent heat storage medium. The latent heat storage module is thermally connected to the cooling body in order to temporarily store the heat generated by the integrated circuit and to convey it to the cooling body. The integrated circuit has at least one semiconductor component which is assembled on a substrate and the substrate is in direct thermal contact with the latent heat storage module.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: November 8, 2005
    Assignee: Tyco Electronics AMP GmbH
    Inventors: Michael Frisch, Ralf Ehler
  • Patent number: 6953981
    Abstract: The present invention relates to a semiconductor device arranged at a surface of a semiconductor substrate having an initial doping having an electrical connection comprising at least one plug made of a material with a high conductivity, especially a material other than the substrate, especially a metal plug, between said initially doped substrate and said surface of the substrate. The device has at least one ground connection arranged to be connected to a ground pin on a package. The ground connection is arranged to be connected to said ground pin using said electrical connection, where the initially doped substrate is arranged to be connected to said ground pin via a reverse side of the substrate, opposite said surface, and thereby being arranged to establish a connection between said ground connection and said ground pin.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: October 11, 2005
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Ted Johansson, Arne Rydin, Christian Nyström
  • Patent number: 6949825
    Abstract: An encapsulation for an electrical device is disclosed. The encapsulation comprises plastic substrates which are laminated onto the surface of the electrical device. The use of laminated plastics is particularly useful for flexible electrical devices such as organic LEDs.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: September 27, 2005
    Assignees: Osram Opto Semiconductor GmbH & Co. OHG, Institute of Materials Research and Engineering
    Inventors: Ewald Karl Michael Guenther, Wei Wang, Soo Jin Chua
  • Patent number: 6943446
    Abstract: An integrated circuit having electrically conductive vias with a diameter of between about one micron and about fifty microns. Prior art vias have a diameter of between no less than 0.3 microns to no more than 0.8 microns. In this manner, stresses such as those that press down upon the top surface of the integrated circuit can be absorbed by the large vias and transferred past fragile layers, such as low k layers, so that the fragile layers are not damaged by the stresses.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventors: John P. McCormick, Ivor G. Barber, Kumar Nagarajan
  • Patent number: 6943445
    Abstract: The present invention provides a semiconductor device which reduces an inductance of wiring for bridge-connecting semiconductor switches and realizes a reduction in size. Within the semiconductor device formed are two controllable bridge-connected semiconductor switches 13a and 13b, an output terminal, positive/negative polarity DC terminals 2 and 3, and an insulating substrate 15a in which conductor layers 12, 17 and 19 having a conductor section and in an inner layer for bridge-connecting the semiconductor switches to the DC terminals on a surface thereof and insulating layers 16 and 18 are alternately laminated. The surface and inner-layer conductor layers 12 and 17 which interpose the insulating layer 16 therebetween are electrically connected by a conductor 20 passing through the insulating layer 16 interposed between the conductor layers 12 and 17.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: September 13, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Shirakawa, Akira Mishima, Keiichi Mashino, Toshiyuki Innami, Shinichi Fujino, Hiromichi Anan, Yoshitaka Ochiai
  • Patent number: 6940184
    Abstract: A semiconductor device includes a first lead having an inner portion on which a semiconductor chip is mounted, a second lead having an inner portion electrically connected to the semiconductor chip via a wire and a resin package for sealing the semiconductor chip and the wire. The inner portions, the semiconductor chip and the wire are coated with a coating film formed of amorphous fluororesin.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: September 6, 2005
    Assignee: Rohm Co., Ltd.
    Inventors: Takashi Ueda, Kiyohiro Isogawa
  • Patent number: 6940164
    Abstract: A power module incorporates a switching semiconductor element and a smoothing capacitor and includes a metallic base plate dissipating heat produced by the switching semiconductor element and the smoothing capacitor. The metallic base plate is thermally separated into a first region adjacent to the switching semiconductor element and a second region adjacent to the smoothing capacitor.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: September 6, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoki Yoshimatsu, Dai Nakajima
  • Patent number: 6930378
    Abstract: A stack of semiconductor dies is disclosed. A first stack level includes a first semiconductor die and at least one first support that are attached to a substrate surface. A second level includes a second semiconductor die and at least one second support that are attached to the active surface of the first semiconductor die and to a coplanar surface of the first support(s). A third level includes a third semiconductor die attached to the active surface of the second semiconductor die and to a coplanar surface of the second support(s). The second and third semiconductor dies do not overlap bond pads of the first and second semiconductor dies, respectively. An adhesive film overlies the entire inactive surface of the second and third semiconductor dies, and attaches the second and third semiconductor dies to the immediately underlying active surface and support(s).
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: August 16, 2005
    Assignee: Amkor Technology, Inc.
    Inventors: Roger D. St. Amand, Vladimir Perelman
  • Patent number: 6922341
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: July 26, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Sion C. Quinlan, Tim J. Bales
  • Patent number: 6919625
    Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: July 19, 2005
    Assignee: General Semiconductor, Inc.
    Inventors: Paddy O'Shea, Eamonn Medley, Finbarr O'Donoghue, Gary Horsman
  • Patent number: 6919632
    Abstract: A semiconductor integrated circuit device includes connection members arranged on an entire chip, a first I/O cell which is arranged on the periphery of the chip and has a first end portion on the peripheral side of the chip and a second end portion on the center side of the chip, a second I/O cell which is arranged inside the first I/O cell and has a third end portion on the peripheral side of the chip and a fourth end portion on the center side of the chip, first terminals formed on the first end portion and connected to the connection members, second terminals formed on the second end portion and connected to an internal circuit of the chip, third terminals formed on the third end portion and connected to the internal circuit, and fourth terminals formed on the fourth end portion and connected to the connection members.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: July 19, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshikazu Sei
  • Patent number: 6914280
    Abstract: Since a 5 GHz-band broadband has a frequency twice that of 2.4 GHz, the parasitic capacitance greatly influences deterioration in isolation of a switching device used in this frequency region. Therefore, to improve isolation, a shunt FET is added to the device. The switching device also includes a protecting element that has a first n+-type region, an insulating region and a second n+-type region. This protecting element is connected in parallel between two electrodes of the shunt FET. Since electrostatic charges are discharged between the first and second n+-type regions, the electrostatic energy reaching an operation region of the shunt FET can be reduced without an increase in parasitic capacitance.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: July 5, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Yoshibumi Nakajima, Hidetoshi Ishihara
  • Patent number: 6911724
    Abstract: The present integrated chip package provides a low cost package that is suitable for high density semiconductors that have high power dissipation. The integrated chip package includes at least one semiconductor chip having a first surface and a second surface. The first surface of the semiconductor chip is electrically coupled to an intermediate substrate via conductive bumps. The intermediate substrate is also electrically coupled to a package substrate via a plurality of bonding wires. The second surface of the semiconductor chip is thermally coupled to a heat sink to increase the power dissipation capacity of the integrated chip package.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: June 28, 2005
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 6909178
    Abstract: As conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: June 21, 2005
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi, Takeshi Nakamura
  • Patent number: 6906409
    Abstract: A multichip semiconductor package and method of making is provided that has a plurality of semiconductor chips fabricated in electrical isolation one from another integrally on a singular coextensive substrate useful for numerous and varied semiconductor chip applications. The semiconductor chips, instead of being singulated into a plurality of single-chip packages, are kept as integrally formed together and are thereafter electrically connected together so as to form a larger circuit. Encapsulation follows so as to form a single, multichip package. Common signals of the plurality of semiconductor chips are bussed together in electrical common across the substrate to a common electrode suitable for electrically providing the signal to another, external circuit, such as a PWB. The common bussing is achieved by conductive leads disposed across the substrate in pair sets having an extended portion that accommodates the common electrode in contact therewith.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: June 14, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Jerrold L. King, Jerry M. Brooks
  • Patent number: 6897552
    Abstract: There is here disclosed a semiconductor device comprising a chip-mounting-member having a lead formed on its major surface, the lead having a thin film plated portion which covers a surface of a predetermined portion of the lead, a semiconductor chip having a bump formed on its major surface, and mounted on the chip-mounting-member by electrically connecting the bump to the lead via the plated portion, and an encapsulating-member formed between the semiconductor chip and the chip-mounting-member.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: May 24, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiro Nakao
  • Patent number: 6882046
    Abstract: The present invention allows multiple IC devices to be placed on the same substrate within a single BGA package. The invention requires minimum distances to be kept between electrical connections of the IC devices to maintain the electrical isolation, so that the devices can be operated at different voltage differentials. Signals between the devices can be connected externally from the package to each other utilizing galvanic isolation techniques. The invention provides the flexibility of choice for the customers to use isolation or not between the devices and takes up less PC board space because only a single package is used on the board.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: April 19, 2005
    Assignee: Koninklijke Phillips Electronics N.V.
    Inventors: Joel Wayne Davenport, Robert R. Parker, Jeff E. Conder
  • Patent number: 6879036
    Abstract: A semiconductor memory device for use in a semiconductor device with a chip on chip structure, which enables a memory specification to be selected and fixed, and improves design and production efficiencies. Bonding bumps corresponding to an input terminal and an output terminal of an interface circuit are connected to bonding bumps provided on another semiconductor device. Then, a polarity of a potential on a bus width varying terminal is fixed by the bonding bump provided on another semiconductor device, so that an isolated input/output specification is selected as a bus specification of the interface circuit and a bus width is selected.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: April 12, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuyuki Nakai
  • Patent number: 6870261
    Abstract: A discrete circuit component having an up-right circuit die with lateral electrical connections. The component comprises a substrate having a pair of electrically conductive traces, and a circuit die is planted between the pair of consecutive traces, wherein one electrode of the circuit die on the surface thereof vertical to the substrate is electrically bonded to one of the conductive trace immediately next thereto, while the other electrode of the circuit die on the opposite surface thereof vertical to the substrate is electrically bonded to the other of the pair of conductive traces immediately next thereto. A body of electrical insulation material hermetically seals the circuit die, and a pair of surface electrodes formed on the surface of the body of insulation material are each electrically connected to the corresponding one of the pair of electrically conductive traces extending from the circuit die.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: March 22, 2005
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Chih-Liang Hu, Wen-Long Chen, Pan-Nan Chen, Ming-Chong Liang, Cheen-Hai Yu
  • Patent number: 6853287
    Abstract: There is provided a coil and a method for fabricating the same. One embodiment of the coil includes a plurality of traces in one area of a substrate. Each trace has a first end located at a first side of the area, and a second end located at a second side of the area opposite the first side. A plurality of wires couples the plurality of traces to form a coil. Each wire couples the first end of one trace to the second end of another trace located adjacent to the one trace.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: February 8, 2005
    Assignee: Intel Corporation
    Inventors: Peter Kirkpatrick, Thomas Mader, Jean-Marc Verdiell
  • Patent number: 6847105
    Abstract: A stacked semiconductor package including a plurality of stacked semiconductor devices on a substrate, and a method of forming the same. The semiconductor devices are stacked in an active surface-to-backside configuration. The top semiconductor die is flipped over to face the active surface of the semiconductor die directly below. An electrical connector can extend from a bond pad on the top semiconductor die to a redistribution circuit on the semiconductor die below. The redistribution circuit can be electrically connected to a substrate. Alternatively, an electrical connector extends from a bond pad on top semiconductor die to a bond pad on a substrate.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: January 25, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Michel Koopmans
  • Patent number: 6828664
    Abstract: The present invention relates to a packaging substrate with electrostatic discharge protection. The packaging substrate is disposed in a recess of a mold and comprises an outer wall electrically connecting an inner wall of the recess. A first copper-mesh layer and a second copper-mesh layer extend to the outer wall to electrically connect the inner wall of the recess. Static electric charges generated during the molding process are conducted via the first copper-mesh layer or the second copper-mesh layer to the inner wall of the recess and then conducted away. Therefore, the static electric charges generated during the molding process can be safely conducted away from the packaging substrate, preventing the dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: December 7, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Pin Hung, Yung-Chi Lee
  • Publication number: 20040238941
    Abstract: Through an improvement of module size increase due to mounting a single passive element on a substrate and an increase in the mounting cost, to provide a highly reliable, high performance and small sized semiconductor connection substrate which permits to integrate a variety of electronic parts such as capacitors, inductors and resistors in a high density with low cost.
    Type: Application
    Filed: January 12, 2004
    Publication date: December 2, 2004
    Inventors: Toshiya Satoh, Masahiko Ogino, Takao Miwa, Takashi Naitou, Takashi Namekawa
  • Patent number: 6822325
    Abstract: Temperature sensitive devices may be shielded from temperature generating devices on the same integrated circuit by appropriately providing a trench that thermally isolates the heat generating devices from the temperature sensitive devices. In one embodiment, the trench may be formed by a back side etch completely through an integrated circuit wafer. The resulting trench may be filled with a thermally insulating material.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: November 23, 2004
    Assignee: Altera Corporation
    Inventor: Ting-Wah Wong
  • Patent number: 6818985
    Abstract: According to one exemplary embodiment, a structure comprises a laminate substrate having a top surface for receiving a semiconductor die. The structure further comprises an antenna element situated on the top surface of the laminate substrate, where the antenna element is coupled to a laminate substrate bond pad. For example, the antenna element may also be coupled to the laminate substrate bond pad by a trace on the top surface of the laminate substrate. According to this exemplary embodiment, the structure further comprises a bonding wire that provides an electrical connection between the laminate substrate bond pad and a semiconductor die bond pad. For example, the input impedance of the antenna element coupled to the laminate substrate bond pad may match the output impedance at the semiconductor die bond pad. The structure may further comprise a capacitor coupled to the antenna element.
    Type: Grant
    Filed: December 22, 2001
    Date of Patent: November 16, 2004
    Assignee: Skyworks Solutions, Inc.
    Inventors: Roberto Coccioli, Mohamed A. Megahed, Trang N. Trinh, Larry D. Vittorini, John S. Walley
  • Patent number: 6812561
    Abstract: A high-frequency module of the invention includes an insulating substrate including a plurality of ceramic thin plates stacked in layers, and an insulating layer formed on the top surface of the insulating substrate. In the high-frequency module, a thin-film circuit is formed on the top surface of the insulating layer, and comprises a wiring pattern and an electrical part comprising a resistor and/or a capacitor. The wiring pattern is formed of a thin film. The electrical part is connected to the wiring pattern and is formed of a thin film. Therefore, the electrical part of the high-frequency module of the invention can be formed more precisely than an electrical part of a related high-frequency module. Consequently, it is possible to provide a high-frequency module having high performance.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: November 2, 2004
    Assignee: Alps Electric Co., Ltd.
    Inventor: Shigetoshi Matsuta
  • Patent number: 6803514
    Abstract: A mounting structure for mounting a photovoltaic element onto a metal body, which outputs a power generated by the photovoltaic element to the outside surface, and a method for mounting the photovoltaic element. In the mounting structure, the metal body has a first surface and a second surface opposite the first surface, in which the photovoltaic element is joined to the first surface and an electrically insulative material is joined to the second surface. A semiconductor element-mounting substrate for mounting a semiconductor element thereon comprising a retaining substrate having a circuit pattern, which has an electrode-joining portion for joining the semiconductor element electrode portion, an external terminal-fixing portion, and a groove between the electrode-joining portion and external-fixing portion, and a method for mounting the semiconductor element. In the mounting substrate, the electrode-joining portion is larger than the semiconductor element electrode portion.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: October 12, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshifumi Takeyama
  • Publication number: 20040195683
    Abstract: An electronic device includes a package having a metal part shaped by pressing a metal member, and an insulator part bonded to the metal part through fusing. A chip is housed in the package. First terminals are electrically connected to the chip and are buried in the insulator part so as to be arranged in a line. A plate member supports the chip from the backside thereof. The metal parts have recess portions that define second external terminals. The plate member is provided so as to cover the recess portions.
    Type: Application
    Filed: March 26, 2004
    Publication date: October 7, 2004
    Applicants: Fujitsu Media Devices Limited, Fujimaru Industry Co., Ltd.
    Inventors: Naoyuki Mishima, Takamasa Oto
  • Patent number: 6790704
    Abstract: A method for electrically coupling a first set of electrically conductive pads on a first semiconductor substrate to a second set of electrically conductive pads on a second semiconductor substrate is described. Dielectric material of a first thickness is deposited on at least one set of the first and second sets of electrically conductive pads. The first and second semiconductor substrates are then attached together such that such that the first and second sets of pads are substantially aligned parallel to one another and such that the dielectric material is disposed between the first and second sets of electrically conductive pads.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: Brian Doyle, Quat T. Vu, David B. Fraser
  • Patent number: 6787902
    Abstract: A package with increased capacitance comprises a core and a plurality of buildup layers. The core has an inner dielectric portion and the core outer conductive layer. The buildup layers are disposed over the core and have offset ablated regions reducing the thickness of the buildup layers in the ablated regions. Conductive material is plated on the buildup layers including within the ablated regions. The reduced thickness and increased plate area due to the ablated regions increases the capacitance between adjacent buildup layers. Processors and processing systems may take advantage of the increased capacitance in the package to draw more current and operate at higher data rates.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: September 7, 2004
    Assignee: Intel Corporation
    Inventor: Mahadevan Survakumar
  • Patent number: 6780767
    Abstract: Semiconductor components in a wafer assembly, in which the components are connected to a frame by means of in each case one holder and are formed from the same silicon wafer. The holder connects the respective component to the frame on one side and has a desired breaking point. The desired breaking point is designed as a V-shaped groove, the surfaces of which form crystal planes. According to the method, the patterning for production of the holder takes place on the wafer back surface, with subsequent wet chemical anisotropic etching of the V-groove. In this way, the holder is produced independently of the processing of the wafer front surface, and when the semiconductor component is removed a defined broken edge is formed without there being any risk of the semiconductor component being damaged.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: August 24, 2004
    Assignee: Nanoworld AG
    Inventor: Stefan Lutter
  • Patent number: 6780696
    Abstract: Methods for fabricating an assembly having functional blocks coupling to a substrate. The method includes providing the substrate with receptor sites wherein each of the receptor sites is designed to couple to one of the functional blocks. Electrodes are coupled to the substrate. The electrodes cover the receptor sites such that portions of the receptor sites are coated with the electrodes. Applying a voltage source to the electrodes using a first electrical circuit such that each electrode has a voltage different from another electrode. The electrodes form an electric field. The functional blocks having electronic devices and being in a slurry solution are dispensed over the substrate. Each functional block is fabricated out of materials having a high dielectric constant such that said functional blocks are attracted to the higher field strength regions and are guided to the receptor sites.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: August 24, 2004
    Assignee: Alien Technology Corporation
    Inventor: Kenneth David Schatz
  • Patent number: 6777791
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) power package includes a conductive mounting flange mounted on a heat sink and electrically connected to a dielectric substrate of a printed circuit board. A plurality of transistors are mounted on the top surface of the mounting flange. Each of the transistors has an input terminal, an output terminal, and a ground terminal, with the ground terminal of each transistor being electrically coupled to the top surface of the mounting flange. A plurality of parallel ground signal return paths are provided to electrically couple the top surface of the mounting flange to the dielectric substrate, thereby reducing resistance and inductance in the ground signal path and increasing the efficiency of the power package.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: August 17, 2004
    Assignee: Infineon Technologies AG
    Inventors: Larry Leighton, Tom Moller, Bengt Ahl, Henrik Hoyer
  • Patent number: 6777793
    Abstract: The present invention relates to a packaging substrate with electrostatic discharge protection. The packaging substrate is deposited in a packaging mold, and the packaging mold comprises a plurality of injection pins for pushing the packaging substrate out of the packaging mold. A first copper-mesh layer and a second copper-mesh layer of the packaging substrate are electrically connected to each other via position pins. A bottom side of the packaging substrate comprises a plurality of recesses in positions corresponding to positions of the injection pins. The recesses pass the second copper-mesh layer to electrically connect the injection pins to the second copper-mesh layer, and static electric charges are conducted to the injection pins via the second copper-mesh layer and away from the packaging substrate. It prevents dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: August 17, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Tsang Lee, Kuang-Lin Lo
  • Patent number: 6777804
    Abstract: A flip-chip package has a first surface and a corresponding second surface. The chip is adapted to be disposed on the first surface of the substrate and electrically connected to the substrate. The chip has a centerline, which evenly divides the chip into two equal parts. The substrate has a peripheral connection-pad layout region disposed on the second surface of the substrate. The peripheral connection-pad layout region has a centerline neighboring region which the centerline of the chip traverses. The substrate also has a plurality of central connection pads disposed in the centerline neighboring region. Within the centerline neighboring region, at both sides of the centerline of the chip is respectively lined with the central connection pads in three rows. The central connection pads in each row are lined in parallel to the direction extending the centerline.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: August 17, 2004
    Assignee: VIA Technologies, Inc.
    Inventor: Chi-Hsing Hsu
  • Publication number: 20040154163
    Abstract: A resist post is formed on a connection pad of a semiconductor chip, and the semiconductor chip and the resist post are covered by a heat resistant insulating layer. A surface of the insulating layer is next polished by CMP or the like, thus an upper surface of the resist post being exposed. The exposed resist post is then removed by developing processing or the like, thus forming a through hole. A conductor is then embedded in the through hole by plating, thus forming a connecting conductor, and wirings are formed. A method of forming the connecting conductor does not impart damage to the semiconductor chip.
    Type: Application
    Filed: February 5, 2004
    Publication date: August 12, 2004
    Inventors: Shinichi Miyazaki, Hirokazu Honda, Kenji Ooyachi
  • Patent number: 6774476
    Abstract: A power converter having at least two semiconductor substrates is provided. Each of the substrates has at least two contact surfaces, and the converter also has two thermally conductive mounting plates carrying the semiconductor substrates, which each have an electrical terminal, an attachment arrangement implemented on one of the mounting plates, and having at least one third electrical terminal, which is distinguished in that the mounting plates and the semiconductor substrates form stacks, the mounting plates receiving the semiconductor substrates between themselves, and an electrically and thermally conductive insert, which has at least the third terminal, is arranged between the semiconductor substrates.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: August 10, 2004
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Alexander Wallrauch, Christoph Ruf, Peter Urbach, Uwe Knappenberger
  • Patent number: 6756689
    Abstract: A power device having a multi-chip package structure and a manufacturing method therefor are provided. In the power device, a transistor, which is a switching device, and a control integrated circuit (IC) chip, which is a driving device, are mounted together in a package, thereby requiring a high insulation withstand voltage between the transistor chip and the control IC chip. The power device and the manufacturing method can simplify a packaging process by attaching the control IC chip on a chip pad of a lead frame using an insulating adhesive tape at a level with the transistor chip. Furthermore, the overall size of a package in the power device can be reduced by attaching the control IC chip on top of the transistor chip using the insulating adhesive tape. In the case of attaching the control IC chip on the top of the transistor chip, a liquid non-conductive adhesive can be used instead of an insulating adhesive tape.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: June 29, 2004
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Shi-baek Nam, O-seob Jun
  • Patent number: 6747300
    Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: June 8, 2004
    Assignee: Ternational Rectifier Corporation
    Inventors: Bruno C. Nadd, Vincent Thiery, Xavier de Frutos, Chik Yam Lee
  • Patent number: 6740962
    Abstract: Stiffeners for tapes, films, or other connective structures that are configured to be secured to a semiconductor device component, such as a semiconductor die or substrate, by tape-automated bonding processes. The stiffeners are fabricated by stereolithographic processes and may include one layer or two or more superimposed, contiguous, mutually adhered layers. The stiffeners are configured to prevent torsional flexion or bending of the connective structure to which they are to be secured. The stiffeners may include apertures through which intermediate conductive elements or other structures secured to the connective structure may be exposed or protrude. Stiffeners that reinforce sprocket or indexing holes in a connective structures are also disclosed.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: May 25, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Ford B. Grigg
  • Publication number: 20040090756
    Abstract: A structure of a chip package and a process thereof are provided. The process of the chip package makes use of the TFT-LCD panel or IC process to increase the circuit layout density for high electrical performance. First, a multi-layer interconnection structure with pads of high layout density and thin fine circuits is formed on a base substrate with a large-area and high co-planarity surface, wherein the base substrate is made of quartz or glass or ceramics. Then, a chip is located on the top surface of the multi-layer interconnection structure by flip-chip or wire-bonding technology. Then, a substrate or a heat sink is attached on the top surface of the multi-layer interconnection structure for being a stiffener and providing mechanical support. Finally, the base substrate is removed and contacts are attached on the bottom surface of the multi-layer interconnection structure.
    Type: Application
    Filed: March 13, 2003
    Publication date: May 13, 2004
    Inventors: Kwun-Yo Ho, Moriss Kung
  • Patent number: 6712284
    Abstract: In a high frequency semiconductor device, a shield plate which is connected to the ground potential is provided above an MMIC structure including line conductors, with an insulating interlayer provided therebetween. By using the shield plate to shield the MMIC, interference caused by external electromagnetic waves or leakage of electromagnetic waves to the exterior can be reduced in a chip alone.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: March 30, 2004
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Yoshio Aoki, Yutaka Mimino, Osamu Baba, Muneharu Gotoh
  • Patent number: 6707165
    Abstract: An encapsulant molding technique used in chip-on-board encapsulation wherein a residual organic compound layer on the surface of a substrate is used to facilitate removal of unwanted encapsulant material. An organic compound layer which inherently forms on the substrate during the fabrication of the substrate or during various chip attachment processes is masked in a predetermined location with a mask. The substrate is then cleaned to remove the organic compound layer. The mask protects the masked portion of the organic material layer which becomes a release layer to facilitate gate break. An encapsulant mold is placed over the substrate and chip and an encapsulant material is injected into the encapsulant mold cavity through an interconnection channel. The release layer is formed in a position to reside as the bottom of the interconnection channel. Preferably, the interconnection channel has a gate adjacent the encapsulant mold cavity.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: March 16, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Richard W. Wensel
  • Patent number: 6707161
    Abstract: A flip-chip-bonded optical module package using flip chip bonding is provided. The flip-chip-bonded optical module package includes an optical device chip which has an input/output pad formed on a substrate, an under bump metal layer fanned on the input/output pad, and a solder bump formed on the under bump metal layer to transmit an electric signal to the outside. The flip-chip-bonded optical module package includes a silicon wafer through which a through hole is formed, on which an under ball metal layer is formed, and to which the optical device chip is flip-chip-banded. The flip-chip-banded optical module package includes a solder ball which is fanned on the under ball metal layer and transmits an electrical signal from the solder bump to the outside, and an optical fiber which is inserted into the through hole and is optically coupled with the optical device chip.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: March 16, 2004
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong-tae Moon, Yong-sung Eom
  • Publication number: 20040041258
    Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.
    Type: Application
    Filed: August 28, 2003
    Publication date: March 4, 2004
    Applicant: Samsung Electronic Co., Ltd.
    Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee