Abstract: Structures and techniques for mounting semiconductor dies are disclosed. In one embodiment, the invention includes a stack of printed wiring board assemblies that are connected via interconnection components. At least one of the printed wiring board assemblies includes an interposer substrate having a constraining layer that includes carbon.

Abstract: A bottom die and a top die stacked on the bottom die are configured to provide a daisy chain function. Both die include an input/output function control bonding pad (20G), a first bonding pad (20C) controllable to function as either an input or an output, and a second bonding pad (20E) controllable to function as either an output or an electrically floating pad in response to a corresponding input/output function control signal. The top die (30) is stacked on the bottom die (20) and the first bonding pad (20C) of the bottom die (20) is wire bonded to the first bonding pad (30C) of the top die (30). A first reference voltage (VDD) on the function control bonding pad of the bottom die configures its first bonding pad as an output and its second bonding pad as electrically floating, and a second reference voltage (VSS) on the function control bonding pad of the top die configures its first bonding pad as an input and its second bonding pad as an output, to thereby provide the daisy chain function.

Abstract: Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: An elongated strip of a sheetlike substrate bearing microelectronic elements such as semiconductor chips is advanced in a downstream direction through one or more folding stations where successive portions of the substrate are folded so as to form a strip including a plurality of fold packages, each including confronting top and bottom runs and a fold region with one or more of the runs bearing one or more microelectronic elements. The strip incorporating the plural fold packages can be wound on a reel or otherwise handled, stored and shipped to a subsequent manufacturing operation, where individual fold packages can be severed from the strip.

Abstract: A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

Abstract: To provide a piezoelectric oscillator which can be reduced in size by reducing the planar size. With regard to a layered lead frame comprising two lead frames and, connection leads for connection with a piezoelectric resonator are formed on the upper lead frame and the connection leads are erected upwards so as to form connection terminals, and mounting leads for mounting to a mounting board are formed on the lower lead frame and the mounting leads are erected downwards so as to form mounting terminals, and an IC forming an oscillating circuit is mounted on the layered lead frame, the piezoelectric resonator formed by sealing a piezoelectric resonator element within a package is mounted on the layered lead frame, and the layered lead frame and the piezoelectric resonator are sealed within a resin package such that the principal surface of the mounting terminals are exposed outwards, thereby forming a completed article.

Abstract: A semiconductor device is provided having a single-piece clip that interlocks into a lead frame using one or more forks on the clip that mate with one or more corresponding slots in the lead frame. A semiconductor die is mounted to a pad of the lead frame and the clip couples the die to a conductive lead of the lead frame. The interlocking coupling forms a lever that allows adjustment of a position of the clip relative to a region of the semiconductor die. Interference between the clip fork and a slot corresponding to the clip fork confines the lever motion or pivoting of the clip relative to the mounted semiconductor die. The coupling between the clip fork and the slot furthermore confines motion of the clip in each of a first dimension and a second dimension relative to a position of the lead frame.

Abstract: A true single-chip radio for bidirectional wireless communications includes a bulk substrate, at least one integrated antenna, at least one transceiver, baseband circuitry and at least one filter all integrally formed in or on the substrate. The radio preferably includes a low-loss dielectric propagating layer disposed beneath the substrate to improve antenna gain. The integrated antenna can be an adaptive array for beamforming.

Abstract: A contact-less high-speed signaling interface and method provide for the communication of high-speed signals across an interface, such as a die-substrate interface or die-die interface. The interface includes a transmission-line structure disposed on a dielectric medium to carry a high-speed forward incident signal, and another transmission-line structure disposed on another dielectric medium and substantially aligned with the other transmission-line structure to generate a coupled high-speed signal in a direction opposite to the incident signal.

Abstract: A semiconductor package that includes two circuit boards and at least one semiconductor device which is disposed between the two circuit boards and connected to external connectors disposed on at least one of the circuit boards.

Abstract: A method for packaging electronic assemblies and a multiple chip package, at least one power semiconductor chip being applied to a base plate using a first solder, at least one logic chip being applied to the base plate, the logic chip and the base plate being positioned electrically insulated from one another, at least one logic chip being connected to the at least one power semiconductor chip using signal transmission lines, and the electronic assembly including the at least one power semiconductor chip and the at least one logic chip being packaged using a molding compound in order to provide a multiple chip package.

Abstract: To isolate at least one electric or electronic element (16, 58), for example an interconnection integrated onto a semiconductor substrate (12), this device comprises at least one isolation means chosen from an isolating layer (84, 86, 90) extending in the substrate and an assembly whose height exceeds that of the element and which comprises, on either side of the element, at least two superposed conductors (60 62 64, 66 68 70), which are integrated into the substrate and extend along the element.

Abstract: A semiconductor chip package that includes a DC—DC converter implemented with a land grid array for interconnection and surface mounting to a printed circuit board. The package includes a two layer substrate comprising a top surface and a bottom surface. At least one via array extends through the substrate. Each via in a via array includes a first end that is proximate to the top surface of the substrate and a second end that is proximate to the bottom surface of the substrate. At least one die attach pad is mounted on the top surface of the substrate and is electrically and thermally coupled to the via array. The DC—DC converter includes at least one power semiconductor die having a bottom surface that forms an electrode. The power semiconductor die is mounted on a die attach pad such that the bottom surface of the die is in electrical contact with the die attach pad. The bottom of the package forms a land grid array.

Abstract: A semiconductor device including a semiconductor substrate having a grid-line area and a chip area, the chip area having a circuit area and a dummy area surrounding the circuit area, circuit patterns formed on the substrate in the circuit area, a first dummy pattern which is formed of the same material as the circuit pattern, formed in the dummy area, the dummy pattern encompassing the circuit area, a first insulating layer formed on an entire surface of the semiconductor substrate, a second insulating layer formed only on the first insulating layer which is formed on the semiconductor substrate and on the circuit patterns; and a third insulating layer formed on the exposed first insulating layer and the second insulating layer.

Abstract: In one embodiment, a device includes but is not limited to: a first integrated circuit affixed to a substrate; an electronic circuit component affixed to the substrate; a first encapsulation structure encasing the first integrated circuit; a second integrated circuit affixed to the first encapsulation structure; and a second encapsulation structure which at least partially encases the first encapsulation structure, the first integrated circuit, and the electronic component.

Abstract: The present integrated chip package provides a low cost package that is suitable for high density semiconductors that have high power dissipation. The integrated chip package includes at least one semiconductor chip having a first surface and a second surface. The first surface of the semiconductor chip is electrically coupled to an intermediate substrate via conductive bumps. The intermediate substrate is also electrically coupled to a package substrate via a plurality of bonding wires. The second surface of the semiconductor chip is thermally coupled to a heat sink to increase the power dissipation capacity of the integrated chip package.

Abstract: A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a back surface, the back surface of the chip adjacent the interposer 31, and the top surface including a plurality of terminals. Also included is a layer of polymeric material 34 disposed on the first surface 311 of the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric material layer is between the chip 30 and the interposer 31. The device further includes a plurality of electrical connections 35 between the chip terminals and the bond pads 351 on the interposer.

Abstract: The present integrated chip package provides a low cost package that is suitable for high density semiconductors that have high power dissipation. The integrated chip package includes at least one semiconductor chip having a first surface and a second surface. The first surface of the semiconductor chip is electrically coupled to an intermediate substrate via conductive bumps. The intermediate substrate is also electrically coupled to a package substrate via a plurality of bonding wires. The second surface of the semiconductor chip is thermally coupled to a heat sink to increase the power dissipation capacity of the integrated chip package.

Abstract: In a manufacturing method of a hybrid integrated circuit device of the invention, transfer molding is carried put by positioning a curved surface formed in a back surface of the substrate on a lower mold die side and a burr formed in a main surface of the substrate on an upper mold die side. This utilizes the curved surface to inject thermosetting resin in an arrow direction to pour the thermosetting resin through a below of the substrate. There are no broken fragments of burr in a thermosetting resin at the below of the substrate. As a result, a required minimum resin thickness is secured at the below of the substrate, thus realizing a hybrid integrated circuit device having a high voltage resistance, an excellent heat dissipation property and a high product quality.

Abstract: An electronic package is provided and its method of construction. A microelectronic die is mounted to a flexible substrate. A mold cap is injection-molded over the die. The mold cap has a curved convex edge surface around which the flexible substrate wraps. Folding of the flexible substrate is controlled by the edge surface to reduce defects, ensure consistent form factor from one package to the next, and allow for the inclusion of a relatively resilient ground plane.

Abstract: The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip, through the core to the bottom surface where signals exit the carrier to the printed wiring board. This fanning out is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip thereby increasing the density of circuits escaping the footprint area.

Abstract: The present invention relates to an integrated circuit system with at least one integrated circuit, a cooling body to dissipate the heat generated by the integrated circuit and a latent heat storage module having a latent heat storage medium. The latent heat storage module is thermally connected to the cooling body in order to temporarily store the heat generated by the integrated circuit and to convey it to the cooling body. The integrated circuit has at least one semiconductor component which is assembled on a substrate and the substrate is in direct thermal contact with the latent heat storage module.

Abstract: A highly reliable semiconductor device less susceptible to external noise is provided. The semiconductor device has a signal output chip and a substrate. The signal output chip has one or more semiconductors and outputs a predetermined signal. The substrate has a circuit formed thereon and is electrically connected to the signal output chip. A potential of the substrate is fixed to a certain level.

Abstract: The present invention relates to a semiconductor device arranged at a surface of a semiconductor substrate having an initial doping having an electrical connection comprising at least one plug made of a material with a high conductivity, especially a material other than the substrate, especially a metal plug, between said initially doped substrate and said surface of the substrate. The device has at least one ground connection arranged to be connected to a ground pin on a package. The ground connection is arranged to be connected to said ground pin using said electrical connection, where the initially doped substrate is arranged to be connected to said ground pin via a reverse side of the substrate, opposite said surface, and thereby being arranged to establish a connection between said ground connection and said ground pin.

Abstract: An encapsulation for an electrical device is disclosed. The encapsulation comprises plastic substrates which are laminated onto the surface of the electrical device. The use of laminated plastics is particularly useful for flexible electrical devices such as organic LEDs.

Abstract: An integrated circuit having electrically conductive vias with a diameter of between about one micron and about fifty microns. Prior art vias have a diameter of between no less than 0.3 microns to no more than 0.8 microns. In this manner, stresses such as those that press down upon the top surface of the integrated circuit can be absorbed by the large vias and transferred past fragile layers, such as low k layers, so that the fragile layers are not damaged by the stresses.

Abstract: The present invention provides a semiconductor device which reduces an inductance of wiring for bridge-connecting semiconductor switches and realizes a reduction in size. Within the semiconductor device formed are two controllable bridge-connected semiconductor switches 13a and 13b, an output terminal, positive/negative polarity DC terminals 2 and 3, and an insulating substrate 15a in which conductor layers 12, 17 and 19 having a conductor section and in an inner layer for bridge-connecting the semiconductor switches to the DC terminals on a surface thereof and insulating layers 16 and 18 are alternately laminated. The surface and inner-layer conductor layers 12 and 17 which interpose the insulating layer 16 therebetween are electrically connected by a conductor 20 passing through the insulating layer 16 interposed between the conductor layers 12 and 17.

Abstract: A power module incorporates a switching semiconductor element and a smoothing capacitor and includes a metallic base plate dissipating heat produced by the switching semiconductor element and the smoothing capacitor. The metallic base plate is thermally separated into a first region adjacent to the switching semiconductor element and a second region adjacent to the smoothing capacitor.

Abstract: A semiconductor device includes a first lead having an inner portion on which a semiconductor chip is mounted, a second lead having an inner portion electrically connected to the semiconductor chip via a wire and a resin package for sealing the semiconductor chip and the wire. The inner portions, the semiconductor chip and the wire are coated with a coating film formed of amorphous fluororesin.

Abstract: A stack of semiconductor dies is disclosed. A first stack level includes a first semiconductor die and at least one first support that are attached to a substrate surface. A second level includes a second semiconductor die and at least one second support that are attached to the active surface of the first semiconductor die and to a coplanar surface of the first support(s). A third level includes a third semiconductor die attached to the active surface of the second semiconductor die and to a coplanar surface of the second support(s). The second and third semiconductor dies do not overlap bond pads of the first and second semiconductor dies, respectively. An adhesive film overlies the entire inactive surface of the second and third semiconductor dies, and attaches the second and third semiconductor dies to the immediately underlying active surface and support(s).

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.

Abstract: A semiconductor integrated circuit device includes connection members arranged on an entire chip, a first I/O cell which is arranged on the periphery of the chip and has a first end portion on the peripheral side of the chip and a second end portion on the center side of the chip, a second I/O cell which is arranged inside the first I/O cell and has a third end portion on the peripheral side of the chip and a fourth end portion on the center side of the chip, first terminals formed on the first end portion and connected to the connection members, second terminals formed on the second end portion and connected to an internal circuit of the chip, third terminals formed on the third end portion and connected to the internal circuit, and fourth terminals formed on the fourth end portion and connected to the connection members.

Abstract: Since a 5 GHz-band broadband has a frequency twice that of 2.4 GHz, the parasitic capacitance greatly influences deterioration in isolation of a switching device used in this frequency region. Therefore, to improve isolation, a shunt FET is added to the device. The switching device also includes a protecting element that has a first n+-type region, an insulating region and a second n+-type region. This protecting element is connected in parallel between two electrodes of the shunt FET. Since electrostatic charges are discharged between the first and second n+-type regions, the electrostatic energy reaching an operation region of the shunt FET can be reduced without an increase in parasitic capacitance.

Abstract: The present integrated chip package provides a low cost package that is suitable for high density semiconductors that have high power dissipation. The integrated chip package includes at least one semiconductor chip having a first surface and a second surface. The first surface of the semiconductor chip is electrically coupled to an intermediate substrate via conductive bumps. The intermediate substrate is also electrically coupled to a package substrate via a plurality of bonding wires. The second surface of the semiconductor chip is thermally coupled to a heat sink to increase the power dissipation capacity of the integrated chip package.

Abstract: As conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.

Abstract: A multichip semiconductor package and method of making is provided that has a plurality of semiconductor chips fabricated in electrical isolation one from another integrally on a singular coextensive substrate useful for numerous and varied semiconductor chip applications. The semiconductor chips, instead of being singulated into a plurality of single-chip packages, are kept as integrally formed together and are thereafter electrically connected together so as to form a larger circuit. Encapsulation follows so as to form a single, multichip package. Common signals of the plurality of semiconductor chips are bussed together in electrical common across the substrate to a common electrode suitable for electrically providing the signal to another, external circuit, such as a PWB. The common bussing is achieved by conductive leads disposed across the substrate in pair sets having an extended portion that accommodates the common electrode in contact therewith.

Abstract: There is here disclosed a semiconductor device comprising a chip-mounting-member having a lead formed on its major surface, the lead having a thin film plated portion which covers a surface of a predetermined portion of the lead, a semiconductor chip having a bump formed on its major surface, and mounted on the chip-mounting-member by electrically connecting the bump to the lead via the plated portion, and an encapsulating-member formed between the semiconductor chip and the chip-mounting-member.

Abstract: The present invention allows multiple IC devices to be placed on the same substrate within a single BGA package. The invention requires minimum distances to be kept between electrical connections of the IC devices to maintain the electrical isolation, so that the devices can be operated at different voltage differentials. Signals between the devices can be connected externally from the package to each other utilizing galvanic isolation techniques. The invention provides the flexibility of choice for the customers to use isolation or not between the devices and takes up less PC board space because only a single package is used on the board.

Abstract: A semiconductor memory device for use in a semiconductor device with a chip on chip structure, which enables a memory specification to be selected and fixed, and improves design and production efficiencies. Bonding bumps corresponding to an input terminal and an output terminal of an interface circuit are connected to bonding bumps provided on another semiconductor device. Then, a polarity of a potential on a bus width varying terminal is fixed by the bonding bump provided on another semiconductor device, so that an isolated input/output specification is selected as a bus specification of the interface circuit and a bus width is selected.

Abstract: A discrete circuit component having an up-right circuit die with lateral electrical connections. The component comprises a substrate having a pair of electrically conductive traces, and a circuit die is planted between the pair of consecutive traces, wherein one electrode of the circuit die on the surface thereof vertical to the substrate is electrically bonded to one of the conductive trace immediately next thereto, while the other electrode of the circuit die on the opposite surface thereof vertical to the substrate is electrically bonded to the other of the pair of conductive traces immediately next thereto. A body of electrical insulation material hermetically seals the circuit die, and a pair of surface electrodes formed on the surface of the body of insulation material are each electrically connected to the corresponding one of the pair of electrically conductive traces extending from the circuit die.

Abstract: There is provided a coil and a method for fabricating the same. One embodiment of the coil includes a plurality of traces in one area of a substrate. Each trace has a first end located at a first side of the area, and a second end located at a second side of the area opposite the first side. A plurality of wires couples the plurality of traces to form a coil. Each wire couples the first end of one trace to the second end of another trace located adjacent to the one trace.

Abstract: A stacked semiconductor package including a plurality of stacked semiconductor devices on a substrate, and a method of forming the same. The semiconductor devices are stacked in an active surface-to-backside configuration. The top semiconductor die is flipped over to face the active surface of the semiconductor die directly below. An electrical connector can extend from a bond pad on the top semiconductor die to a redistribution circuit on the semiconductor die below. The redistribution circuit can be electrically connected to a substrate. Alternatively, an electrical connector extends from a bond pad on top semiconductor die to a bond pad on a substrate.

Abstract: The present invention relates to a packaging substrate with electrostatic discharge protection. The packaging substrate is disposed in a recess of a mold and comprises an outer wall electrically connecting an inner wall of the recess. A first copper-mesh layer and a second copper-mesh layer extend to the outer wall to electrically connect the inner wall of the recess. Static electric charges generated during the molding process are conducted via the first copper-mesh layer or the second copper-mesh layer to the inner wall of the recess and then conducted away. Therefore, the static electric charges generated during the molding process can be safely conducted away from the packaging substrate, preventing the dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.

Abstract: Through an improvement of module size increase due to mounting a single passive element on a substrate and an increase in the mounting cost, to provide a highly reliable, high performance and small sized semiconductor connection substrate which permits to integrate a variety of electronic parts such as capacitors, inductors and resistors in a high density with low cost.

Abstract: Temperature sensitive devices may be shielded from temperature generating devices on the same integrated circuit by appropriately providing a trench that thermally isolates the heat generating devices from the temperature sensitive devices. In one embodiment, the trench may be formed by a back side etch completely through an integrated circuit wafer. The resulting trench may be filled with a thermally insulating material.

Abstract: According to one exemplary embodiment, a structure comprises a laminate substrate having a top surface for receiving a semiconductor die. The structure further comprises an antenna element situated on the top surface of the laminate substrate, where the antenna element is coupled to a laminate substrate bond pad. For example, the antenna element may also be coupled to the laminate substrate bond pad by a trace on the top surface of the laminate substrate. According to this exemplary embodiment, the structure further comprises a bonding wire that provides an electrical connection between the laminate substrate bond pad and a semiconductor die bond pad. For example, the input impedance of the antenna element coupled to the laminate substrate bond pad may match the output impedance at the semiconductor die bond pad. The structure may further comprise a capacitor coupled to the antenna element.

Abstract: A high-frequency module of the invention includes an insulating substrate including a plurality of ceramic thin plates stacked in layers, and an insulating layer formed on the top surface of the insulating substrate. In the high-frequency module, a thin-film circuit is formed on the top surface of the insulating layer, and comprises a wiring pattern and an electrical part comprising a resistor and/or a capacitor. The wiring pattern is formed of a thin film. The electrical part is connected to the wiring pattern and is formed of a thin film. Therefore, the electrical part of the high-frequency module of the invention can be formed more precisely than an electrical part of a related high-frequency module. Consequently, it is possible to provide a high-frequency module having high performance.

Abstract: A mounting structure for mounting a photovoltaic element onto a metal body, which outputs a power generated by the photovoltaic element to the outside surface, and a method for mounting the photovoltaic element. In the mounting structure, the metal body has a first surface and a second surface opposite the first surface, in which the photovoltaic element is joined to the first surface and an electrically insulative material is joined to the second surface. A semiconductor element-mounting substrate for mounting a semiconductor element thereon comprising a retaining substrate having a circuit pattern, which has an electrode-joining portion for joining the semiconductor element electrode portion, an external terminal-fixing portion, and a groove between the electrode-joining portion and external-fixing portion, and a method for mounting the semiconductor element. In the mounting substrate, the electrode-joining portion is larger than the semiconductor element electrode portion.