Abstract: A system and methodology are disclosed for forming a passive layer on a conductive layer. The formation can be done during fabrication of an organic memory cell, where the passive layer generally includes a conductivity facilitating compound, such as copper sulfide (Cu2S). The conductivity facilitating compound is deposited onto the conductive layer via plasma enhanced chemical vapor deposition (PECVD) utilizing a metal organic (MO) precursor. The precursor facilitates depositing the conductivity facilitating compound in the absence of toxic hydrogen sulfide (H2S), and at a relatively low temperature and pressure (e.g., between about 400 to 600 K and 0.05 to 0.5 Pa., respectively). The deposition process can be monitored and controlled to facilitate, among other things, depositing the conductivity facilitating compound to a desired thickness.

Abstract: A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

Abstract: The present invention provides a bonding pad for an optical semiconductor device, including: a first supplementary adhesive layer made of Si3N4, being formed on a semiconductor substrate; a bonding pad layer made of benzocyclobutene, being formed on the first supplementary adhesive layer; a second supplementary adhesive layer made of Si3N4, being formed on the bonding pad layer; and a metallic electrode layer formed on the second supplementary adhesive layer.

Abstract: A GaN layer is formed on a sapphire substrate through an AlN buffer layer and doped with Mg to prepare a laminate (referred to as “GaN substrate”). A metal (Pt and Ni) electrode 50 nm thick is formed on the GaN substrate by (1) vapor deposition after the GaN substrate is heated to a temperature of 300° C. or by (2) vapor deposition while the GaN substrate is left at room temperature. (3) The electrode obtained in (2) is heated to 300° C. in a nitrogen atmosphere. The contact resistance of the electrode obtained in (1) is lower by two or three digits than that of the electrode obtained in (2) or (3). That is, the electric characteristic of the electrode obtained in (1) is improved greatly.

Abstract: Ohmic contact formation on p-type Silicon Carbide is disclosed. The formed contact includes an initial amorphous Carbon film layer converted to graphitic sp2 Carbon during an elevated temperature annealing sequence. Decreased annealing sequence temperature, reduced Silicon Carbide doping concentration and reduced specific resistivity in the formed ohmic contact are achieved with respect to a conventional p-type Silicon Carbide ohmic contact. Addition of a Boron carbide layer covering the p-type Silicon Carbide along with the sp2 Carbon is also disclosed. Ohmic contact improvement with increased annealing temperature up to an optimum temperature near 1000° C. is included. Addition of several metals including Aluminum, the optimum metal identified, over the Carbon layer is also included; many other of the identified metals provide Schottky rather than the desired ohmic contacts, however.

Abstract: In the fabrication of stacked vias, metal islands referred to as landing pads are introduced for the purpose of contact-connection between the vias that are arranged one above the other. The metal islands project laterally beyond the vias to a significant extent on account of the line shortening effect. The vias arranged in layers lying one above the other are laterally offset with respect to one another. The landing pad of the invention is configured as an interconnect running between the vias. On account of the line shortening effect, which is less critical for longer tracks, contact areas provided at the ends of the interconnect do not have to be chosen to be as large as the square contact areas of conventional metal islands and can therefore be accommodated to save more space on a circuit layout to be miniaturized. The shrink factor of such a semiconductor structure is increased.

Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).

Abstract: A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improves speed and efficiency of the integrated circuit. However, current air bridges must be kept short because typical aluminum conductors sag too much. Accordingly, one embodiment of the invention forms air-bridge conductors from an aluminum-beryllium alloy, which enhances stiffness and ultimately provides a 40-percent improvement in air-bridge lengths.

Abstract: A contact structure for group III-V and group II-VI compound semiconductor devices, generally used as a light emitting diode (LED), a laser diode (LD), or a photodiode (PD), comprising p-type and/or n-type conduction is disclosed. The contact structure comprises a stack of multiple layers of metals and transparent conducting oxide. The first layer of the contact structure is in direct contact to the semiconductor and comprises at least one of indium, tin, nickel, chromium and zinc, or an alloy or combination of layers thereof. The second layer of the structure is in direct contact to the first layer and comprises at least one of Indium Tin Oxide, Indium oxide, and Tin oxide, or a combination thereof. The optional third layer of the structure contacts the second layer and comprises at least one of Au, Al, Pt, Pd, Mo, Cr, Rh, Ti. The third layer may be a contact pad contacting a smaller portion of the second layer.

Abstract: A p-type contact electrode device in a ZnSe-based II-VI compound semiconductor, which electrode device uses, as a contact layer, a BeTe layer having a high p-type doping and a low lattice mismatching with a GaAs substrate to prevent oxidation in air. The device 2 includes a contact layer 5 composed of p-BeTe and a cap layer 4 is composed of p-ZnSe. The cap layer 4 is positioned on the contact layer 5 and an electrode 3 sits atop the cap layer. Preferably, the thickness of the cap layer is 30 to 70 Å and the electrode is composed of gold or gold is dispersed in the cap layer.

Abstract: For improving the light output, a light-emitting diode has at least one section of a light exit-side surface covered with a plurality of truncated pyramids. Light radiations, which are emitted by a light-generating layer, enter into the truncated pyramids through a base area and are efficiently coupled out of the sidewalls of the pyramids.

Abstract: A light-emitting element comprising a transparent electrode, a light-emitting layer, and a back electrode, on a substrate, wherein the light-emitting layer comprises photoluminescent metal oxide nanoparticles having an average particle size of 1 to 50 nm; and a method of producing the same.

Abstract: A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map.

Abstract: A method of reducing the specific contact resistivity of a metal to semiconductor interface between a metal contact and an InP semiconductor compound. The method includes the step of increasing the amount of the group V element (P) in the semiconductor compound so that the semiconductor compound is non-stoichiometric having an excess concentration of the group V element in an amount of at least 0.1% above stoichiometric levels.

Abstract: A method for selectively doping an organic semiconductor 1material in the region of a contact area 0.1formed between a contact and the organic semiconductor material disposed thereon includes introducing the dopant with the aid of nanoparticles, the nanoparticles being disposed in a manner adjoining the contact area and, as a result, only a very narrow region of the organic semiconductor material being doped. The field increase effected by the nanoparticles results in a further reduction of the contact resistance.

Abstract: A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

Abstract: A Group III nitride compound semiconductor light-emitting element (flip chip type light-emitting element) provided with a p-side electrode and an n-side electrode formed on one surface side, wherein the p-side electrode includes: a first metal layer containing Ag and formed on a p-type semiconductor layer; a protective film with which the first metal layer except a part region is covered; and a second metal layer not containing Ag and formed on the protective film.

Abstract: The present invention provides a bonding pad for an optical semiconductor device, including: a first supplementary adhesive layer made of Si3N4, being formed on a semiconductor substrate; a bonding pad layer made of benzocyclobutene, being formed on the first supplementary adhesive layer; a second supplementary adhesive layer made of Si3N4, being formed on the bonding pad layer; and a metallic electrode layer formed on the second supplementary adhesive layer.

Abstract: A nitride semiconductor laser device of high reliability such that the width of contact between a p-side ohmic electrode and a p-type contact layer is precisely controlled. The device comprises a substrate, an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer. All the layers are formed in order on the substrate. A ridge part including the uppermost layer of the p-type nitride semiconductor layer of the p-type nitride semiconductor layer i.e., a p-type contact layer is formed in the p-type nitride semiconductor layer. A p-side ohmic electrode is formed on the p-type contact layer of the top of the ridge part. A first insulating film having an opening over the top of the ridge part covers the side of the ridge part and the portion near the side of the ridge part. The p-side ohmic electrode is in contact with the p-type contact layer through the opening. A second insulating film is formed on the first insulating film.

Abstract: A light shield film is provided adjacent to an anode of an EL element that consists of the anode, an EL layer, and a cathode. The anode and the cathode are transparent or semitransparent to visible light and hence transmit EL light. With this structure, ambient light is absorbed by the light shield film and does not reach an observer. This prevents an external view from appearing on the observation surface.

Abstract: A semiconductor device with an ohmic contact and method of manufacturing the same is disclosed. The semiconductor device comprises a substrate, a p-type gallium nitride layer provided on said substrate, and a p-type indium gallium nitride (InxGa1-xN) layer provided on said p-type gallium nitride layer, so as to form an excellent interface with low ohmic contact resistance between a semiconductor and a metal layer. A light-emitting device with a low ohmic contact resistance and a method of manufacturing the same. Wherein the light emitting device comprises a substrate, a buffer layer on the substrate, an n-type cladding layer on the buffer layer, an active layer on the n-type cladding layer, a p-type cladding layer on the active layer, a p-type indium gallium nitride (InxGa1-xN) layer on the p-type cladding layer, and a metal layer on the indium gallium nitride (InxGa1-xN) layer to form an excellent interface with low ohmic contact resistance between a semiconductor and a metal layer.

Abstract: A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improves speed and efficiency of the integrated circuit. However, current air bridges must be kept short because typical aluminum conductors sag too much. Accordingly, one embodiment of the invention forms air-bridge conductors from an aluminum-beryllium alloy, which enhances stiffness and ultimately provides a 40-percent improvement in air-bridge lengths.

Abstract: A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.

Abstract: An ohmic contact to II-VI compound semiconductor device for lowering the contact resistance and increasing the efficiency and reliability of a photoelectric device. The method of manufacturing the ohmic contact to a II-VI compound semiconductor device comprises the steps of forming a II-VI compound semiconductor layer on the substrate, forming a mask layer with a contact via on the II-VI compound semiconductor layer, forming a metal-contact layer on the mask layer and II-VI compound semiconductor layer, and removing the metal-contact layer over the mask layer, wherein the remainder of the metal-contact layer forms the ohmic contact. In order to prevent oxidization of the metal-contact layer, a shield layer comprised of a noble metal can be disposed on the metal-contact layer.

Abstract: A nitride semiconductor device having high electrode contact properties is disclosed. The nitride semiconductor device includes a semiconductor layer made of a group III nitride semiconductor, and a metal electrode for supplying the semiconductor layer with a carrier. The device has a first contact layer made of a group III nitride semiconductor (AlxGa1−x)1−yInyN (0≦x≦1, 0<y≦1), laminated between the semiconductor layer and the metal electrode, and a group II element added thereto, and a second contact layer made of a group III nitride semiconductor Alx′Ga1−x′N (0≦x′≦1) and laminated between the first contact and the metal electrode.

Abstract: A vertical type power MOSFET made of silicon carbide includes a surface channel layer doped with nitrogen as dopant with a concentration equal to or less than 1×1015 cm−3. Accordingly, when a gate oxide film is formed on the surface channel layer, an amount of silicon nitride produced in the gate oxide film and at the interface between the gate oxide film and the surface channel layer becomes extremely small. As a result, carrier traps are prevented from being produced by silicon nitride, resulting in stable FET characteristics and high reliability to the gate oxide film.

Abstract: A first interlayer insulating film and an etching stopper film are sequentially formed on a semiconductor substrate with a surface area on which first wiring is formed. The etching stopper film is patterned so as to correspond to a pattern of via hole formed on the first interlayer insulating film and a pattern of forming a second wiring. A second interlayer insulating film is formed on the etching stopper film. For forming the second wiring, a wiring trench is formed by etching the second interlayer insulating film. Continuously, the via hole Is formed by etching the first interlayer insulating film while having the etching stopper film as a photomask. Conductive materials are laid in the via hole and the wiring trench so that the second wiring connected to the first wiring is formed.

Abstract: An electronic semiconductor device comprising a semiconductor base deposited on a semiconductor substrate by means of molecular beam epitaxy and source, drain and gate disposed on the base in a spaced relationghip to each other, the source and the drain comprising Pd/barrier/Au layers with the palladium layer being in contact with the device. The device is fabricated conventionally except the heat treating is at above about 170° C. for ¼-10 hours sufficient for the palladium layer to react with the base yielding reduced contact and access resistances and a narrower spacing between source and drain.

Abstract: Disclosed are an epitaxial structure for low ohmic contact resistance in p-type GaN-based semiconductors and a method for growing such a structure. A very high density of p-type doped GaAs or p-type graded AlxGa1−xAs (0<x≦1) is formed between an ohmic metal and a p-type GaN and subjected to crystal growth. The doped p-type GaAs or graded p-type AlxGa1−xAs reduces the potential barrier formed in the p-type GaN, thus significantly reducing the ohmic resistance. This structure can be applied for the improvement in the power efficiency and function of GaN-based optical devices and ultra-speed electronic devices.

Abstract: The invention provides an electrode material having the low contact resistance against a III-V group compound semiconductor, thereby realizing a light emitting device having a high luminance and driven at low voltages. The electrode material of the invention is applied to a III-V group compound semiconductor, which is expressed as a general formula of InxGayAlzN, where x+y+z=1, 0≦x≦1, 0≦y≦1, and 0≦z≦1, and doped with p-type impurities. The electrode material comprises an alloy of Au and at least one metal selected from the group consisting of Mg and Zn.

Abstract: Ohmic and rectifying contacts to a TaC layer on an n-type or p-type area of an SiC substrate are formed by depositing a WC layer over the TaC layer, followed by a metallic W layer. Such contacts are stable to at least 1150° C. Electrodes connect to the contacts either directly or via a protective bonding layer such as Pt or PtAu alloy through a dielectric layer.

Abstract: An ohmic electrode consists of a plurality of metal layers stacked on a p-type group III-V semiconductor crystal base material, in which a layer consisting of a group VB metal is stacked as a first layer as viewed from the side of the base material and a second layer containing Zn, for example, a third layer consisting of a refractory metal and a fourth layer consisting of Au are successively stacked on the first layer. Thus, a thin reaction layer can be formed by performing heating at a low temperature of not more than 400° C. simultaneously with formation of a p-type semiconductor electrode, for obtaining a metal electrode structure of a p-type group III-V semiconductor having an excellent ohmic characteristic.

Abstract: An electrode structure of compound semiconductor device. The compound semiconductor device has a substrate, an n-type layer over entire substrate, a mesa-like p-type layer on partial surface of the n-type layer, a transparent conductive layer on the mesa-like p-type layer; a p-contact formed on the transparent conductive layer and an n-contact formed on the exposed n-type layer. The n-contact comprises an enclosure portion compassing the p-contact, whereby the current flowed from the p-contact to the n-contact is uniform.

Abstract: Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an etchant solution or an oxidizing solution. The etchant solutions are aqueous solutions containing an etchant and a buffer. The etchant contains one or more etching agents selective to titanium nitride. The oxidizing solutions are aqueous solutions containing an oxidizer and a buffer. The oxidizer contains one or more oxidizing agents selective to titanium nitride. In either solution, i.e., etchant or oxidizing solution, the buffer contains one or more buffering agents. Titanium nitride layers planarized in accordance with the invention may be utilized in the production of integrated circuits, and various apparatus utilizing such integrated circuits.

Abstract: A method of forming titanium nitride barrier layers that are highly conformal, have high step coverage and low resistivity through a two stage deposition process is described. Low temperature deposition of titanium nitride barrier layer provides material of high conformity and good step coverage but of high resistivity. High temperature deposition of titanium nitride barrier layer yields material of low resistivity. Thus, a titanium nitride barrier layer deposited in separate steps at low temperature and high temperature by the method of the present invention is particularly suited for use in modern devices of increasing density that are characterized by narrow and deep contact holes.

Abstract: An electrode of a metal, which is one of Group IV and VI elements, is deposited on an n-type InxAlyGa1−x−yN layer. Alternatively, after an electrode material of carbon, germanium), selenium, rhodium, tellurium, iridium, zirconium, hafnium, copper, titanium nitride, tungsten nitride, molybdenum or titanium silicide, is deposited on an n-type InxAlyGa1−x−yN layer or a p-type InxAlyGa1−x−yN layer, an impurity for increasing the carrier concentration of the semiconductor layer is ion-implanted, and the annealing is carried out. Thus, it is possible to provide a light emitting semiconductor device, which has a low contact resistance and a sufficient bond strength to the InxAlyGa1−x−yN layer while maintaining the crystallinity of the InxAlyGa1−x−yN layer.

Abstract: An electrode for a light-emitting semiconductor device includes a light-permeable electrode formed to come into contact with the surface of the semiconductor, and a wire-bonding electrode that is in electrical contact with the light-permeable electrode and is formed to come into partial contact with the surface of the semiconductor with at least a region in contact with the semiconductor having a higher contact resistance per unit area with respect to the semiconductor than a region of the light-permeable electrode in contact with the semiconductor.

Abstract: A semiconductor device comprises an active element and contacts that permit low-resistance external electrical connections. The active element includes an active layer formed from group II-VI elements, an n-doped layer on one side of the active it layer, and a p-doped layer on the other side of the active layer. The p-doped layer is a ZnSe-based alloy or a ZnTe-based alloy. There are electrical contacts to the n-doped layer and to the p-doped layer. The electrical contact to the p-doped layer includes a graded-alloy contact layer in epitaxial contact with the p-doped layer and whose bandgap varies from about that of the p-doped layer adjacent the p-doped layer to about zero at a location remote from the p-doped layer. The graded-alloy contact layer is a HgZnSSe-based graded-composition alloy where the p-doped layer is a ZnSe-based alloy, or a HgZnSeTe-based graded-composition alloy where the p-doped layer is a ZnTe-based alloy.

Abstract: A p-contact that comprises a contact layer of a p-type Group III-nitride semiconductor having an exposed surface and an electrode layer of palladium (Pd) located on the exposed surface of the contact layer. The p-contact is made by providing a p-type Group III-nitride semiconductor contact layer having an exposed surface, and depositing an electrode layer of palladium on the exposed surface of the contact layer. Preferably, the p-contact is annealed for a prolonged annealing time after the electrode layer is deposited, and the exposed surface of the contact layer is etched using hydrofluoric acid (HF) before depositing the electrode layer.

Abstract: A semiconductor configuration with ohmic contact-connection includes a first and a second semiconductor region made of silicon carbide, each having a different conduction type. A first and a second contact region serve for contact-connection. The first contact region and the second contact region have an at least approximately identical material composition which is practically homogeneous within the respective contact region. A method is provided for contact-connecting n-conducting and p-conducting silicon carbide, in each case with at least approximately identical material.

Abstract: A circuit module includes at least one high temperature semiconductor chip having chip pads; a substrate having substrate metallization, the chip pads and the substrate metallization being substantially planar; and a deposited flexible pattern of electrical conductors capable of withstanding high temperatures and coupling selected chip pads and portions of the substrate metallization. The deposited flexible pattern of electrical conductors includes a plurality of integral interconnect segments, at least one of the integral interconnect segments including first and second leg portions and a shelf portion with the shelf portion being spaced apart from the at least one semiconductor chip and substrate and being coupled by the first leg portion to a selected chip pad and by the second leg portion to a selected portion of the substrate metallization.

Abstract: Aluminum containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.

Abstract: As will be described in more detail hereinafter, there is disclosed herein a titanium nitride diffusion barrier layer and associated method for use in non-silicon semiconductor technologies. In one aspect of the invention, a semiconductor device includes a non-silicon active surface. The improvement comprises an ohmic contact serving to form an external electrical connection to the non-silicon active surface in which the ohmic contact includes at least one layer consisting essentially of titanium nitride. In another aspect of the invention, a semiconductor ridge waveguide laser is disclosed which includes a semiconductor substrate and an active layer disposed on the substrate. A cladding layer is supported partially on the substrate and partially on the active layer. The cladding layer includes a ridge portion disposed in a confronting relationship with the active region.

Abstract: An object of the invention is to provide a light emitting diode which enables relatively easy fabrication of large-area displays and is applicable to thin, long life, low cost, full color displays too. The object is attained by a light emitting diode comprising a positive electrode, a negative electrode, an inorganic light emitting layer between the electrodes exhibiting at least electroluminescence, a high resistance inorganic electron transporting layer between the inorganic light emitting layer and the negative electrode, capable of blocking holes and having conduction paths for carrying electrons, and an inorganic hole transporting layer between the inorganic light emitting layer and the positive electrode, the inorganic hole transporting layer being a high resistance inorganic hole transporting layer capable of blocking electrons and having conduction paths for carrying holes.

Abstract: An electrode for a Group III nitride compound semiconductor having p-type conduction that has a double layer structure. The first metal electrode layer comprising, for example, nickel (Ni) and the second metal electrode layer comprising, for example, gold (Au). The Ni layer is formed on the Group III nitride compound semiconductor having p-type conduction, and the Au layer is formed on the Ni layer. Heat treatment changes or reverses the distribution of the elements Ni and Au. Namely, Au is distributed deeper into the Group III nitride compound semiconductor than is Ni. As a result, the resistivity of the electrode is lowered and its ohmic characteristics are improved as well as its adhesive strength.

Abstract: Disclosed is an electrode material for Group III-V compound semiconductor represented by the general formula In.sub.x Ga.sub.y Al.sub.z N (provided that x+y+z=1, 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, and 0.ltoreq.z.ltoreq.1) doped with a p-type impurity which is capable of obtaining good ohmic contact, and an electrode using the same, thereby making it possible to reduce a driving voltage of a device using the compound semiconductor. The electrode material is a metal comprising at least Ca and a noble metal, wherein the total amount of the weight of Ca and the noble metal is not less than 50% by weight and not more than 100% by weight based on the weight of the whole electrode material.

Abstract: A GaN group compound semiconductor device includes an electrode structure provided on a p-GaN group compound semiconductor layer, the electrode structure including: a first layer formed on the p-GaN group compound semiconductor layer, the first layer including a compound including a first metal element and Ga; and a second layer formed on the first layer, the second layer including the first metal element. The first layer contains substantially no nitrogen.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: On a substrate of n-type GaAs, an n-type cladding layer of n-type Zn.sub.0.9 Mg.sub.0.1 S.sub.0.13 Se.sub.0.87, an n-type light guiding layer of n-type ZnS.sub.0.06 Se.sub.0.94, an active layer of ZnCdSe and a p-type light guiding layer of p-type ZnS.sub.0.06 Se.sub.0.94 are successively formed. On the p-type light guiding layer, a p-type contact structure is formed. The p-type contact structure includes a first layer of p-type ZnS.sub.0.31 Se.sub.0.54 Te.sub.0.15, a second layer of ZnS.sub.0.47 Se.sub.0.28 Te.sub.0.25, a third layer of p-type ZnS.sub.0.65 Te.sub.0.35, a fourth layer of p-type ZnS.sub.0.5 Te.sub.0.5 and a fifth layer of p-type ZnTe.

Abstract: An enhancement mode periodic table group III-IV semiconductor field-effect transistor device is disclosed. The disclosed transistor includes single metallization for ohmic and Schottky barrier contacts, a permanent non photosensitive passivation layer (a layer which has also been used for masking purposes during fabrication of the transistor) and a gate element of small dimension and shaped cross section as needed to provide desirable microwave spectrum electrical characteristics. The transistor of the invention is fabricated from undoped semiconductor materials disposed in a layered wafer structure and selectively doped by ion implantation to achieve either a p-channel or an n-channel transistor. The semiconductor materials may include two, one or zero buffer layers in their layer structure. The disclosed transistor is of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.